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0010 #include <linux/module.h>
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/io.h>
0014 #include <uapi/linux/mdio.h>
0015 #include <linux/delay.h>
0016
0017 #include "../vfio_platform_private.h"
0018
0019 #define DMA_MR 0x3000
0020 #define MAC_VR 0x0110
0021 #define DMA_ISR 0x3008
0022 #define MAC_ISR 0x00b0
0023 #define PCS_MMD_SELECT 0xff
0024 #define MDIO_AN_INT 0x8002
0025 #define MDIO_AN_INTMASK 0x8001
0026
0027 static unsigned int xmdio_read(void __iomem *ioaddr, unsigned int mmd,
0028 unsigned int reg)
0029 {
0030 unsigned int mmd_address, value;
0031
0032 mmd_address = (mmd << 16) | ((reg) & 0xffff);
0033 iowrite32(mmd_address >> 8, ioaddr + (PCS_MMD_SELECT << 2));
0034 value = ioread32(ioaddr + ((mmd_address & 0xff) << 2));
0035 return value;
0036 }
0037
0038 static void xmdio_write(void __iomem *ioaddr, unsigned int mmd,
0039 unsigned int reg, unsigned int value)
0040 {
0041 unsigned int mmd_address;
0042
0043 mmd_address = (mmd << 16) | ((reg) & 0xffff);
0044 iowrite32(mmd_address >> 8, ioaddr + (PCS_MMD_SELECT << 2));
0045 iowrite32(value, ioaddr + ((mmd_address & 0xff) << 2));
0046 }
0047
0048 static int vfio_platform_amdxgbe_reset(struct vfio_platform_device *vdev)
0049 {
0050 struct vfio_platform_region *xgmac_regs = &vdev->regions[0];
0051 struct vfio_platform_region *xpcs_regs = &vdev->regions[1];
0052 u32 dma_mr_value, pcs_value, value;
0053 unsigned int count;
0054
0055 if (!xgmac_regs->ioaddr) {
0056 xgmac_regs->ioaddr =
0057 ioremap(xgmac_regs->addr, xgmac_regs->size);
0058 if (!xgmac_regs->ioaddr)
0059 return -ENOMEM;
0060 }
0061 if (!xpcs_regs->ioaddr) {
0062 xpcs_regs->ioaddr =
0063 ioremap(xpcs_regs->addr, xpcs_regs->size);
0064 if (!xpcs_regs->ioaddr)
0065 return -ENOMEM;
0066 }
0067
0068
0069 pcs_value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1);
0070 pcs_value |= MDIO_CTRL1_RESET;
0071 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1, pcs_value);
0072
0073 count = 50;
0074 do {
0075 msleep(20);
0076 pcs_value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_PCS,
0077 MDIO_CTRL1);
0078 } while ((pcs_value & MDIO_CTRL1_RESET) && --count);
0079
0080 if (pcs_value & MDIO_CTRL1_RESET)
0081 dev_warn(vdev->device, "%s: XGBE PHY reset timeout\n",
0082 __func__);
0083
0084
0085 value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1);
0086 value &= ~MDIO_AN_CTRL1_ENABLE;
0087 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1, value);
0088
0089
0090 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
0091
0092
0093 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INT, 0);
0094
0095
0096 dma_mr_value = ioread32(xgmac_regs->ioaddr + DMA_MR);
0097 dma_mr_value |= 0x1;
0098 iowrite32(dma_mr_value, xgmac_regs->ioaddr + DMA_MR);
0099
0100 usleep_range(10, 15);
0101
0102 count = 2000;
0103 while (--count && (ioread32(xgmac_regs->ioaddr + DMA_MR) & 1))
0104 usleep_range(500, 600);
0105
0106 if (!count)
0107 dev_warn(vdev->device, "%s: MAC SW reset failed\n", __func__);
0108
0109 return 0;
0110 }
0111
0112 module_vfio_reset_handler("amd,xgbe-seattle-v1a", vfio_platform_amdxgbe_reset);
0113
0114 MODULE_VERSION("0.1");
0115 MODULE_LICENSE("GPL v2");
0116 MODULE_AUTHOR("Eric Auger <eric.auger@linaro.org>");
0117 MODULE_DESCRIPTION("Reset support for AMD xgbe vfio platform device");