pci/hisilicon/hisi_acc_vfio_pci.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2021 HiSilicon Ltd. */
0003
0004 #ifndef HISI_ACC_VFIO_PCI_H
0005 #define HISI_ACC_VFIO_PCI_H
0006
0007 #include <linux/hisi_acc_qm.h>
0008
0009 #define MB_POLL_PERIOD_US       10
0010 #define MB_POLL_TIMEOUT_US      1000
0011 #define QM_CACHE_WB_START       0x204
0012 #define QM_CACHE_WB_DONE        0x208
0013 #define QM_MB_CMD_PAUSE_QM      0xe
0014 #define QM_ABNORMAL_INT_STATUS      0x100008
0015 #define QM_IFC_INT_STATUS       0x0028
0016 #define SEC_CORE_INT_STATUS     0x301008
0017 #define HPRE_HAC_INT_STATUS     0x301800
0018 #define HZIP_CORE_INT_STATUS        0x3010AC
0019 #define QM_QUE_ISO_CFG          0x301154
0020
0021 #define QM_VFT_CFG_RDY          0x10006c
0022 #define QM_VFT_CFG_OP_WR        0x100058
0023 #define QM_VFT_CFG_TYPE         0x10005c
0024 #define QM_VFT_CFG          0x100060
0025 #define QM_VFT_CFG_OP_ENABLE        0x100054
0026 #define QM_VFT_CFG_DATA_L       0x100064
0027 #define QM_VFT_CFG_DATA_H       0x100068
0028
0029 #define ERROR_CHECK_TIMEOUT     100
0030 #define CHECK_DELAY_TIME        100
0031
0032 #define QM_SQC_VFT_BASE_SHIFT_V2    28
0033 #define QM_SQC_VFT_BASE_MASK_V2     GENMASK(15, 0)
0034 #define QM_SQC_VFT_NUM_SHIFT_V2     45
0035 #define QM_SQC_VFT_NUM_MASK_V2      GENMASK(9, 0)
0036
0037 /* RW regs */
0038 #define QM_REGS_MAX_LEN     7
0039 #define QM_REG_ADDR_OFFSET  0x0004
0040
0041 #define QM_XQC_ADDR_OFFSET  32U
0042 #define QM_VF_AEQ_INT_MASK  0x0004
0043 #define QM_VF_EQ_INT_MASK   0x000c
0044 #define QM_IFC_INT_SOURCE_V 0x0020
0045 #define QM_IFC_INT_MASK     0x0024
0046 #define QM_IFC_INT_SET_V    0x002c
0047 #define QM_QUE_ISO_CFG_V    0x0030
0048 #define QM_PAGE_SIZE        0x0034
0049
0050 #define QM_EQC_DW0      0X8000
0051 #define QM_AEQC_DW0     0X8020
0052
0053 struct acc_vf_data {
0054 #define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state)
0055     /* QM match information */
0056 #define ACC_DEV_MAGIC   0XCDCDCDCDFEEDAACC
0057     u64 acc_magic;
0058     u32 qp_num;
0059     u32 dev_id;
0060     u32 que_iso_cfg;
0061     u32 qp_base;
0062     u32 vf_qm_state;
0063     /* QM reserved match information */
0064     u32 qm_rsv_state[3];
0065
0066     /* QM RW regs */
0067     u32 aeq_int_mask;
0068     u32 eq_int_mask;
0069     u32 ifc_int_source;
0070     u32 ifc_int_mask;
0071     u32 ifc_int_set;
0072     u32 page_size;
0073
0074     /* QM_EQC_DW has 7 regs */
0075     u32 qm_eqc_dw[7];
0076
0077     /* QM_AEQC_DW has 7 regs */
0078     u32 qm_aeqc_dw[7];
0079
0080     /* QM reserved 5 regs */
0081     u32 qm_rsv_regs[5];
0082     u32 padding;
0083     /* qm memory init information */
0084     u64 eqe_dma;
0085     u64 aeqe_dma;
0086     u64 sqc_dma;
0087     u64 cqc_dma;
0088 };
0089
0090 struct hisi_acc_vf_migration_file {
0091     struct file *filp;
0092     struct mutex lock;
0093     bool disabled;
0094
0095     struct acc_vf_data vf_data;
0096     size_t total_length;
0097 };
0098
0099 struct hisi_acc_vf_core_device {
0100     struct vfio_pci_core_device core_device;
0101     u8 deferred_reset:1;
0102     /* for migration state */
0103     struct mutex state_mutex;
0104     enum vfio_device_mig_state mig_state;
0105     struct pci_dev *pf_dev;
0106     struct pci_dev *vf_dev;
0107     struct hisi_qm *pf_qm;
0108     struct hisi_qm vf_qm;
0109     u32 vf_qm_state;
0110     int vf_id;
0111     /* for reset handler */
0112     spinlock_t reset_lock;
0113     struct hisi_acc_vf_migration_file *resuming_migf;
0114     struct hisi_acc_vf_migration_file *saving_migf;
0115 };
0116 #endif /* HISI_ACC_VFIO_PCI_H */