typec/tcpm/wcove.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * typec_wcove.c - WhiskeyCove PMIC USB Type-C PHY driver
0004  *
0005  * Copyright (C) 2017 Intel Corporation
0006  * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
0007  */
0008
0009 #include <linux/acpi.h>
0010 #include <linux/module.h>
0011 #include <linux/usb/tcpm.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/mfd/intel_soc_pmic.h>
0015
0016 /* Register offsets */
0017 #define WCOVE_CHGRIRQ0      0x4e09
0018
0019 #define USBC_CONTROL1       0x7001
0020 #define USBC_CONTROL2       0x7002
0021 #define USBC_CONTROL3       0x7003
0022 #define USBC_CC1_CTRL       0x7004
0023 #define USBC_CC2_CTRL       0x7005
0024 #define USBC_STATUS1        0x7007
0025 #define USBC_STATUS2        0x7008
0026 #define USBC_STATUS3        0x7009
0027 #define USBC_CC1        0x700a
0028 #define USBC_CC2        0x700b
0029 #define USBC_CC1_STATUS     0x700c
0030 #define USBC_CC2_STATUS     0x700d
0031 #define USBC_IRQ1       0x7015
0032 #define USBC_IRQ2       0x7016
0033 #define USBC_IRQMASK1       0x7017
0034 #define USBC_IRQMASK2       0x7018
0035 #define USBC_PDCFG2     0x701a
0036 #define USBC_PDCFG3     0x701b
0037 #define USBC_PDSTATUS       0x701c
0038 #define USBC_RXSTATUS       0x701d
0039 #define USBC_RXINFO     0x701e
0040 #define USBC_TXCMD      0x701f
0041 #define USBC_TXINFO     0x7020
0042 #define USBC_RX_DATA        0x7028
0043 #define USBC_TX_DATA        0x7047
0044
0045 /* Register bits */
0046
0047 #define USBC_CONTROL1_MODE_MASK     0x3
0048 #define   USBC_CONTROL1_MODE_SNK    0
0049 #define   USBC_CONTROL1_MODE_SNKACC 1
0050 #define   USBC_CONTROL1_MODE_SRC    2
0051 #define   USBC_CONTROL1_MODE_SRCACC 3
0052 #define   USBC_CONTROL1_MODE_DRP    4
0053 #define   USBC_CONTROL1_MODE_DRPACC 5
0054 #define   USBC_CONTROL1_MODE_TEST   7
0055 #define USBC_CONTROL1_CURSRC_MASK   0xc
0056 #define   USBC_CONTROL1_CURSRC_UA_0 (0 << 3)
0057 #define   USBC_CONTROL1_CURSRC_UA_80    (1 << 3)
0058 #define   USBC_CONTROL1_CURSRC_UA_180   (2 << 3)
0059 #define   USBC_CONTROL1_CURSRC_UA_330   (3 << 3)
0060 #define USBC_CONTROL1_DRPTOGGLE_RANDOM  0xe0
0061
0062 #define USBC_CONTROL2_UNATT_SNK     BIT(0)
0063 #define USBC_CONTROL2_UNATT_SRC     BIT(1)
0064 #define USBC_CONTROL2_DIS_ST        BIT(2)
0065
0066 #define USBC_CONTROL3_DET_DIS       BIT(0)
0067 #define USBC_CONTROL3_PD_DIS        BIT(1)
0068 #define USBC_CONTROL3_RESETPHY      BIT(2)
0069
0070 #define USBC_CC_CTRL_PU_EN      BIT(0)
0071 #define USBC_CC_CTRL_VCONN_EN       BIT(1)
0072 #define USBC_CC_CTRL_TX_EN      BIT(2)
0073 #define USBC_CC_CTRL_PD_EN      BIT(3)
0074 #define USBC_CC_CTRL_CDET_EN        BIT(4)
0075 #define USBC_CC_CTRL_RDET_EN        BIT(5)
0076 #define USBC_CC_CTRL_ADC_EN     BIT(6)
0077 #define USBC_CC_CTRL_VBUSOK     BIT(7)
0078
0079 #define USBC_STATUS1_DET_ONGOING    BIT(6)
0080 #define USBC_STATUS1_RSLT(r)        ((r) & 0xf)
0081 #define USBC_RSLT_NOTHING       0
0082 #define USBC_RSLT_SRC_DEFAULT       1
0083 #define USBC_RSLT_SRC_1_5A      2
0084 #define USBC_RSLT_SRC_3_0A      3
0085 #define USBC_RSLT_SNK           4
0086 #define USBC_RSLT_DEBUG_ACC     5
0087 #define USBC_RSLT_AUDIO_ACC     6
0088 #define USBC_RSLT_UNDEF         15
0089 #define USBC_STATUS1_ORIENT(r)      (((r) >> 4) & 0x3)
0090 #define USBC_ORIENT_NORMAL      1
0091 #define USBC_ORIENT_REVERSE     2
0092
0093 #define USBC_STATUS2_VBUS_REQ       BIT(5)
0094
0095 #define UCSC_CC_STATUS_SNK_RP       BIT(0)
0096 #define UCSC_CC_STATUS_PWRDEFSNK    BIT(1)
0097 #define UCSC_CC_STATUS_PWR_1P5A_SNK BIT(2)
0098 #define UCSC_CC_STATUS_PWR_3A_SNK   BIT(3)
0099 #define UCSC_CC_STATUS_SRC_RP       BIT(4)
0100 #define UCSC_CC_STATUS_RX(r)        (((r) >> 5) & 0x3)
0101 #define   USBC_CC_STATUS_RD     1
0102 #define   USBC_CC_STATUS_RA     2
0103
0104 #define USBC_IRQ1_ADCDONE1      BIT(2)
0105 #define USBC_IRQ1_OVERTEMP      BIT(1)
0106 #define USBC_IRQ1_SHORT         BIT(0)
0107
0108 #define USBC_IRQ2_CC_CHANGE     BIT(7)
0109 #define USBC_IRQ2_RX_PD         BIT(6)
0110 #define USBC_IRQ2_RX_HR         BIT(5)
0111 #define USBC_IRQ2_RX_CR         BIT(4)
0112 #define USBC_IRQ2_TX_SUCCESS        BIT(3)
0113 #define USBC_IRQ2_TX_FAIL       BIT(2)
0114
0115 #define USBC_IRQMASK1_ALL   (USBC_IRQ1_ADCDONE1 | USBC_IRQ1_OVERTEMP | \
0116                  USBC_IRQ1_SHORT)
0117
0118 #define USBC_IRQMASK2_ALL   (USBC_IRQ2_CC_CHANGE | USBC_IRQ2_RX_PD | \
0119                  USBC_IRQ2_RX_HR | USBC_IRQ2_RX_CR | \
0120                  USBC_IRQ2_TX_SUCCESS | USBC_IRQ2_TX_FAIL)
0121
0122 #define USBC_PDCFG2_SOP         BIT(0)
0123 #define USBC_PDCFG2_SOP_P       BIT(1)
0124 #define USBC_PDCFG2_SOP_PP      BIT(2)
0125 #define USBC_PDCFG2_SOP_P_DEBUG     BIT(3)
0126 #define USBC_PDCFG2_SOP_PP_DEBUG    BIT(4)
0127
0128 #define USBC_PDCFG3_DATAROLE_SHIFT  1
0129 #define USBC_PDCFG3_SOP_SHIFT       2
0130
0131 #define USBC_RXSTATUS_RXCLEAR       BIT(0)
0132 #define USBC_RXSTATUS_RXDATA        BIT(7)
0133
0134 #define USBC_RXINFO_RXBYTES(i)      (((i) >> 3) & 0x1f)
0135
0136 #define USBC_TXCMD_BUF_RDY      BIT(0)
0137 #define USBC_TXCMD_START        BIT(1)
0138 #define USBC_TXCMD_NOP          (0 << 5)
0139 #define USBC_TXCMD_MSG          (1 << 5)
0140 #define USBC_TXCMD_CR           (2 << 5)
0141 #define USBC_TXCMD_HR           (3 << 5)
0142 #define USBC_TXCMD_BIST         (4 << 5)
0143
0144 #define USBC_TXINFO_RETRIES(d)      (d << 3)
0145
0146 struct wcove_typec {
0147     struct mutex lock; /* device lock */
0148     struct device *dev;
0149     struct regmap *regmap;
0150     guid_t guid;
0151
0152     bool vbus;
0153
0154     struct tcpc_dev tcpc;
0155     struct tcpm_port *tcpm;
0156 };
0157
0158 #define tcpc_to_wcove(_tcpc_) container_of(_tcpc_, struct wcove_typec, tcpc)
0159
0160 enum wcove_typec_func {
0161     WCOVE_FUNC_DRIVE_VBUS = 1,
0162     WCOVE_FUNC_ORIENTATION,
0163     WCOVE_FUNC_ROLE,
0164     WCOVE_FUNC_DRIVE_VCONN,
0165 };
0166
0167 enum wcove_typec_orientation {
0168     WCOVE_ORIENTATION_NORMAL,
0169     WCOVE_ORIENTATION_REVERSE,
0170 };
0171
0172 enum wcove_typec_role {
0173     WCOVE_ROLE_HOST,
0174     WCOVE_ROLE_DEVICE,
0175 };
0176
0177 #define WCOVE_DSM_UUID      "482383f0-2876-4e49-8685-db66211af037"
0178
0179 static int wcove_typec_func(struct wcove_typec *wcove,
0180                 enum wcove_typec_func func, int param)
0181 {
0182     union acpi_object *obj;
0183     union acpi_object tmp;
0184     union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
0185
0186     tmp.type = ACPI_TYPE_INTEGER;
0187     tmp.integer.value = param;
0188
0189     obj = acpi_evaluate_dsm(ACPI_HANDLE(wcove->dev), &wcove->guid, 1, func,
0190                 &argv4);
0191     if (!obj) {
0192         dev_err(wcove->dev, "%s: failed to evaluate _DSM\n", __func__);
0193         return -EIO;
0194     }
0195
0196     ACPI_FREE(obj);
0197     return 0;
0198 }
0199
0200 static int wcove_init(struct tcpc_dev *tcpc)
0201 {
0202     struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
0203     int ret;
0204
0205     ret = regmap_write(wcove->regmap, USBC_CONTROL1, 0);
0206     if (ret)
0207         return ret;
0208
0209     /* Unmask everything */
0210     ret = regmap_write(wcove->regmap, USBC_IRQMASK1, 0);
0211     if (ret)
0212         return ret;
0213
0214     return regmap_write(wcove->regmap, USBC_IRQMASK2, 0);
0215 }
0216
0217 static int wcove_get_vbus(struct tcpc_dev *tcpc)
0218 {
0219     struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
0220     unsigned int cc1ctrl;
0221     int ret;
0222
0223     ret = regmap_read(wcove->regmap, USBC_CC1_CTRL, &cc1ctrl);
0224     if (ret)
0225         return ret;
0226
0227     wcove->vbus = !!(cc1ctrl & USBC_CC_CTRL_VBUSOK);
0228
0229     return wcove->vbus;
0230 }
0231
0232 static int wcove_set_vbus(struct tcpc_dev *tcpc, bool on, bool sink)
0233 {
0234     struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
0235
0236     return wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VBUS, on);
0237 }
0238
0239 static int wcove_set_vconn(struct tcpc_dev *tcpc, bool on)
0240 {
0241     struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
0242
0243     return wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, on);
0244 }
0245
0246 static enum typec_cc_status wcove_to_typec_cc(unsigned int cc)
0247 {
0248     if (cc & UCSC_CC_STATUS_SNK_RP) {
0249         if (cc & UCSC_CC_STATUS_PWRDEFSNK)
0250             return TYPEC_CC_RP_DEF;
0251         else if (cc & UCSC_CC_STATUS_PWR_1P5A_SNK)
0252             return TYPEC_CC_RP_1_5;
0253         else if (cc & UCSC_CC_STATUS_PWR_3A_SNK)
0254             return TYPEC_CC_RP_3_0;
0255     } else {
0256         switch (UCSC_CC_STATUS_RX(cc)) {
0257         case USBC_CC_STATUS_RD:
0258             return TYPEC_CC_RD;
0259         case USBC_CC_STATUS_RA:
0260             return TYPEC_CC_RA;
0261         default:
0262             break;
0263         }
0264     }
0265     return TYPEC_CC_OPEN;
0266 }
0267
0268 static int wcove_get_cc(struct tcpc_dev *tcpc, enum typec_cc_status *cc1,
0269             enum typec_cc_status *cc2)
0270 {
0271     struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
0272     unsigned int cc1_status;
0273     unsigned int cc2_status;
0274     int ret;
0275
0276     ret = regmap_read(wcove->regmap, USBC_CC1_STATUS, &cc1_status);
0277     if (ret)
0278         return ret;
0279
0280     ret = regmap_read(wcove->regmap, USBC_CC2_STATUS, &cc2_status);
0281     if (ret)
0282         return ret;
0283
0284     *cc1 = wcove_to_typec_cc(cc1_status);
0285     *cc2 = wcove_to_typec_cc(cc2_status);
0286
0287     return 0;
0288 }
0289
0290 static int wcove_set_cc(struct tcpc_dev *tcpc, enum typec_cc_status cc)
0291 {
0292     struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
0293     unsigned int ctrl;
0294
0295     switch (cc) {
0296     case TYPEC_CC_RD:
0297         ctrl = USBC_CONTROL1_MODE_SNK;
0298         break;
0299     case TYPEC_CC_RP_DEF:
0300         ctrl = USBC_CONTROL1_CURSRC_UA_80 | USBC_CONTROL1_MODE_SRC;
0301         break;
0302     case TYPEC_CC_RP_1_5:
0303         ctrl = USBC_CONTROL1_CURSRC_UA_180 | USBC_CONTROL1_MODE_SRC;
0304         break;
0305     case TYPEC_CC_RP_3_0:
0306         ctrl = USBC_CONTROL1_CURSRC_UA_330 | USBC_CONTROL1_MODE_SRC;
0307         break;
0308     case TYPEC_CC_OPEN:
0309         ctrl = 0;
0310         break;
0311     default:
0312         return -EINVAL;
0313     }
0314
0315     return regmap_write(wcove->regmap, USBC_CONTROL1, ctrl);
0316 }
0317
0318 static int wcove_set_polarity(struct tcpc_dev *tcpc, enum typec_cc_polarity pol)
0319 {
0320     struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
0321
0322     return wcove_typec_func(wcove, WCOVE_FUNC_ORIENTATION, pol);
0323 }
0324
0325 static int wcove_set_current_limit(struct tcpc_dev *tcpc, u32 max_ma, u32 mv)
0326 {
0327     return 0;
0328 }
0329
0330 static int wcove_set_roles(struct tcpc_dev *tcpc, bool attached,
0331                enum typec_role role, enum typec_data_role data)
0332 {
0333     struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
0334     unsigned int val;
0335     int ret;
0336
0337     ret = wcove_typec_func(wcove, WCOVE_FUNC_ROLE, data == TYPEC_HOST ?
0338                    WCOVE_ROLE_HOST : WCOVE_ROLE_DEVICE);
0339     if (ret)
0340         return ret;
0341
0342     val = role;
0343     val |= data << USBC_PDCFG3_DATAROLE_SHIFT;
0344     val |= PD_REV20 << USBC_PDCFG3_SOP_SHIFT;
0345
0346     return regmap_write(wcove->regmap, USBC_PDCFG3, val);
0347 }
0348
0349 static int wcove_set_pd_rx(struct tcpc_dev *tcpc, bool on)
0350 {
0351     struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
0352
0353     return regmap_write(wcove->regmap, USBC_PDCFG2,
0354                 on ? USBC_PDCFG2_SOP : 0);
0355 }
0356
0357 static int wcove_pd_transmit(struct tcpc_dev *tcpc,
0358                  enum tcpm_transmit_type type,
0359                  const struct pd_message *msg,
0360                  unsigned int negotiated_rev)
0361 {
0362     struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
0363     unsigned int info = 0;
0364     unsigned int cmd;
0365     int ret;
0366
0367     ret = regmap_read(wcove->regmap, USBC_TXCMD, &cmd);
0368     if (ret)
0369         return ret;
0370
0371     if (!(cmd & USBC_TXCMD_BUF_RDY)) {
0372         dev_warn(wcove->dev, "%s: Last transmission still ongoing!",
0373              __func__);
0374         return -EBUSY;
0375     }
0376
0377     if (msg) {
0378         const u8 *data = (void *)msg;
0379         int i;
0380
0381         for (i = 0; i < pd_header_cnt_le(msg->header) * 4 + 2; i++) {
0382             ret = regmap_write(wcove->regmap, USBC_TX_DATA + i,
0383                        data[i]);
0384             if (ret)
0385                 return ret;
0386         }
0387     }
0388
0389     switch (type) {
0390     case TCPC_TX_SOP:
0391     case TCPC_TX_SOP_PRIME:
0392     case TCPC_TX_SOP_PRIME_PRIME:
0393     case TCPC_TX_SOP_DEBUG_PRIME:
0394     case TCPC_TX_SOP_DEBUG_PRIME_PRIME:
0395         info = type + 1;
0396         cmd = USBC_TXCMD_MSG;
0397         break;
0398     case TCPC_TX_HARD_RESET:
0399         cmd = USBC_TXCMD_HR;
0400         break;
0401     case TCPC_TX_CABLE_RESET:
0402         cmd = USBC_TXCMD_CR;
0403         break;
0404     case TCPC_TX_BIST_MODE_2:
0405         cmd = USBC_TXCMD_BIST;
0406         break;
0407     default:
0408         return -EINVAL;
0409     }
0410
0411     /* NOTE Setting maximum number of retries (7) */
0412     ret = regmap_write(wcove->regmap, USBC_TXINFO,
0413                info | USBC_TXINFO_RETRIES(7));
0414     if (ret)
0415         return ret;
0416
0417     return regmap_write(wcove->regmap, USBC_TXCMD, cmd | USBC_TXCMD_START);
0418 }
0419
0420 static int wcove_start_toggling(struct tcpc_dev *tcpc,
0421                 enum typec_port_type port_type,
0422                 enum typec_cc_status cc)
0423 {
0424     struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
0425     unsigned int usbc_ctrl;
0426
0427     if (port_type != TYPEC_PORT_DRP)
0428         return -EOPNOTSUPP;
0429
0430     usbc_ctrl = USBC_CONTROL1_MODE_DRP | USBC_CONTROL1_DRPTOGGLE_RANDOM;
0431
0432     switch (cc) {
0433     case TYPEC_CC_RP_1_5:
0434         usbc_ctrl |= USBC_CONTROL1_CURSRC_UA_180;
0435         break;
0436     case TYPEC_CC_RP_3_0:
0437         usbc_ctrl |= USBC_CONTROL1_CURSRC_UA_330;
0438         break;
0439     default:
0440         usbc_ctrl |= USBC_CONTROL1_CURSRC_UA_80;
0441         break;
0442     }
0443
0444     return regmap_write(wcove->regmap, USBC_CONTROL1, usbc_ctrl);
0445 }
0446
0447 static int wcove_read_rx_buffer(struct wcove_typec *wcove, void *msg)
0448 {
0449     unsigned int info;
0450     int ret;
0451     int i;
0452
0453     ret = regmap_read(wcove->regmap, USBC_RXINFO, &info);
0454     if (ret)
0455         return ret;
0456
0457     /* FIXME: Check that USBC_RXINFO_RXBYTES(info) matches the header */
0458
0459     for (i = 0; i < USBC_RXINFO_RXBYTES(info); i++) {
0460         ret = regmap_read(wcove->regmap, USBC_RX_DATA + i, msg + i);
0461         if (ret)
0462             return ret;
0463     }
0464
0465     return regmap_write(wcove->regmap, USBC_RXSTATUS,
0466                 USBC_RXSTATUS_RXCLEAR);
0467 }
0468
0469 static irqreturn_t wcove_typec_irq(int irq, void *data)
0470 {
0471     struct wcove_typec *wcove = data;
0472     unsigned int usbc_irq1 = 0;
0473     unsigned int usbc_irq2 = 0;
0474     unsigned int cc1ctrl;
0475     int ret;
0476
0477     mutex_lock(&wcove->lock);
0478
0479     /* Read.. */
0480     ret = regmap_read(wcove->regmap, USBC_IRQ1, &usbc_irq1);
0481     if (ret)
0482         goto err;
0483
0484     ret = regmap_read(wcove->regmap, USBC_IRQ2, &usbc_irq2);
0485     if (ret)
0486         goto err;
0487
0488     ret = regmap_read(wcove->regmap, USBC_CC1_CTRL, &cc1ctrl);
0489     if (ret)
0490         goto err;
0491
0492     if (!wcove->tcpm)
0493         goto err;
0494
0495     /* ..check.. */
0496     if (usbc_irq1 & USBC_IRQ1_OVERTEMP) {
0497         dev_err(wcove->dev, "VCONN Switch Over Temperature!\n");
0498         wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, false);
0499         /* REVISIT: Report an error? */
0500     }
0501
0502     if (usbc_irq1 & USBC_IRQ1_SHORT) {
0503         dev_err(wcove->dev, "VCONN Switch Short Circuit!\n");
0504         wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, false);
0505         /* REVISIT: Report an error? */
0506     }
0507
0508     if (wcove->vbus != !!(cc1ctrl & USBC_CC_CTRL_VBUSOK))
0509         tcpm_vbus_change(wcove->tcpm);
0510
0511     /* REVISIT: See if tcpm code can be made to consider Type-C HW FSMs */
0512     if (usbc_irq2 & USBC_IRQ2_CC_CHANGE)
0513         tcpm_cc_change(wcove->tcpm);
0514
0515     if (usbc_irq2 & USBC_IRQ2_RX_PD) {
0516         unsigned int status;
0517
0518         /*
0519          * FIXME: Need to check if TX is ongoing and report
0520          * TX_DIREGARDED if needed?
0521          */
0522
0523         ret = regmap_read(wcove->regmap, USBC_RXSTATUS, &status);
0524         if (ret)
0525             goto err;
0526
0527         /* Flush all buffers */
0528         while (status & USBC_RXSTATUS_RXDATA) {
0529             struct pd_message msg;
0530
0531             ret = wcove_read_rx_buffer(wcove, &msg);
0532             if (ret) {
0533                 dev_err(wcove->dev, "%s: RX read failed\n",
0534                     __func__);
0535                 goto err;
0536             }
0537
0538             tcpm_pd_receive(wcove->tcpm, &msg);
0539
0540             ret = regmap_read(wcove->regmap, USBC_RXSTATUS,
0541                       &status);
0542             if (ret)
0543                 goto err;
0544         }
0545     }
0546
0547     if (usbc_irq2 & USBC_IRQ2_RX_HR)
0548         tcpm_pd_hard_reset(wcove->tcpm);
0549
0550     /* REVISIT: if (usbc_irq2 & USBC_IRQ2_RX_CR) */
0551
0552     if (usbc_irq2 & USBC_IRQ2_TX_SUCCESS)
0553         tcpm_pd_transmit_complete(wcove->tcpm, TCPC_TX_SUCCESS);
0554
0555     if (usbc_irq2 & USBC_IRQ2_TX_FAIL)
0556         tcpm_pd_transmit_complete(wcove->tcpm, TCPC_TX_FAILED);
0557
0558 err:
0559     /* ..and clear. */
0560     if (usbc_irq1) {
0561         ret = regmap_write(wcove->regmap, USBC_IRQ1, usbc_irq1);
0562         if (ret)
0563             dev_WARN(wcove->dev, "%s failed to clear IRQ1\n",
0564                  __func__);
0565     }
0566
0567     if (usbc_irq2) {
0568         ret = regmap_write(wcove->regmap, USBC_IRQ2, usbc_irq2);
0569         if (ret)
0570             dev_WARN(wcove->dev, "%s failed to clear IRQ2\n",
0571                  __func__);
0572     }
0573
0574     /* REVISIT: Clear WhiskeyCove CHGR Type-C interrupt */
0575     regmap_write(wcove->regmap, WCOVE_CHGRIRQ0, BIT(5));
0576
0577     mutex_unlock(&wcove->lock);
0578     return IRQ_HANDLED;
0579 }
0580
0581 /*
0582  * The following power levels should be safe to use with Joule board.
0583  */
0584 static const u32 src_pdo[] = {
0585     PDO_FIXED(5000, 1500, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |
0586           PDO_FIXED_USB_COMM),
0587 };
0588
0589 static const u32 snk_pdo[] = {
0590     PDO_FIXED(5000, 500, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |
0591           PDO_FIXED_USB_COMM),
0592     PDO_VAR(5000, 12000, 3000),
0593 };
0594
0595 static const struct property_entry wcove_props[] = {
0596     PROPERTY_ENTRY_STRING("data-role", "dual"),
0597     PROPERTY_ENTRY_STRING("power-role", "dual"),
0598     PROPERTY_ENTRY_STRING("try-power-role", "sink"),
0599     PROPERTY_ENTRY_U32_ARRAY("source-pdos", src_pdo),
0600     PROPERTY_ENTRY_U32_ARRAY("sink-pdos", snk_pdo),
0601     PROPERTY_ENTRY_U32("op-sink-microwatt", 15000000),
0602     { }
0603 };
0604
0605 static int wcove_typec_probe(struct platform_device *pdev)
0606 {
0607     struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
0608     struct wcove_typec *wcove;
0609     int irq;
0610     int ret;
0611
0612     wcove = devm_kzalloc(&pdev->dev, sizeof(*wcove), GFP_KERNEL);
0613     if (!wcove)
0614         return -ENOMEM;
0615
0616     mutex_init(&wcove->lock);
0617     wcove->dev = &pdev->dev;
0618     wcove->regmap = pmic->regmap;
0619
0620     irq = platform_get_irq(pdev, 0);
0621     if (irq < 0)
0622         return irq;
0623
0624     irq = regmap_irq_get_virq(pmic->irq_chip_data_chgr, irq);
0625     if (irq < 0)
0626         return irq;
0627
0628     ret = guid_parse(WCOVE_DSM_UUID, &wcove->guid);
0629     if (ret)
0630         return ret;
0631
0632     if (!acpi_check_dsm(ACPI_HANDLE(&pdev->dev), &wcove->guid, 0, 0x1f)) {
0633         dev_err(&pdev->dev, "Missing _DSM functions\n");
0634         return -ENODEV;
0635     }
0636
0637     wcove->tcpc.init = wcove_init;
0638     wcove->tcpc.get_vbus = wcove_get_vbus;
0639     wcove->tcpc.set_vbus = wcove_set_vbus;
0640     wcove->tcpc.set_cc = wcove_set_cc;
0641     wcove->tcpc.get_cc = wcove_get_cc;
0642     wcove->tcpc.set_polarity = wcove_set_polarity;
0643     wcove->tcpc.set_vconn = wcove_set_vconn;
0644     wcove->tcpc.set_current_limit = wcove_set_current_limit;
0645     wcove->tcpc.start_toggling = wcove_start_toggling;
0646
0647     wcove->tcpc.set_pd_rx = wcove_set_pd_rx;
0648     wcove->tcpc.set_roles = wcove_set_roles;
0649     wcove->tcpc.pd_transmit = wcove_pd_transmit;
0650
0651     wcove->tcpc.fwnode = fwnode_create_software_node(wcove_props, NULL);
0652     if (IS_ERR(wcove->tcpc.fwnode))
0653         return PTR_ERR(wcove->tcpc.fwnode);
0654
0655     wcove->tcpm = tcpm_register_port(wcove->dev, &wcove->tcpc);
0656     if (IS_ERR(wcove->tcpm)) {
0657         fwnode_remove_software_node(wcove->tcpc.fwnode);
0658         return PTR_ERR(wcove->tcpm);
0659     }
0660
0661     ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
0662                     wcove_typec_irq, IRQF_ONESHOT,
0663                     "wcove_typec", wcove);
0664     if (ret) {
0665         tcpm_unregister_port(wcove->tcpm);
0666         fwnode_remove_software_node(wcove->tcpc.fwnode);
0667         return ret;
0668     }
0669
0670     platform_set_drvdata(pdev, wcove);
0671     return 0;
0672 }
0673
0674 static int wcove_typec_remove(struct platform_device *pdev)
0675 {
0676     struct wcove_typec *wcove = platform_get_drvdata(pdev);
0677     unsigned int val;
0678
0679     /* Mask everything */
0680     regmap_read(wcove->regmap, USBC_IRQMASK1, &val);
0681     regmap_write(wcove->regmap, USBC_IRQMASK1, val | USBC_IRQMASK1_ALL);
0682     regmap_read(wcove->regmap, USBC_IRQMASK2, &val);
0683     regmap_write(wcove->regmap, USBC_IRQMASK2, val | USBC_IRQMASK2_ALL);
0684
0685     tcpm_unregister_port(wcove->tcpm);
0686     fwnode_remove_software_node(wcove->tcpc.fwnode);
0687
0688     return 0;
0689 }
0690
0691 static struct platform_driver wcove_typec_driver = {
0692     .driver = {
0693         .name       = "bxt_wcove_usbc",
0694     },
0695     .probe          = wcove_typec_probe,
0696     .remove         = wcove_typec_remove,
0697 };
0698
0699 module_platform_driver(wcove_typec_driver);
0700
0701 MODULE_AUTHOR("Intel Corporation");
0702 MODULE_LICENSE("GPL v2");
0703 MODULE_DESCRIPTION("WhiskeyCove PMIC USB Type-C PHY driver");
0704 MODULE_ALIAS("platform:bxt_wcove_usbc");