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0001 /* SPDX-License-Identifier: GPL-2.0+ */ 0002 /************************************************************************ 0003 * 0004 * 16654.H Definitions for 16C654 UART used on EdgePorts 0005 * 0006 * Copyright (C) 1998 Inside Out Networks, Inc. 0007 * 0008 ************************************************************************/ 0009 0010 #if !defined(_16654_H) 0011 #define _16654_H 0012 0013 /************************************************************************ 0014 * 0015 * D e f i n e s / T y p e d e f s 0016 * 0017 ************************************************************************/ 0018 0019 // 0020 // UART register numbers 0021 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and 0022 // above are used internally to indicate that we must enable access 0023 // to them via LCR bit 0x80 or LCR = 0xBF. 0024 // The register number sent to the Edgeport is then (x & 0x7). 0025 // 0026 // Driver must not access registers that affect operation of the 0027 // the EdgePort firmware -- that includes THR, RHR, IER, FCR. 0028 0029 0030 #define THR 0 // ! Transmit Holding Register (Write) 0031 #define RDR 0 // ! Receive Holding Register (Read) 0032 #define IER 1 // ! Interrupt Enable Register 0033 #define FCR 2 // ! Fifo Control Register (Write) 0034 #define ISR 2 // Interrupt Status Register (Read) 0035 #define LCR 3 // Line Control Register 0036 #define MCR 4 // Modem Control Register 0037 #define LSR 5 // Line Status Register 0038 #define MSR 6 // Modem Status Register 0039 #define SPR 7 // ScratchPad Register 0040 #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB 0041 #define DLM 9 // Bank2[ 1 ] Divisor Latch MSB 0042 #define EFR 10 // Bank2[ 2 ] Extended Function Register 0043 //efine unused 11 // Bank2[ 3 ] 0044 #define XON1 12 // Bank2[ 4 ] Xon-1 0045 #define XON2 13 // Bank2[ 5 ] Xon-2 0046 #define XOFF1 14 // Bank2[ 6 ] Xoff-1 0047 #define XOFF2 15 // Bank2[ 7 ] Xoff-2 0048 0049 #define NUM_16654_REGS 16 0050 0051 #define IS_REG_2ND_BANK(x) ((x) >= 8) 0052 0053 // 0054 // Bit definitions for each register 0055 // 0056 0057 #define IER_RX 0x01 // Enable receive interrupt 0058 #define IER_TX 0x02 // Enable transmit interrupt 0059 #define IER_RXS 0x04 // Enable receive status interrupt 0060 #define IER_MDM 0x08 // Enable modem status interrupt 0061 #define IER_SLEEP 0x10 // Enable sleep mode 0062 #define IER_XOFF 0x20 // Enable s/w flow control (XOFF) interrupt 0063 #define IER_RTS 0x40 // Enable RTS interrupt 0064 #define IER_CTS 0x80 // Enable CTS interrupt 0065 #define IER_ENABLE_ALL 0xFF // Enable all ints 0066 0067 0068 #define FCR_FIFO_EN 0x01 // Enable FIFOs 0069 #define FCR_RXCLR 0x02 // Reset Rx FIFO 0070 #define FCR_TXCLR 0x04 // Reset Tx FIFO 0071 #define FCR_DMA_BLK 0x08 // Enable DMA block mode 0072 #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level 0073 #define FCR_TX_LEVEL_8 0x00 // Tx FIFO Level = 8 bytes 0074 #define FCR_TX_LEVEL_16 0x10 // Tx FIFO Level = 16 bytes 0075 #define FCR_TX_LEVEL_32 0x20 // Tx FIFO Level = 32 bytes 0076 #define FCR_TX_LEVEL_56 0x30 // Tx FIFO Level = 56 bytes 0077 #define FCR_RX_LEVEL_MASK 0xC0 // Mask for Rx FIFO Level 0078 #define FCR_RX_LEVEL_8 0x00 // Rx FIFO Level = 8 bytes 0079 #define FCR_RX_LEVEL_16 0x40 // Rx FIFO Level = 16 bytes 0080 #define FCR_RX_LEVEL_56 0x80 // Rx FIFO Level = 56 bytes 0081 #define FCR_RX_LEVEL_60 0xC0 // Rx FIFO Level = 60 bytes 0082 0083 0084 #define ISR_INT_MDM_STATUS 0x00 // Modem status int pending 0085 #define ISR_INT_NONE 0x01 // No interrupt pending 0086 #define ISR_INT_TXRDY 0x02 // Tx ready int pending 0087 #define ISR_INT_RXRDY 0x04 // Rx ready int pending 0088 #define ISR_INT_LINE_STATUS 0x06 // Line status int pending 0089 #define ISR_INT_RX_TIMEOUT 0x0C // Rx timeout int pending 0090 #define ISR_INT_RX_XOFF 0x10 // Rx Xoff int pending 0091 #define ISR_INT_RTS_CTS 0x20 // RTS/CTS change int pending 0092 #define ISR_FIFO_ENABLED 0xC0 // Bits set if FIFOs enabled 0093 #define ISR_INT_BITS_MASK 0x3E // Mask to isolate valid int causes 0094 0095 0096 #define LCR_BITS_5 0x00 // 5 bits/char 0097 #define LCR_BITS_6 0x01 // 6 bits/char 0098 #define LCR_BITS_7 0x02 // 7 bits/char 0099 #define LCR_BITS_8 0x03 // 8 bits/char 0100 #define LCR_BITS_MASK 0x03 // Mask for bits/char field 0101 0102 #define LCR_STOP_1 0x00 // 1 stop bit 0103 #define LCR_STOP_1_5 0x04 // 1.5 stop bits (if 5 bits/char) 0104 #define LCR_STOP_2 0x04 // 2 stop bits (if 6-8 bits/char) 0105 #define LCR_STOP_MASK 0x04 // Mask for stop bits field 0106 0107 #define LCR_PAR_NONE 0x00 // No parity 0108 #define LCR_PAR_ODD 0x08 // Odd parity 0109 #define LCR_PAR_EVEN 0x18 // Even parity 0110 #define LCR_PAR_MARK 0x28 // Force parity bit to 1 0111 #define LCR_PAR_SPACE 0x38 // Force parity bit to 0 0112 #define LCR_PAR_MASK 0x38 // Mask for parity field 0113 0114 #define LCR_SET_BREAK 0x40 // Set Break condition 0115 #define LCR_DL_ENABLE 0x80 // Enable access to divisor latch 0116 0117 #define LCR_ACCESS_EFR 0xBF // Load this value to access DLL,DLM, 0118 // and also the '654-only registers 0119 // EFR, XON1, XON2, XOFF1, XOFF2 0120 0121 0122 #define MCR_DTR 0x01 // Assert DTR 0123 #define MCR_RTS 0x02 // Assert RTS 0124 #define MCR_OUT1 0x04 // Loopback only: Sets state of RI 0125 #define MCR_MASTER_IE 0x08 // Enable interrupt outputs 0126 #define MCR_LOOPBACK 0x10 // Set internal (digital) loopback mode 0127 #define MCR_XON_ANY 0x20 // Enable any char to exit XOFF mode 0128 #define MCR_IR_ENABLE 0x40 // Enable IrDA functions 0129 #define MCR_BRG_DIV_4 0x80 // Divide baud rate clk by /4 instead of /1 0130 0131 0132 #define LSR_RX_AVAIL 0x01 // Rx data available 0133 #define LSR_OVER_ERR 0x02 // Rx overrun 0134 #define LSR_PAR_ERR 0x04 // Rx parity error 0135 #define LSR_FRM_ERR 0x08 // Rx framing error 0136 #define LSR_BREAK 0x10 // Rx break condition detected 0137 #define LSR_TX_EMPTY 0x20 // Tx Fifo empty 0138 #define LSR_TX_ALL_EMPTY 0x40 // Tx Fifo and shift register empty 0139 #define LSR_FIFO_ERR 0x80 // Rx Fifo contains at least 1 erred char 0140 0141 0142 #define EDGEPORT_MSR_DELTA_CTS 0x01 // CTS changed from last read 0143 #define EDGEPORT_MSR_DELTA_DSR 0x02 // DSR changed from last read 0144 #define EDGEPORT_MSR_DELTA_RI 0x04 // RI changed from 0 -> 1 0145 #define EDGEPORT_MSR_DELTA_CD 0x08 // CD changed from last read 0146 #define EDGEPORT_MSR_CTS 0x10 // Current state of CTS 0147 #define EDGEPORT_MSR_DSR 0x20 // Current state of DSR 0148 #define EDGEPORT_MSR_RI 0x40 // Current state of RI 0149 #define EDGEPORT_MSR_CD 0x80 // Current state of CD 0150 0151 0152 0153 // Tx Rx 0154 //------------------------------- 0155 #define EFR_SWFC_NONE 0x00 // None None 0156 #define EFR_SWFC_RX1 0x02 // None XOFF1 0157 #define EFR_SWFC_RX2 0x01 // None XOFF2 0158 #define EFR_SWFC_RX12 0x03 // None XOFF1 & XOFF2 0159 #define EFR_SWFC_TX1 0x08 // XOFF1 None 0160 #define EFR_SWFC_TX1_RX1 0x0a // XOFF1 XOFF1 0161 #define EFR_SWFC_TX1_RX2 0x09 // XOFF1 XOFF2 0162 #define EFR_SWFC_TX1_RX12 0x0b // XOFF1 XOFF1 & XOFF2 0163 #define EFR_SWFC_TX2 0x04 // XOFF2 None 0164 #define EFR_SWFC_TX2_RX1 0x06 // XOFF2 XOFF1 0165 #define EFR_SWFC_TX2_RX2 0x05 // XOFF2 XOFF2 0166 #define EFR_SWFC_TX2_RX12 0x07 // XOFF2 XOFF1 & XOFF2 0167 #define EFR_SWFC_TX12 0x0c // XOFF1 & XOFF2 None 0168 #define EFR_SWFC_TX12_RX1 0x0e // XOFF1 & XOFF2 XOFF1 0169 #define EFR_SWFC_TX12_RX2 0x0d // XOFF1 & XOFF2 XOFF2 0170 #define EFR_SWFC_TX12_RX12 0x0f // XOFF1 & XOFF2 XOFF1 & XOFF2 0171 0172 #define EFR_TX_FC_MASK 0x0c // Mask to isolate Rx flow control 0173 #define EFR_TX_FC_NONE 0x00 // No Tx Xon/Xoff flow control 0174 #define EFR_TX_FC_X1 0x08 // Transmit Xon1/Xoff1 0175 #define EFR_TX_FC_X2 0x04 // Transmit Xon2/Xoff2 0176 #define EFR_TX_FC_X1_2 0x0c // Transmit Xon1&2/Xoff1&2 0177 0178 #define EFR_RX_FC_MASK 0x03 // Mask to isolate Rx flow control 0179 #define EFR_RX_FC_NONE 0x00 // No Rx Xon/Xoff flow control 0180 #define EFR_RX_FC_X1 0x02 // Receiver compares Xon1/Xoff1 0181 #define EFR_RX_FC_X2 0x01 // Receiver compares Xon2/Xoff2 0182 #define EFR_RX_FC_X1_2 0x03 // Receiver compares Xon1&2/Xoff1&2 0183 0184 0185 #define EFR_SWFC_MASK 0x0F // Mask for software flow control field 0186 #define EFR_ENABLE_16654 0x10 // Enable 16C654 features 0187 #define EFR_SPEC_DETECT 0x20 // Enable special character detect interrupt 0188 #define EFR_AUTO_RTS 0x40 // Use RTS for Rx flow control 0189 #define EFR_AUTO_CTS 0x80 // Use CTS for Tx flow control 0190 0191 #endif // if !defined(_16654_H) 0192
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