usb/renesas_usbhs/rza.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas USB driver RZ/A initialization and power control
0004  *
0005  * Copyright (C) 2018 Chris Brandt
0006  * Copyright (C) 2018-2019 Renesas Electronics Corporation
0007  */
0008
0009 #include <linux/delay.h>
0010 #include <linux/io.h>
0011 #include <linux/of_device.h>
0012 #include "common.h"
0013 #include "rza.h"
0014
0015 static int usbhs_rza1_hardware_init(struct platform_device *pdev)
0016 {
0017     struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
0018     struct device_node *usb_x1_clk, *extal_clk;
0019     u32 freq_usb = 0, freq_extal = 0;
0020
0021     /* Input Clock Selection (NOTE: ch0 controls both ch0 and ch1) */
0022     usb_x1_clk = of_find_node_by_name(NULL, "usb_x1");
0023     extal_clk = of_find_node_by_name(NULL, "extal");
0024     of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb);
0025     of_property_read_u32(extal_clk, "clock-frequency", &freq_extal);
0026
0027     of_node_put(usb_x1_clk);
0028     of_node_put(extal_clk);
0029
0030     if (freq_usb == 0) {
0031         if (freq_extal == 12000000) {
0032             /* Select 12MHz XTAL */
0033             usbhs_bset(priv, SYSCFG, UCKSEL, UCKSEL);
0034         } else {
0035             dev_err(usbhs_priv_to_dev(priv), "A 48MHz USB clock or 12MHz main clock is required.\n");
0036             return -EIO;
0037         }
0038     }
0039
0040     /* Enable USB PLL (NOTE: ch0 controls both ch0 and ch1) */
0041     usbhs_bset(priv, SYSCFG, UPLLE, UPLLE);
0042     usleep_range(1000, 2000);
0043     usbhs_bset(priv, SUSPMODE, SUSPM, SUSPM);
0044
0045     return 0;
0046 }
0047
0048 const struct renesas_usbhs_platform_info usbhs_rza1_plat_info = {
0049     .platform_callback = {
0050         .hardware_init = usbhs_rza1_hardware_init,
0051         .get_id = usbhs_get_id_as_gadget,
0052     },
0053     .driver_param = {
0054         .has_new_pipe_configs = 1,
0055     },
0056 };