usb/renesas_usbhs/common.h

0001 /* SPDX-License-Identifier: GPL-1.0+ */
0002 /*
0003  * Renesas USB driver
0004  *
0005  * Copyright (C) 2011 Renesas Solutions Corp.
0006  * Copyright (C) 2019 Renesas Electronics Corporation
0007  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
0008  */
0009 #ifndef RENESAS_USB_DRIVER_H
0010 #define RENESAS_USB_DRIVER_H
0011
0012 #include <linux/clk.h>
0013 #include <linux/extcon.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/reset.h>
0016 #include <linux/usb/renesas_usbhs.h>
0017
0018 struct usbhs_priv;
0019
0020 #include "mod.h"
0021 #include "pipe.h"
0022
0023 /*
0024  *
0025  *      register define
0026  *
0027  */
0028 #define SYSCFG      0x0000
0029 #define BUSWAIT     0x0002
0030 #define DVSTCTR     0x0008
0031 #define TESTMODE    0x000C
0032 #define CFIFO       0x0014
0033 #define CFIFOSEL    0x0020
0034 #define CFIFOCTR    0x0022
0035 #define D0FIFO      0x0100
0036 #define D0FIFOSEL   0x0028
0037 #define D0FIFOCTR   0x002A
0038 #define D1FIFO      0x0120
0039 #define D1FIFOSEL   0x002C
0040 #define D1FIFOCTR   0x002E
0041 #define INTENB0     0x0030
0042 #define INTENB1     0x0032
0043 #define BRDYENB     0x0036
0044 #define NRDYENB     0x0038
0045 #define BEMPENB     0x003A
0046 #define INTSTS0     0x0040
0047 #define INTSTS1     0x0042
0048 #define BRDYSTS     0x0046
0049 #define NRDYSTS     0x0048
0050 #define BEMPSTS     0x004A
0051 #define FRMNUM      0x004C
0052 #define USBREQ      0x0054  /* USB request type register */
0053 #define USBVAL      0x0056  /* USB request value register */
0054 #define USBINDX     0x0058  /* USB request index register */
0055 #define USBLENG     0x005A  /* USB request length register */
0056 #define DCPCFG      0x005C
0057 #define DCPMAXP     0x005E
0058 #define DCPCTR      0x0060
0059 #define PIPESEL     0x0064
0060 #define PIPECFG     0x0068
0061 #define PIPEBUF     0x006A
0062 #define PIPEMAXP    0x006C
0063 #define PIPEPERI    0x006E
0064 #define PIPEnCTR    0x0070
0065 #define PIPE1TRE    0x0090
0066 #define PIPE1TRN    0x0092
0067 #define PIPE2TRE    0x0094
0068 #define PIPE2TRN    0x0096
0069 #define PIPE3TRE    0x0098
0070 #define PIPE3TRN    0x009A
0071 #define PIPE4TRE    0x009C
0072 #define PIPE4TRN    0x009E
0073 #define PIPE5TRE    0x00A0
0074 #define PIPE5TRN    0x00A2
0075 #define PIPEBTRE    0x00A4
0076 #define PIPEBTRN    0x00A6
0077 #define PIPECTRE    0x00A8
0078 #define PIPECTRN    0x00AA
0079 #define PIPEDTRE    0x00AC
0080 #define PIPEDTRN    0x00AE
0081 #define PIPEETRE    0x00B0
0082 #define PIPEETRN    0x00B2
0083 #define PIPEFTRE    0x00B4
0084 #define PIPEFTRN    0x00B6
0085 #define PIPE9TRE    0x00B8
0086 #define PIPE9TRN    0x00BA
0087 #define PIPEATRE    0x00BC
0088 #define PIPEATRN    0x00BE
0089 #define DEVADD0     0x00D0 /* Device address n configuration */
0090 #define DEVADD1     0x00D2
0091 #define DEVADD2     0x00D4
0092 #define DEVADD3     0x00D6
0093 #define DEVADD4     0x00D8
0094 #define DEVADD5     0x00DA
0095 #define DEVADD6     0x00DC
0096 #define DEVADD7     0x00DE
0097 #define DEVADD8     0x00E0
0098 #define DEVADD9     0x00E2
0099 #define DEVADDA     0x00E4
0100 #define D2FIFOSEL   0x00F0  /* for R-Car Gen2 */
0101 #define D2FIFOCTR   0x00F2  /* for R-Car Gen2 */
0102 #define D3FIFOSEL   0x00F4  /* for R-Car Gen2 */
0103 #define D3FIFOCTR   0x00F6  /* for R-Car Gen2 */
0104 #define SUSPMODE    0x0102  /* for RZ/A */
0105
0106 /* SYSCFG */
0107 #define SCKE    (1 << 10)   /* USB Module Clock Enable */
0108 #define CNEN    (1 << 8)    /* Single-ended receiver operation Enable */
0109 #define HSE (1 << 7)    /* High-Speed Operation Enable */
0110 #define DCFM    (1 << 6)    /* Controller Function Select */
0111 #define DRPD    (1 << 5)    /* D+ Line/D- Line Resistance Control */
0112 #define DPRPU   (1 << 4)    /* D+ Line Resistance Control */
0113 #define USBE    (1 << 0)    /* USB Module Operation Enable */
0114 #define UCKSEL  (1 << 2)    /* Clock Select for RZ/A1 */
0115 #define UPLLE   (1 << 1)    /* USB PLL Enable for RZ/A1 */
0116
0117 /* DVSTCTR */
0118 #define EXTLP   (1 << 10)   /* Controls the EXTLP pin output state */
0119 #define PWEN    (1 << 9)    /* Controls the PWEN pin output state */
0120 #define USBRST  (1 << 6)    /* Bus Reset Output */
0121 #define UACT    (1 << 4)    /* USB Bus Enable */
0122 #define RHST    (0x7)       /* Reset Handshake */
0123 #define  RHST_LOW_SPEED  1  /* Low-speed connection */
0124 #define  RHST_FULL_SPEED 2  /* Full-speed connection */
0125 #define  RHST_HIGH_SPEED 3  /* High-speed connection */
0126
0127 /* CFIFOSEL */
0128 #define DREQE   (1 << 12)   /* DMA Transfer Request Enable */
0129 #define MBW_32  (0x2 << 10) /* CFIFO Port Access Bit Width */
0130
0131 /* CFIFOCTR */
0132 #define BVAL    (1 << 15)   /* Buffer Memory Enable Flag */
0133 #define BCLR    (1 << 14)   /* CPU buffer clear */
0134 #define FRDY    (1 << 13)   /* FIFO Port Ready */
0135 #define DTLN_MASK (0x0FFF)  /* Receive Data Length */
0136
0137 /* INTENB0 */
0138 #define VBSE    (1 << 15)   /* Enable IRQ VBUS_0 and VBUSIN_0 */
0139 #define RSME    (1 << 14)   /* Enable IRQ Resume */
0140 #define SOFE    (1 << 13)   /* Enable IRQ Frame Number Update */
0141 #define DVSE    (1 << 12)   /* Enable IRQ Device State Transition */
0142 #define CTRE    (1 << 11)   /* Enable IRQ Control Stage Transition */
0143 #define BEMPE   (1 << 10)   /* Enable IRQ Buffer Empty */
0144 #define NRDYE   (1 << 9)    /* Enable IRQ Buffer Not Ready Response */
0145 #define BRDYE   (1 << 8)    /* Enable IRQ Buffer Ready */
0146
0147 /* INTENB1 */
0148 #define BCHGE   (1 << 14)   /* USB Bus Change Interrupt Enable */
0149 #define DTCHE   (1 << 12)   /* Disconnection Detect Interrupt Enable */
0150 #define ATTCHE  (1 << 11)   /* Connection Detect Interrupt Enable */
0151 #define EOFERRE (1 << 6)    /* EOF Error Detect Interrupt Enable */
0152 #define SIGNE   (1 << 5)    /* Setup Transaction Error Interrupt Enable */
0153 #define SACKE   (1 << 4)    /* Setup Transaction ACK Interrupt Enable */
0154
0155 /* INTSTS0 */
0156 #define VBINT   (1 << 15)   /* VBUS0_0 and VBUS1_0 Interrupt Status */
0157 #define DVST    (1 << 12)   /* Device State Transition Interrupt Status */
0158 #define CTRT    (1 << 11)   /* Control Stage Interrupt Status */
0159 #define BEMP    (1 << 10)   /* Buffer Empty Interrupt Status */
0160 #define BRDY    (1 << 8)    /* Buffer Ready Interrupt Status */
0161 #define VBSTS   (1 << 7)    /* VBUS_0 and VBUSIN_0 Input Status */
0162 #define VALID   (1 << 3)    /* USB Request Receive */
0163
0164 #define DVSQ_MASK       (0x7 << 4)  /* Device State */
0165 #define  POWER_STATE        (0 << 4)
0166 #define  DEFAULT_STATE      (1 << 4)
0167 #define  ADDRESS_STATE      (2 << 4)
0168 #define  CONFIGURATION_STATE    (3 << 4)
0169 #define  SUSPENDED_STATE    (4 << 4)
0170
0171 #define CTSQ_MASK       (0x7)   /* Control Transfer Stage */
0172 #define  IDLE_SETUP_STAGE   0   /* Idle stage or setup stage */
0173 #define  READ_DATA_STAGE    1   /* Control read data stage */
0174 #define  READ_STATUS_STAGE  2   /* Control read status stage */
0175 #define  WRITE_DATA_STAGE   3   /* Control write data stage */
0176 #define  WRITE_STATUS_STAGE 4   /* Control write status stage */
0177 #define  NODATA_STATUS_STAGE    5   /* Control write NoData status stage */
0178 #define  SEQUENCE_ERROR     6   /* Control transfer sequence error */
0179
0180 /* INTSTS1 */
0181 #define OVRCR   (1 << 15) /* OVRCR Interrupt Status */
0182 #define BCHG    (1 << 14) /* USB Bus Change Interrupt Status */
0183 #define DTCH    (1 << 12) /* USB Disconnection Detect Interrupt Status */
0184 #define ATTCH   (1 << 11) /* ATTCH Interrupt Status */
0185 #define EOFERR  (1 << 6)  /* EOF Error Detect Interrupt Status */
0186 #define SIGN    (1 << 5)  /* Setup Transaction Error Interrupt Status */
0187 #define SACK    (1 << 4)  /* Setup Transaction ACK Response Interrupt Status */
0188
0189 /* PIPECFG */
0190 /* DCPCFG */
0191 #define TYPE_NONE   (0 << 14)   /* Transfer Type */
0192 #define TYPE_BULK   (1 << 14)
0193 #define TYPE_INT    (2 << 14)
0194 #define TYPE_ISO    (3 << 14)
0195 #define BFRE        (1 << 10)   /* BRDY Interrupt Operation Spec. */
0196 #define DBLB        (1 << 9)    /* Double Buffer Mode */
0197 #define SHTNAK      (1 << 7)    /* Pipe Disable in Transfer End */
0198 #define DIR_OUT     (1 << 4)    /* Transfer Direction */
0199
0200 /* PIPEMAXP */
0201 /* DCPMAXP */
0202 #define DEVSEL_MASK (0xF << 12) /* Device Select */
0203 #define DCP_MAXP_MASK   (0x7F)
0204 #define PIPE_MAXP_MASK  (0x7FF)
0205
0206 /* PIPEBUF */
0207 #define BUFSIZE_SHIFT   10
0208 #define BUFSIZE_MASK    (0x1F << BUFSIZE_SHIFT)
0209 #define BUFNMB_MASK (0xFF)
0210
0211 /* PIPEnCTR */
0212 /* DCPCTR */
0213 #define BSTS        (1 << 15)   /* Buffer Status */
0214 #define SUREQ       (1 << 14)   /* Sending SETUP Token */
0215 #define INBUFM      (1 << 14)   /* (PIPEnCTR) Transfer Buffer Monitor */
0216 #define CSSTS       (1 << 12)   /* CSSTS Status */
0217 #define ACLRM       (1 << 9)    /* Buffer Auto-Clear Mode */
0218 #define SQCLR       (1 << 8)    /* Toggle Bit Clear */
0219 #define SQSET       (1 << 7)    /* Toggle Bit Set */
0220 #define SQMON       (1 << 6)    /* Toggle Bit Check */
0221 #define PBUSY       (1 << 5)    /* Pipe Busy */
0222 #define PID_MASK    (0x3)       /* Response PID */
0223 #define  PID_NAK    0
0224 #define  PID_BUF    1
0225 #define  PID_STALL10    2
0226 #define  PID_STALL11    3
0227
0228 #define CCPL        (1 << 2)    /* Control Transfer End Enable */
0229
0230 /* PIPEnTRE */
0231 #define TRENB       (1 << 9)    /* Transaction Counter Enable */
0232 #define TRCLR       (1 << 8)    /* Transaction Counter Clear */
0233
0234 /* FRMNUM */
0235 #define FRNM_MASK   (0x7FF)
0236
0237 /* DEVADDn */
0238 #define UPPHUB(x)   (((x) & 0xF) << 11) /* HUB Register */
0239 #define HUBPORT(x)  (((x) & 0x7) << 8)  /* HUB Port for Target Device */
0240 #define USBSPD(x)   (((x) & 0x3) << 6)  /* Device Transfer Rate */
0241 #define USBSPD_SPEED_LOW    0x1
0242 #define USBSPD_SPEED_FULL   0x2
0243 #define USBSPD_SPEED_HIGH   0x3
0244
0245 /* SUSPMODE */
0246 #define SUSPM       (1 << 14)   /* SuspendM Control */
0247
0248 /*
0249  *      struct
0250  */
0251 struct usbhs_priv {
0252
0253     void __iomem *base;
0254     unsigned int irq;
0255
0256     const struct renesas_usbhs_platform_callback *pfunc;
0257     struct renesas_usbhs_driver_param   dparam;
0258
0259     struct delayed_work notify_hotplug_work;
0260     struct platform_device *pdev;
0261
0262     struct extcon_dev *edev;
0263
0264     spinlock_t      lock;
0265
0266     /*
0267      * module control
0268      */
0269     struct usbhs_mod_info mod_info;
0270
0271     /*
0272      * pipe control
0273      */
0274     struct usbhs_pipe_info pipe_info;
0275
0276     /*
0277      * fifo control
0278      */
0279     struct usbhs_fifo_info fifo_info;
0280
0281     struct phy *phy;
0282     struct reset_control *rsts;
0283     struct clk *clks[2];
0284 };
0285
0286 /*
0287  * common
0288  */
0289 u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
0290 void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
0291 void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
0292
0293 #define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
0294 #define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)
0295
0296 int usbhs_get_id_as_gadget(struct platform_device *pdev);
0297
0298 /*
0299  * sysconfig
0300  */
0301 void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
0302 void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
0303 void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable);
0304 void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode);
0305
0306 /*
0307  * usb request
0308  */
0309 void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
0310 void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
0311
0312 /*
0313  * bus
0314  */
0315 void usbhs_bus_send_sof_enable(struct usbhs_priv *priv);
0316 void usbhs_bus_send_reset(struct usbhs_priv *priv);
0317 int usbhs_bus_get_speed(struct usbhs_priv *priv);
0318 int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
0319 int usbhsc_schedule_notify_hotplug(struct platform_device *pdev);
0320
0321 /*
0322  * frame
0323  */
0324 int usbhs_frame_get_num(struct usbhs_priv *priv);
0325
0326 /*
0327  * device config
0328  */
0329 int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub,
0330                u16 hubport, u16 speed);
0331
0332 /*
0333  * interrupt functions
0334  */
0335 void usbhs_xxxsts_clear(struct usbhs_priv *priv, u16 sts_reg, u16 bit);
0336
0337 /*
0338  * data
0339  */
0340 struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
0341 #define usbhs_get_dparam(priv, param)   (priv->dparam.param)
0342 #define usbhs_priv_to_pdev(priv)    (priv->pdev)
0343 #define usbhs_priv_to_dev(priv)     (&priv->pdev->dev)
0344 #define usbhs_priv_to_lock(priv)    (&priv->lock)
0345
0346 #endif /* RENESAS_USB_DRIVER_H */