usb/phy/phy-mv-usb.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
0004  */
0005
0006 #ifndef __MV_USB_OTG_CONTROLLER__
0007 #define __MV_USB_OTG_CONTROLLER__
0008
0009 #include <linux/types.h>
0010
0011 /* Command Register Bit Masks */
0012 #define USBCMD_RUN_STOP         (0x00000001)
0013 #define USBCMD_CTRL_RESET       (0x00000002)
0014
0015 /* otgsc Register Bit Masks */
0016 #define OTGSC_CTRL_VUSB_DISCHARGE       0x00000001
0017 #define OTGSC_CTRL_VUSB_CHARGE          0x00000002
0018 #define OTGSC_CTRL_OTG_TERM         0x00000008
0019 #define OTGSC_CTRL_DATA_PULSING         0x00000010
0020 #define OTGSC_STS_USB_ID            0x00000100
0021 #define OTGSC_STS_A_VBUS_VALID          0x00000200
0022 #define OTGSC_STS_A_SESSION_VALID       0x00000400
0023 #define OTGSC_STS_B_SESSION_VALID       0x00000800
0024 #define OTGSC_STS_B_SESSION_END         0x00001000
0025 #define OTGSC_STS_1MS_TOGGLE            0x00002000
0026 #define OTGSC_STS_DATA_PULSING          0x00004000
0027 #define OTGSC_INTSTS_USB_ID         0x00010000
0028 #define OTGSC_INTSTS_A_VBUS_VALID       0x00020000
0029 #define OTGSC_INTSTS_A_SESSION_VALID        0x00040000
0030 #define OTGSC_INTSTS_B_SESSION_VALID        0x00080000
0031 #define OTGSC_INTSTS_B_SESSION_END      0x00100000
0032 #define OTGSC_INTSTS_1MS            0x00200000
0033 #define OTGSC_INTSTS_DATA_PULSING       0x00400000
0034 #define OTGSC_INTR_USB_ID           0x01000000
0035 #define OTGSC_INTR_A_VBUS_VALID         0x02000000
0036 #define OTGSC_INTR_A_SESSION_VALID      0x04000000
0037 #define OTGSC_INTR_B_SESSION_VALID      0x08000000
0038 #define OTGSC_INTR_B_SESSION_END        0x10000000
0039 #define OTGSC_INTR_1MS_TIMER            0x20000000
0040 #define OTGSC_INTR_DATA_PULSING         0x40000000
0041
0042 #define CAPLENGTH_MASK      (0xff)
0043
0044 /* Timer's interval, unit 10ms */
0045 #define T_A_WAIT_VRISE      100
0046 #define T_A_WAIT_BCON       2000
0047 #define T_A_AIDL_BDIS       100
0048 #define T_A_BIDL_ADIS       20
0049 #define T_B_ASE0_BRST       400
0050 #define T_B_SE0_SRP     300
0051 #define T_B_SRP_FAIL        2000
0052 #define T_B_DATA_PLS        10
0053 #define T_B_SRP_INIT        100
0054 #define T_A_SRP_RSPNS       10
0055 #define T_A_DRV_RSM     5
0056
0057 enum otg_function {
0058     OTG_B_DEVICE = 0,
0059     OTG_A_DEVICE
0060 };
0061
0062 enum mv_otg_timer {
0063     A_WAIT_BCON_TIMER = 0,
0064     OTG_TIMER_NUM
0065 };
0066
0067 /* PXA OTG state machine */
0068 struct mv_otg_ctrl {
0069     /* internal variables */
0070     u8 a_set_b_hnp_en;  /* A-Device set b_hnp_en */
0071     u8 b_srp_done;
0072     u8 b_hnp_en;
0073
0074     /* OTG inputs */
0075     u8 a_bus_drop;
0076     u8 a_bus_req;
0077     u8 a_clr_err;
0078     u8 a_bus_resume;
0079     u8 a_bus_suspend;
0080     u8 a_conn;
0081     u8 a_sess_vld;
0082     u8 a_srp_det;
0083     u8 a_vbus_vld;
0084     u8 b_bus_req;       /* B-Device Require Bus */
0085     u8 b_bus_resume;
0086     u8 b_bus_suspend;
0087     u8 b_conn;
0088     u8 b_se0_srp;
0089     u8 b_sess_end;
0090     u8 b_sess_vld;
0091     u8 id;
0092     u8 a_suspend_req;
0093
0094     /*Timer event */
0095     u8 a_aidl_bdis_timeout;
0096     u8 b_ase0_brst_timeout;
0097     u8 a_bidl_adis_timeout;
0098     u8 a_wait_bcon_timeout;
0099
0100     struct timer_list timer[OTG_TIMER_NUM];
0101 };
0102
0103 #define VUSBHS_MAX_PORTS    8
0104
0105 struct mv_otg_regs {
0106     u32 usbcmd;     /* Command register */
0107     u32 usbsts;     /* Status register */
0108     u32 usbintr;        /* Interrupt enable */
0109     u32 frindex;        /* Frame index */
0110     u32 reserved1[1];
0111     u32 deviceaddr;     /* Device Address */
0112     u32 eplistaddr;     /* Endpoint List Address */
0113     u32 ttctrl;     /* HOST TT status and control */
0114     u32 burstsize;      /* Programmable Burst Size */
0115     u32 txfilltuning;   /* Host Transmit Pre-Buffer Packet Tuning */
0116     u32 reserved[4];
0117     u32 epnak;      /* Endpoint NAK */
0118     u32 epnaken;        /* Endpoint NAK Enable */
0119     u32 configflag;     /* Configured Flag register */
0120     u32 portsc[VUSBHS_MAX_PORTS];   /* Port Status/Control x, x = 1..8 */
0121     u32 otgsc;
0122     u32 usbmode;        /* USB Host/Device mode */
0123     u32 epsetupstat;    /* Endpoint Setup Status */
0124     u32 epprime;        /* Endpoint Initialize */
0125     u32 epflush;        /* Endpoint De-initialize */
0126     u32 epstatus;       /* Endpoint Status */
0127     u32 epcomplete;     /* Endpoint Interrupt On Complete */
0128     u32 epctrlx[16];    /* Endpoint Control, where x = 0.. 15 */
0129     u32 mcr;        /* Mux Control */
0130     u32 isr;        /* Interrupt Status */
0131     u32 ier;        /* Interrupt Enable */
0132 };
0133
0134 struct mv_otg {
0135     struct usb_phy phy;
0136     struct mv_otg_ctrl otg_ctrl;
0137
0138     /* base address */
0139     void __iomem *phy_regs;
0140     void __iomem *cap_regs;
0141     struct mv_otg_regs __iomem *op_regs;
0142
0143     struct platform_device *pdev;
0144     int irq;
0145     u32 irq_status;
0146     u32 irq_en;
0147
0148     struct delayed_work work;
0149     struct workqueue_struct *qwork;
0150
0151     spinlock_t wq_lock;
0152
0153     struct mv_usb_platform_data *pdata;
0154
0155     unsigned int active;
0156     unsigned int clock_gating;
0157     struct clk *clk;
0158 };
0159
0160 #endif