usb/phy/phy-jz4770.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Ingenic SoCs USB PHY driver
0004  * Copyright (c) Paul Cercueil <paul@crapouillou.net>
0005  * Copyright (c) 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
0006  * Copyright (c) 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/regulator/consumer.h>
0014 #include <linux/usb/otg.h>
0015 #include <linux/usb/phy.h>
0016
0017 /* OTGPHY register offsets */
0018 #define REG_USBPCR_OFFSET           0x00
0019 #define REG_USBRDT_OFFSET           0x04
0020 #define REG_USBVBFIL_OFFSET         0x08
0021 #define REG_USBPCR1_OFFSET          0x0c
0022
0023 /* bits within the USBPCR register */
0024 #define USBPCR_USB_MODE             BIT(31)
0025 #define USBPCR_AVLD_REG             BIT(30)
0026 #define USBPCR_COMMONONN            BIT(25)
0027 #define USBPCR_VBUSVLDEXT           BIT(24)
0028 #define USBPCR_VBUSVLDEXTSEL        BIT(23)
0029 #define USBPCR_POR                  BIT(22)
0030 #define USBPCR_SIDDQ                BIT(21)
0031 #define USBPCR_OTG_DISABLE          BIT(20)
0032 #define USBPCR_TXPREEMPHTUNE        BIT(6)
0033
0034 #define USBPCR_IDPULLUP_LSB 28
0035 #define USBPCR_IDPULLUP_MASK        GENMASK(29, USBPCR_IDPULLUP_LSB)
0036 #define USBPCR_IDPULLUP_ALWAYS      (0x2 << USBPCR_IDPULLUP_LSB)
0037 #define USBPCR_IDPULLUP_SUSPEND     (0x1 << USBPCR_IDPULLUP_LSB)
0038 #define USBPCR_IDPULLUP_OTG         (0x0 << USBPCR_IDPULLUP_LSB)
0039
0040 #define USBPCR_COMPDISTUNE_LSB      17
0041 #define USBPCR_COMPDISTUNE_MASK     GENMASK(19, USBPCR_COMPDISTUNE_LSB)
0042 #define USBPCR_COMPDISTUNE_DFT      (0x4 << USBPCR_COMPDISTUNE_LSB)
0043
0044 #define USBPCR_OTGTUNE_LSB          14
0045 #define USBPCR_OTGTUNE_MASK         GENMASK(16, USBPCR_OTGTUNE_LSB)
0046 #define USBPCR_OTGTUNE_DFT          (0x4 << USBPCR_OTGTUNE_LSB)
0047
0048 #define USBPCR_SQRXTUNE_LSB 11
0049 #define USBPCR_SQRXTUNE_MASK        GENMASK(13, USBPCR_SQRXTUNE_LSB)
0050 #define USBPCR_SQRXTUNE_DCR_20PCT   (0x7 << USBPCR_SQRXTUNE_LSB)
0051 #define USBPCR_SQRXTUNE_DFT         (0x3 << USBPCR_SQRXTUNE_LSB)
0052
0053 #define USBPCR_TXFSLSTUNE_LSB       7
0054 #define USBPCR_TXFSLSTUNE_MASK      GENMASK(10, USBPCR_TXFSLSTUNE_LSB)
0055 #define USBPCR_TXFSLSTUNE_DCR_50PPT (0xf << USBPCR_TXFSLSTUNE_LSB)
0056 #define USBPCR_TXFSLSTUNE_DCR_25PPT (0x7 << USBPCR_TXFSLSTUNE_LSB)
0057 #define USBPCR_TXFSLSTUNE_DFT       (0x3 << USBPCR_TXFSLSTUNE_LSB)
0058 #define USBPCR_TXFSLSTUNE_INC_25PPT (0x1 << USBPCR_TXFSLSTUNE_LSB)
0059 #define USBPCR_TXFSLSTUNE_INC_50PPT (0x0 << USBPCR_TXFSLSTUNE_LSB)
0060
0061 #define USBPCR_TXHSXVTUNE_LSB       4
0062 #define USBPCR_TXHSXVTUNE_MASK      GENMASK(5, USBPCR_TXHSXVTUNE_LSB)
0063 #define USBPCR_TXHSXVTUNE_DFT       (0x3 << USBPCR_TXHSXVTUNE_LSB)
0064 #define USBPCR_TXHSXVTUNE_DCR_15MV  (0x1 << USBPCR_TXHSXVTUNE_LSB)
0065
0066 #define USBPCR_TXRISETUNE_LSB       4
0067 #define USBPCR_TXRISETUNE_MASK      GENMASK(5, USBPCR_TXRISETUNE_LSB)
0068 #define USBPCR_TXRISETUNE_DFT       (0x3 << USBPCR_TXRISETUNE_LSB)
0069
0070 #define USBPCR_TXVREFTUNE_LSB       0
0071 #define USBPCR_TXVREFTUNE_MASK      GENMASK(3, USBPCR_TXVREFTUNE_LSB)
0072 #define USBPCR_TXVREFTUNE_INC_25PPT (0x7 << USBPCR_TXVREFTUNE_LSB)
0073 #define USBPCR_TXVREFTUNE_DFT       (0x5 << USBPCR_TXVREFTUNE_LSB)
0074
0075 /* bits within the USBRDTR register */
0076 #define USBRDT_UTMI_RST             BIT(27)
0077 #define USBRDT_HB_MASK              BIT(26)
0078 #define USBRDT_VBFIL_LD_EN          BIT(25)
0079 #define USBRDT_IDDIG_EN             BIT(24)
0080 #define USBRDT_IDDIG_REG            BIT(23)
0081 #define USBRDT_VBFIL_EN             BIT(2)
0082
0083 /* bits within the USBPCR1 register */
0084 #define USBPCR1_BVLD_REG            BIT(31)
0085 #define USBPCR1_DPPD                BIT(29)
0086 #define USBPCR1_DMPD                BIT(28)
0087 #define USBPCR1_USB_SEL             BIT(28)
0088 #define USBPCR1_WORD_IF_16BIT       BIT(19)
0089
0090 enum ingenic_usb_phy_version {
0091     ID_JZ4770,
0092     ID_JZ4780,
0093     ID_X1000,
0094     ID_X1830,
0095 };
0096
0097 struct ingenic_soc_info {
0098     enum ingenic_usb_phy_version version;
0099
0100     void (*usb_phy_init)(struct usb_phy *phy);
0101 };
0102
0103 struct jz4770_phy {
0104     const struct ingenic_soc_info *soc_info;
0105
0106     struct usb_phy phy;
0107     struct usb_otg otg;
0108     struct device *dev;
0109     void __iomem *base;
0110     struct clk *clk;
0111     struct regulator *vcc_supply;
0112 };
0113
0114 static inline struct jz4770_phy *otg_to_jz4770_phy(struct usb_otg *otg)
0115 {
0116     return container_of(otg, struct jz4770_phy, otg);
0117 }
0118
0119 static inline struct jz4770_phy *phy_to_jz4770_phy(struct usb_phy *phy)
0120 {
0121     return container_of(phy, struct jz4770_phy, phy);
0122 }
0123
0124 static int ingenic_usb_phy_set_peripheral(struct usb_otg *otg,
0125                      struct usb_gadget *gadget)
0126 {
0127     struct jz4770_phy *priv = otg_to_jz4770_phy(otg);
0128     u32 reg;
0129
0130     if (priv->soc_info->version >= ID_X1000) {
0131         reg = readl(priv->base + REG_USBPCR1_OFFSET);
0132         reg |= USBPCR1_BVLD_REG;
0133         writel(reg, priv->base + REG_USBPCR1_OFFSET);
0134     }
0135
0136     reg = readl(priv->base + REG_USBPCR_OFFSET);
0137     reg &= ~USBPCR_USB_MODE;
0138     reg |= USBPCR_VBUSVLDEXT | USBPCR_VBUSVLDEXTSEL | USBPCR_OTG_DISABLE;
0139     writel(reg, priv->base + REG_USBPCR_OFFSET);
0140
0141     return 0;
0142 }
0143
0144 static int ingenic_usb_phy_set_host(struct usb_otg *otg, struct usb_bus *host)
0145 {
0146     struct jz4770_phy *priv = otg_to_jz4770_phy(otg);
0147     u32 reg;
0148
0149     reg = readl(priv->base + REG_USBPCR_OFFSET);
0150     reg &= ~(USBPCR_VBUSVLDEXT | USBPCR_VBUSVLDEXTSEL | USBPCR_OTG_DISABLE);
0151     reg |= USBPCR_USB_MODE;
0152     writel(reg, priv->base + REG_USBPCR_OFFSET);
0153
0154     return 0;
0155 }
0156
0157 static int ingenic_usb_phy_init(struct usb_phy *phy)
0158 {
0159     struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
0160     int err;
0161     u32 reg;
0162
0163     err = regulator_enable(priv->vcc_supply);
0164     if (err) {
0165         dev_err(priv->dev, "Unable to enable VCC: %d\n", err);
0166         return err;
0167     }
0168
0169     err = clk_prepare_enable(priv->clk);
0170     if (err) {
0171         dev_err(priv->dev, "Unable to start clock: %d\n", err);
0172         return err;
0173     }
0174
0175     priv->soc_info->usb_phy_init(phy);
0176
0177     /* Wait for PHY to reset */
0178     usleep_range(30, 300);
0179     reg = readl(priv->base + REG_USBPCR_OFFSET);
0180     writel(reg & ~USBPCR_POR, priv->base + REG_USBPCR_OFFSET);
0181     usleep_range(300, 1000);
0182
0183     return 0;
0184 }
0185
0186 static void ingenic_usb_phy_shutdown(struct usb_phy *phy)
0187 {
0188     struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
0189
0190     clk_disable_unprepare(priv->clk);
0191     regulator_disable(priv->vcc_supply);
0192 }
0193
0194 static void ingenic_usb_phy_remove(void *phy)
0195 {
0196     usb_remove_phy(phy);
0197 }
0198
0199 static void jz4770_usb_phy_init(struct usb_phy *phy)
0200 {
0201     struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
0202     u32 reg;
0203
0204     reg = USBPCR_AVLD_REG | USBPCR_COMMONONN | USBPCR_IDPULLUP_ALWAYS |
0205         USBPCR_COMPDISTUNE_DFT | USBPCR_OTGTUNE_DFT | USBPCR_SQRXTUNE_DFT |
0206         USBPCR_TXFSLSTUNE_DFT | USBPCR_TXRISETUNE_DFT | USBPCR_TXVREFTUNE_DFT |
0207         USBPCR_POR;
0208     writel(reg, priv->base + REG_USBPCR_OFFSET);
0209 }
0210
0211 static void jz4780_usb_phy_init(struct usb_phy *phy)
0212 {
0213     struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
0214     u32 reg;
0215
0216     reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_USB_SEL |
0217         USBPCR1_WORD_IF_16BIT;
0218     writel(reg, priv->base + REG_USBPCR1_OFFSET);
0219
0220     reg = USBPCR_TXPREEMPHTUNE | USBPCR_COMMONONN | USBPCR_POR;
0221     writel(reg, priv->base + REG_USBPCR_OFFSET);
0222 }
0223
0224 static void x1000_usb_phy_init(struct usb_phy *phy)
0225 {
0226     struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
0227     u32 reg;
0228
0229     reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT;
0230     writel(reg, priv->base + REG_USBPCR1_OFFSET);
0231
0232     reg = USBPCR_SQRXTUNE_DCR_20PCT | USBPCR_TXPREEMPHTUNE |
0233         USBPCR_TXHSXVTUNE_DCR_15MV | USBPCR_TXVREFTUNE_INC_25PPT |
0234         USBPCR_COMMONONN | USBPCR_POR;
0235     writel(reg, priv->base + REG_USBPCR_OFFSET);
0236 }
0237
0238 static void x1830_usb_phy_init(struct usb_phy *phy)
0239 {
0240     struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
0241     u32 reg;
0242
0243     /* rdt */
0244     writel(USBRDT_VBFIL_EN | USBRDT_UTMI_RST, priv->base + REG_USBRDT_OFFSET);
0245
0246     reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT |
0247         USBPCR1_DMPD | USBPCR1_DPPD;
0248     writel(reg, priv->base + REG_USBPCR1_OFFSET);
0249
0250     reg = USBPCR_IDPULLUP_OTG | USBPCR_VBUSVLDEXT | USBPCR_TXPREEMPHTUNE |
0251         USBPCR_COMMONONN | USBPCR_POR;
0252     writel(reg, priv->base + REG_USBPCR_OFFSET);
0253 }
0254
0255 static const struct ingenic_soc_info jz4770_soc_info = {
0256     .version = ID_JZ4770,
0257
0258     .usb_phy_init = jz4770_usb_phy_init,
0259 };
0260
0261 static const struct ingenic_soc_info jz4780_soc_info = {
0262     .version = ID_JZ4780,
0263
0264     .usb_phy_init = jz4780_usb_phy_init,
0265 };
0266
0267 static const struct ingenic_soc_info x1000_soc_info = {
0268     .version = ID_X1000,
0269
0270     .usb_phy_init = x1000_usb_phy_init,
0271 };
0272
0273 static const struct ingenic_soc_info x1830_soc_info = {
0274     .version = ID_X1830,
0275
0276     .usb_phy_init = x1830_usb_phy_init,
0277 };
0278
0279 static const struct of_device_id ingenic_usb_phy_of_matches[] = {
0280     { .compatible = "ingenic,jz4770-phy", .data = &jz4770_soc_info },
0281     { .compatible = "ingenic,jz4780-phy", .data = &jz4780_soc_info },
0282     { .compatible = "ingenic,x1000-phy", .data = &x1000_soc_info },
0283     { .compatible = "ingenic,x1830-phy", .data = &x1830_soc_info },
0284     { /* sentinel */ }
0285 };
0286 MODULE_DEVICE_TABLE(of, ingenic_usb_phy_of_matches);
0287
0288 static int jz4770_phy_probe(struct platform_device *pdev)
0289 {
0290     struct device *dev = &pdev->dev;
0291     struct jz4770_phy *priv;
0292     int err;
0293
0294     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0295     if (!priv)
0296         return -ENOMEM;
0297
0298     priv->soc_info = device_get_match_data(&pdev->dev);
0299     if (!priv->soc_info) {
0300         dev_err(&pdev->dev, "Error: No device match found\n");
0301         return -ENODEV;
0302     }
0303
0304     platform_set_drvdata(pdev, priv);
0305     priv->dev = dev;
0306     priv->phy.dev = dev;
0307     priv->phy.otg = &priv->otg;
0308     priv->phy.label = "ingenic-usb-phy";
0309     priv->phy.init = ingenic_usb_phy_init;
0310     priv->phy.shutdown = ingenic_usb_phy_shutdown;
0311
0312     priv->otg.state = OTG_STATE_UNDEFINED;
0313     priv->otg.usb_phy = &priv->phy;
0314     priv->otg.set_host = ingenic_usb_phy_set_host;
0315     priv->otg.set_peripheral = ingenic_usb_phy_set_peripheral;
0316
0317     priv->base = devm_platform_ioremap_resource(pdev, 0);
0318     if (IS_ERR(priv->base)) {
0319         dev_err(dev, "Failed to map registers\n");
0320         return PTR_ERR(priv->base);
0321     }
0322
0323     priv->clk = devm_clk_get(dev, NULL);
0324     if (IS_ERR(priv->clk)) {
0325         err = PTR_ERR(priv->clk);
0326         if (err != -EPROBE_DEFER)
0327             dev_err(dev, "Failed to get clock\n");
0328         return err;
0329     }
0330
0331     priv->vcc_supply = devm_regulator_get(dev, "vcc");
0332     if (IS_ERR(priv->vcc_supply)) {
0333         err = PTR_ERR(priv->vcc_supply);
0334         if (err != -EPROBE_DEFER)
0335             dev_err(dev, "Failed to get regulator\n");
0336         return err;
0337     }
0338
0339     err = usb_add_phy(&priv->phy, USB_PHY_TYPE_USB2);
0340     if (err) {
0341         if (err != -EPROBE_DEFER)
0342             dev_err(dev, "Unable to register PHY\n");
0343         return err;
0344     }
0345
0346     return devm_add_action_or_reset(dev, ingenic_usb_phy_remove, &priv->phy);
0347 }
0348
0349 static struct platform_driver ingenic_phy_driver = {
0350     .probe      = jz4770_phy_probe,
0351     .driver     = {
0352         .name   = "jz4770-phy",
0353         .of_match_table = ingenic_usb_phy_of_matches,
0354     },
0355 };
0356 module_platform_driver(ingenic_phy_driver);
0357
0358 MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>");
0359 MODULE_AUTHOR("漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>");
0360 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
0361 MODULE_DESCRIPTION("Ingenic SoCs USB PHY driver");
0362 MODULE_LICENSE("GPL");