usb/phy/phy-fsl-usb.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /* Copyright (C) 2007,2008 Freescale Semiconductor, Inc. */
0003
0004 #include <linux/usb/otg-fsm.h>
0005 #include <linux/usb/otg.h>
0006 #include <linux/ioctl.h>
0007
0008 /* USB Command Register Bit Masks */
0009 #define USB_CMD_RUN_STOP        (0x1<<0)
0010 #define USB_CMD_CTRL_RESET      (0x1<<1)
0011 #define USB_CMD_PERIODIC_SCHEDULE_EN    (0x1<<4)
0012 #define USB_CMD_ASYNC_SCHEDULE_EN   (0x1<<5)
0013 #define USB_CMD_INT_AA_DOORBELL     (0x1<<6)
0014 #define USB_CMD_ASP         (0x3<<8)
0015 #define USB_CMD_ASYNC_SCH_PARK_EN   (0x1<<11)
0016 #define USB_CMD_SUTW            (0x1<<13)
0017 #define USB_CMD_ATDTW           (0x1<<14)
0018 #define USB_CMD_ITC         (0xFF<<16)
0019
0020 /* bit 15,3,2 are frame list size */
0021 #define USB_CMD_FRAME_SIZE_1024     (0x0<<15 | 0x0<<2)
0022 #define USB_CMD_FRAME_SIZE_512      (0x0<<15 | 0x1<<2)
0023 #define USB_CMD_FRAME_SIZE_256      (0x0<<15 | 0x2<<2)
0024 #define USB_CMD_FRAME_SIZE_128      (0x0<<15 | 0x3<<2)
0025 #define USB_CMD_FRAME_SIZE_64       (0x1<<15 | 0x0<<2)
0026 #define USB_CMD_FRAME_SIZE_32       (0x1<<15 | 0x1<<2)
0027 #define USB_CMD_FRAME_SIZE_16       (0x1<<15 | 0x2<<2)
0028 #define USB_CMD_FRAME_SIZE_8        (0x1<<15 | 0x3<<2)
0029
0030 /* bit 9-8 are async schedule park mode count */
0031 #define USB_CMD_ASP_00          (0x0<<8)
0032 #define USB_CMD_ASP_01          (0x1<<8)
0033 #define USB_CMD_ASP_10          (0x2<<8)
0034 #define USB_CMD_ASP_11          (0x3<<8)
0035 #define USB_CMD_ASP_BIT_POS     (8)
0036
0037 /* bit 23-16 are interrupt threshold control */
0038 #define USB_CMD_ITC_NO_THRESHOLD    (0x00<<16)
0039 #define USB_CMD_ITC_1_MICRO_FRM     (0x01<<16)
0040 #define USB_CMD_ITC_2_MICRO_FRM     (0x02<<16)
0041 #define USB_CMD_ITC_4_MICRO_FRM     (0x04<<16)
0042 #define USB_CMD_ITC_8_MICRO_FRM     (0x08<<16)
0043 #define USB_CMD_ITC_16_MICRO_FRM    (0x10<<16)
0044 #define USB_CMD_ITC_32_MICRO_FRM    (0x20<<16)
0045 #define USB_CMD_ITC_64_MICRO_FRM    (0x40<<16)
0046 #define USB_CMD_ITC_BIT_POS     (16)
0047
0048 /* USB Status Register Bit Masks */
0049 #define USB_STS_INT         (0x1<<0)
0050 #define USB_STS_ERR         (0x1<<1)
0051 #define USB_STS_PORT_CHANGE     (0x1<<2)
0052 #define USB_STS_FRM_LST_ROLL        (0x1<<3)
0053 #define USB_STS_SYS_ERR         (0x1<<4)
0054 #define USB_STS_IAA         (0x1<<5)
0055 #define USB_STS_RESET_RECEIVED      (0x1<<6)
0056 #define USB_STS_SOF         (0x1<<7)
0057 #define USB_STS_DCSUSPEND       (0x1<<8)
0058 #define USB_STS_HC_HALTED       (0x1<<12)
0059 #define USB_STS_RCL         (0x1<<13)
0060 #define USB_STS_PERIODIC_SCHEDULE   (0x1<<14)
0061 #define USB_STS_ASYNC_SCHEDULE      (0x1<<15)
0062
0063 /* USB Interrupt Enable Register Bit Masks */
0064 #define USB_INTR_INT_EN         (0x1<<0)
0065 #define USB_INTR_ERR_INT_EN     (0x1<<1)
0066 #define USB_INTR_PC_DETECT_EN       (0x1<<2)
0067 #define USB_INTR_FRM_LST_ROLL_EN    (0x1<<3)
0068 #define USB_INTR_SYS_ERR_EN     (0x1<<4)
0069 #define USB_INTR_ASYN_ADV_EN        (0x1<<5)
0070 #define USB_INTR_RESET_EN       (0x1<<6)
0071 #define USB_INTR_SOF_EN         (0x1<<7)
0072 #define USB_INTR_DEVICE_SUSPEND     (0x1<<8)
0073
0074 /* Device Address bit masks */
0075 #define USB_DEVICE_ADDRESS_MASK     (0x7F<<25)
0076 #define USB_DEVICE_ADDRESS_BIT_POS  (25)
0077 /* PORTSC  Register Bit Masks,Only one PORT in OTG mode*/
0078 #define PORTSC_CURRENT_CONNECT_STATUS   (0x1<<0)
0079 #define PORTSC_CONNECT_STATUS_CHANGE    (0x1<<1)
0080 #define PORTSC_PORT_ENABLE      (0x1<<2)
0081 #define PORTSC_PORT_EN_DIS_CHANGE   (0x1<<3)
0082 #define PORTSC_OVER_CURRENT_ACT     (0x1<<4)
0083 #define PORTSC_OVER_CUURENT_CHG     (0x1<<5)
0084 #define PORTSC_PORT_FORCE_RESUME    (0x1<<6)
0085 #define PORTSC_PORT_SUSPEND     (0x1<<7)
0086 #define PORTSC_PORT_RESET       (0x1<<8)
0087 #define PORTSC_LINE_STATUS_BITS     (0x3<<10)
0088 #define PORTSC_PORT_POWER       (0x1<<12)
0089 #define PORTSC_PORT_INDICTOR_CTRL   (0x3<<14)
0090 #define PORTSC_PORT_TEST_CTRL       (0xF<<16)
0091 #define PORTSC_WAKE_ON_CONNECT_EN   (0x1<<20)
0092 #define PORTSC_WAKE_ON_CONNECT_DIS  (0x1<<21)
0093 #define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22)
0094 #define PORTSC_PHY_LOW_POWER_SPD    (0x1<<23)
0095 #define PORTSC_PORT_FORCE_FULL_SPEED    (0x1<<24)
0096 #define PORTSC_PORT_SPEED_MASK      (0x3<<26)
0097 #define PORTSC_TRANSCEIVER_WIDTH    (0x1<<28)
0098 #define PORTSC_PHY_TYPE_SEL     (0x3<<30)
0099 /* bit 11-10 are line status */
0100 #define PORTSC_LINE_STATUS_SE0      (0x0<<10)
0101 #define PORTSC_LINE_STATUS_JSTATE   (0x1<<10)
0102 #define PORTSC_LINE_STATUS_KSTATE   (0x2<<10)
0103 #define PORTSC_LINE_STATUS_UNDEF    (0x3<<10)
0104 #define PORTSC_LINE_STATUS_BIT_POS  (10)
0105
0106 /* bit 15-14 are port indicator control */
0107 #define PORTSC_PIC_OFF          (0x0<<14)
0108 #define PORTSC_PIC_AMBER        (0x1<<14)
0109 #define PORTSC_PIC_GREEN        (0x2<<14)
0110 #define PORTSC_PIC_UNDEF        (0x3<<14)
0111 #define PORTSC_PIC_BIT_POS      (14)
0112
0113 /* bit 19-16 are port test control */
0114 #define PORTSC_PTC_DISABLE      (0x0<<16)
0115 #define PORTSC_PTC_JSTATE       (0x1<<16)
0116 #define PORTSC_PTC_KSTATE       (0x2<<16)
0117 #define PORTSC_PTC_SEQNAK       (0x3<<16)
0118 #define PORTSC_PTC_PACKET       (0x4<<16)
0119 #define PORTSC_PTC_FORCE_EN     (0x5<<16)
0120 #define PORTSC_PTC_BIT_POS      (16)
0121
0122 /* bit 27-26 are port speed */
0123 #define PORTSC_PORT_SPEED_FULL      (0x0<<26)
0124 #define PORTSC_PORT_SPEED_LOW       (0x1<<26)
0125 #define PORTSC_PORT_SPEED_HIGH      (0x2<<26)
0126 #define PORTSC_PORT_SPEED_UNDEF     (0x3<<26)
0127 #define PORTSC_SPEED_BIT_POS        (26)
0128
0129 /* bit 28 is parallel transceiver width for UTMI interface */
0130 #define PORTSC_PTW          (0x1<<28)
0131 #define PORTSC_PTW_8BIT         (0x0<<28)
0132 #define PORTSC_PTW_16BIT        (0x1<<28)
0133
0134 /* bit 31-30 are port transceiver select */
0135 #define PORTSC_PTS_UTMI         (0x0<<30)
0136 #define PORTSC_PTS_ULPI         (0x2<<30)
0137 #define PORTSC_PTS_FSLS_SERIAL      (0x3<<30)
0138 #define PORTSC_PTS_BIT_POS      (30)
0139
0140 #define PORTSC_W1C_BITS         \
0141     (PORTSC_CONNECT_STATUS_CHANGE | \
0142      PORTSC_PORT_EN_DIS_CHANGE    | \
0143      PORTSC_OVER_CUURENT_CHG)
0144
0145 /* OTG Status Control Register Bit Masks */
0146 #define OTGSC_CTRL_VBUS_DISCHARGE   (0x1<<0)
0147 #define OTGSC_CTRL_VBUS_CHARGE      (0x1<<1)
0148 #define OTGSC_CTRL_OTG_TERMINATION  (0x1<<3)
0149 #define OTGSC_CTRL_DATA_PULSING     (0x1<<4)
0150 #define OTGSC_CTRL_ID_PULL_EN       (0x1<<5)
0151 #define OTGSC_HA_DATA_PULSE     (0x1<<6)
0152 #define OTGSC_HA_BA         (0x1<<7)
0153 #define OTGSC_STS_USB_ID        (0x1<<8)
0154 #define OTGSC_STS_A_VBUS_VALID      (0x1<<9)
0155 #define OTGSC_STS_A_SESSION_VALID   (0x1<<10)
0156 #define OTGSC_STS_B_SESSION_VALID   (0x1<<11)
0157 #define OTGSC_STS_B_SESSION_END     (0x1<<12)
0158 #define OTGSC_STS_1MS_TOGGLE        (0x1<<13)
0159 #define OTGSC_STS_DATA_PULSING      (0x1<<14)
0160 #define OTGSC_INTSTS_USB_ID     (0x1<<16)
0161 #define OTGSC_INTSTS_A_VBUS_VALID   (0x1<<17)
0162 #define OTGSC_INTSTS_A_SESSION_VALID    (0x1<<18)
0163 #define OTGSC_INTSTS_B_SESSION_VALID    (0x1<<19)
0164 #define OTGSC_INTSTS_B_SESSION_END  (0x1<<20)
0165 #define OTGSC_INTSTS_1MS        (0x1<<21)
0166 #define OTGSC_INTSTS_DATA_PULSING   (0x1<<22)
0167 #define OTGSC_INTR_USB_ID_EN        (0x1<<24)
0168 #define OTGSC_INTR_A_VBUS_VALID_EN  (0x1<<25)
0169 #define OTGSC_INTR_A_SESSION_VALID_EN   (0x1<<26)
0170 #define OTGSC_INTR_B_SESSION_VALID_EN   (0x1<<27)
0171 #define OTGSC_INTR_B_SESSION_END_EN (0x1<<28)
0172 #define OTGSC_INTR_1MS_TIMER_EN     (0x1<<29)
0173 #define OTGSC_INTR_DATA_PULSING_EN  (0x1<<30)
0174 #define OTGSC_INTSTS_MASK       (0x00ff0000)
0175
0176 /* USB MODE Register Bit Masks */
0177 #define  USB_MODE_CTRL_MODE_IDLE    (0x0<<0)
0178 #define  USB_MODE_CTRL_MODE_DEVICE  (0x2<<0)
0179 #define  USB_MODE_CTRL_MODE_HOST    (0x3<<0)
0180 #define  USB_MODE_CTRL_MODE_RSV     (0x1<<0)
0181 #define  USB_MODE_SETUP_LOCK_OFF    (0x1<<3)
0182 #define  USB_MODE_STREAM_DISABLE    (0x1<<4)
0183 #define  USB_MODE_ES            (0x1<<2) /* Endian Select */
0184
0185 /* control Register Bit Masks */
0186 #define  USB_CTRL_IOENB         (0x1<<2)
0187 #define  USB_CTRL_ULPI_INT0EN       (0x1<<0)
0188
0189 /* BCSR5 */
0190 #define BCSR5_INT_USB           (0x02)
0191
0192 /* USB module clk cfg */
0193 #define SCCR_OFFS           (0xA08)
0194 #define SCCR_USB_CLK_DISABLE        (0x00000000)    /* USB clk disable */
0195 #define SCCR_USB_MPHCM_11       (0x00c00000)
0196 #define SCCR_USB_MPHCM_01       (0x00400000)
0197 #define SCCR_USB_MPHCM_10       (0x00800000)
0198 #define SCCR_USB_DRCM_11        (0x00300000)
0199 #define SCCR_USB_DRCM_01        (0x00100000)
0200 #define SCCR_USB_DRCM_10        (0x00200000)
0201
0202 #define SICRL_OFFS          (0x114)
0203 #define SICRL_USB0          (0x40000000)
0204 #define SICRL_USB1          (0x20000000)
0205
0206 #define SICRH_OFFS          (0x118)
0207 #define SICRH_USB_UTMI          (0x00020000)
0208
0209 /* OTG interrupt enable bit masks */
0210 #define  OTGSC_INTERRUPT_ENABLE_BITS_MASK  \
0211     (OTGSC_INTR_USB_ID_EN            | \
0212     OTGSC_INTR_1MS_TIMER_EN      | \
0213     OTGSC_INTR_A_VBUS_VALID_EN       | \
0214     OTGSC_INTR_A_SESSION_VALID_EN    | \
0215     OTGSC_INTR_B_SESSION_VALID_EN    | \
0216     OTGSC_INTR_B_SESSION_END_EN      | \
0217     OTGSC_INTR_DATA_PULSING_EN)
0218
0219 /* OTG interrupt status bit masks */
0220 #define  OTGSC_INTERRUPT_STATUS_BITS_MASK  \
0221     (OTGSC_INTSTS_USB_ID          |    \
0222     OTGSC_INTR_1MS_TIMER_EN       |    \
0223     OTGSC_INTSTS_A_VBUS_VALID     |    \
0224     OTGSC_INTSTS_A_SESSION_VALID  |    \
0225     OTGSC_INTSTS_B_SESSION_VALID  |    \
0226     OTGSC_INTSTS_B_SESSION_END    |    \
0227     OTGSC_INTSTS_DATA_PULSING)
0228
0229 /*
0230  *  A-DEVICE timing  constants
0231  */
0232
0233 /* Wait for VBUS Rise  */
0234 #define TA_WAIT_VRISE   (100)   /* a_wait_vrise 100 ms, section: 6.6.5.1 */
0235
0236 /* Wait for B-Connect */
0237 #define TA_WAIT_BCON    (10000)  /* a_wait_bcon > 1 sec, section: 6.6.5.2
0238                   * This is only used to get out of
0239                   * OTG_STATE_A_WAIT_BCON state if there was
0240                   * no connection for these many milliseconds
0241                   */
0242
0243 /* A-Idle to B-Disconnect */
0244 /* It is necessary for this timer to be more than 750 ms because of a bug in OPT
0245  * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated
0246  * in the test description
0247  */
0248 #define TA_AIDL_BDIS    (5000)  /* a_suspend minimum 200 ms, section: 6.6.5.3 */
0249
0250 /* B-Idle to A-Disconnect */
0251 #define TA_BIDL_ADIS    (12)    /* 3 to 200 ms */
0252
0253 /* B-device timing constants */
0254
0255
0256 /* Data-Line Pulse Time*/
0257 #define TB_DATA_PLS (10)    /* b_srp_init,continue 5~10ms, section:5.3.3 */
0258 #define TB_DATA_PLS_MIN (5) /* minimum 5 ms */
0259 #define TB_DATA_PLS_MAX (10)    /* maximum 10 ms */
0260
0261 /* SRP Initiate Time  */
0262 #define TB_SRP_INIT (100)   /* b_srp_init,maximum 100 ms, section:5.3.8 */
0263
0264 /* SRP Fail Time  */
0265 #define TB_SRP_FAIL (7000)  /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/
0266
0267 /* SRP result wait time */
0268 #define TB_SRP_WAIT (60)
0269
0270 /* VBus time */
0271 #define TB_VBUS_PLS (30)    /* time to keep vbus pulsing asserted */
0272
0273 /* Discharge time */
0274 /* This time should be less than 10ms. It varies from system to system. */
0275 #define TB_VBUS_DSCHRG  (8)
0276
0277 /* A-SE0 to B-Reset  */
0278 #define TB_ASE0_BRST    (20)    /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */
0279
0280 /* A bus suspend timer before we can switch to b_wait_aconn */
0281 #define TB_A_SUSPEND    (7)
0282 #define TB_BUS_RESUME   (12)
0283
0284 /* SE0 Time Before SRP */
0285 #define TB_SE0_SRP  (2) /* b_idle,minimum 2 ms, section:5.3.2 */
0286
0287 #define SET_OTG_STATE(phy, newstate)    ((phy)->otg->state = newstate)
0288
0289 struct usb_dr_mmap {
0290     /* Capability register */
0291     u8 res1[256];
0292     u16 caplength;      /* Capability Register Length */
0293     u16 hciversion;     /* Host Controller Interface Version */
0294     u32 hcsparams;      /* Host Controller Structual Parameters */
0295     u32 hccparams;      /* Host Controller Capability Parameters */
0296     u8 res2[20];
0297     u32 dciversion;     /* Device Controller Interface Version */
0298     u32 dccparams;      /* Device Controller Capability Parameters */
0299     u8 res3[24];
0300     /* Operation register */
0301     u32 usbcmd;     /* USB Command Register */
0302     u32 usbsts;     /* USB Status Register */
0303     u32 usbintr;        /* USB Interrupt Enable Register */
0304     u32 frindex;        /* Frame Index Register */
0305     u8 res4[4];
0306     u32 deviceaddr;     /* Device Address */
0307     u32 endpointlistaddr;   /* Endpoint List Address Register */
0308     u8 res5[4];
0309     u32 burstsize;      /* Master Interface Data Burst Size Register */
0310     u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
0311     u8 res6[8];
0312     u32 ulpiview;       /* ULPI register access */
0313     u8 res7[12];
0314     u32 configflag;     /* Configure Flag Register */
0315     u32 portsc;     /* Port 1 Status and Control Register */
0316     u8 res8[28];
0317     u32 otgsc;      /* On-The-Go Status and Control */
0318     u32 usbmode;        /* USB Mode Register */
0319     u32 endptsetupstat; /* Endpoint Setup Status Register */
0320     u32 endpointprime;  /* Endpoint Initialization Register */
0321     u32 endptflush;     /* Endpoint Flush Register */
0322     u32 endptstatus;    /* Endpoint Status Register */
0323     u32 endptcomplete;  /* Endpoint Complete Register */
0324     u32 endptctrl[6];   /* Endpoint Control Registers */
0325     u8 res9[552];
0326     u32 snoop1;
0327     u32 snoop2;
0328     u32 age_cnt_thresh; /* Age Count Threshold Register */
0329     u32 pri_ctrl;       /* Priority Control Register */
0330     u32 si_ctrl;        /* System Interface Control Register */
0331     u8 res10[236];
0332     u32 control;        /* General Purpose Control Register */
0333 };
0334
0335 struct fsl_otg_timer {
0336     unsigned long expires;  /* Number of count increase to timeout */
0337     unsigned long count;    /* Tick counter */
0338     void (*function)(unsigned long);    /* Timeout function */
0339     unsigned long data; /* Data passed to function */
0340     struct list_head list;
0341 };
0342
0343 inline struct fsl_otg_timer *otg_timer_initializer
0344 (void (*function)(unsigned long), unsigned long expires, unsigned long data)
0345 {
0346     struct fsl_otg_timer *timer;
0347
0348     timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL);
0349     if (!timer)
0350         return NULL;
0351     timer->function = function;
0352     timer->expires = expires;
0353     timer->data = data;
0354     return timer;
0355 }
0356
0357 struct fsl_otg {
0358     struct usb_phy phy;
0359     struct otg_fsm fsm;
0360     struct usb_dr_mmap *dr_mem_map;
0361     struct delayed_work otg_event;
0362
0363     /* used for usb host */
0364     struct work_struct work_wq;
0365     u8  host_working;
0366
0367     int irq;
0368 };
0369
0370 struct fsl_otg_config {
0371     u8 otg_port;
0372 };
0373
0374 #define FSL_OTG_NAME        "fsl-usb2-otg"
0375
0376 void fsl_otg_add_timer(struct otg_fsm *fsm, void *timer);
0377 void fsl_otg_del_timer(struct otg_fsm *fsm, void *timer);
0378 void fsl_otg_pulse_vbus(void);