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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * drivers/usb/musb/ux500_dma.c
0004  *
0005  * U8500 DMA support code
0006  *
0007  * Copyright (C) 2009 STMicroelectronics
0008  * Copyright (C) 2011 ST-Ericsson SA
0009  * Authors:
0010  *  Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
0011  *  Praveena Nadahally <praveen.nadahally@stericsson.com>
0012  *  Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
0013  */
0014 
0015 #include <linux/device.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/dma-mapping.h>
0019 #include <linux/dmaengine.h>
0020 #include <linux/pfn.h>
0021 #include <linux/sizes.h>
0022 #include <linux/platform_data/usb-musb-ux500.h>
0023 #include "musb_core.h"
0024 
0025 static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12",
0026                     "iep_5_13", "iep_6_14", "iep_7_15", "iep_8" };
0027 static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12",
0028                     "oep_5_13", "oep_6_14", "oep_7_15", "oep_8" };
0029 
0030 struct ux500_dma_channel {
0031     struct dma_channel channel;
0032     struct ux500_dma_controller *controller;
0033     struct musb_hw_ep *hw_ep;
0034     struct dma_chan *dma_chan;
0035     unsigned int cur_len;
0036     dma_cookie_t cookie;
0037     u8 ch_num;
0038     u8 is_tx;
0039     u8 is_allocated;
0040 };
0041 
0042 struct ux500_dma_controller {
0043     struct dma_controller controller;
0044     struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
0045     struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
0046     void *private_data;
0047     dma_addr_t phy_base;
0048 };
0049 
0050 /* Work function invoked from DMA callback to handle rx transfers. */
0051 static void ux500_dma_callback(void *private_data)
0052 {
0053     struct dma_channel *channel = private_data;
0054     struct ux500_dma_channel *ux500_channel = channel->private_data;
0055     struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
0056     struct musb *musb = hw_ep->musb;
0057     unsigned long flags;
0058 
0059     dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n",
0060         hw_ep->epnum);
0061 
0062     spin_lock_irqsave(&musb->lock, flags);
0063     ux500_channel->channel.actual_len = ux500_channel->cur_len;
0064     ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
0065     musb_dma_completion(musb, hw_ep->epnum, ux500_channel->is_tx);
0066     spin_unlock_irqrestore(&musb->lock, flags);
0067 
0068 }
0069 
0070 static bool ux500_configure_channel(struct dma_channel *channel,
0071                 u16 packet_sz, u8 mode,
0072                 dma_addr_t dma_addr, u32 len)
0073 {
0074     struct ux500_dma_channel *ux500_channel = channel->private_data;
0075     struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
0076     struct dma_chan *dma_chan = ux500_channel->dma_chan;
0077     struct dma_async_tx_descriptor *dma_desc;
0078     enum dma_transfer_direction direction;
0079     struct scatterlist sg;
0080     struct dma_slave_config slave_conf;
0081     enum dma_slave_buswidth addr_width;
0082     struct musb *musb = ux500_channel->controller->private_data;
0083     dma_addr_t usb_fifo_addr = (musb->io.fifo_offset(hw_ep->epnum) +
0084                     ux500_channel->controller->phy_base);
0085 
0086     dev_dbg(musb->controller,
0087         "packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
0088         packet_sz, mode, (unsigned long long) dma_addr,
0089         len, ux500_channel->is_tx);
0090 
0091     ux500_channel->cur_len = len;
0092 
0093     sg_init_table(&sg, 1);
0094     sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
0095                         offset_in_page(dma_addr));
0096     sg_dma_address(&sg) = dma_addr;
0097     sg_dma_len(&sg) = len;
0098 
0099     direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
0100     addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
0101                     DMA_SLAVE_BUSWIDTH_4_BYTES;
0102 
0103     slave_conf.direction = direction;
0104     slave_conf.src_addr = usb_fifo_addr;
0105     slave_conf.src_addr_width = addr_width;
0106     slave_conf.src_maxburst = 16;
0107     slave_conf.dst_addr = usb_fifo_addr;
0108     slave_conf.dst_addr_width = addr_width;
0109     slave_conf.dst_maxburst = 16;
0110     slave_conf.device_fc = false;
0111 
0112     dmaengine_slave_config(dma_chan, &slave_conf);
0113 
0114     dma_desc = dmaengine_prep_slave_sg(dma_chan, &sg, 1, direction,
0115                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0116     if (!dma_desc)
0117         return false;
0118 
0119     dma_desc->callback = ux500_dma_callback;
0120     dma_desc->callback_param = channel;
0121     ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
0122 
0123     dma_async_issue_pending(dma_chan);
0124 
0125     return true;
0126 }
0127 
0128 static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
0129                 struct musb_hw_ep *hw_ep, u8 is_tx)
0130 {
0131     struct ux500_dma_controller *controller = container_of(c,
0132             struct ux500_dma_controller, controller);
0133     struct ux500_dma_channel *ux500_channel = NULL;
0134     struct musb *musb = controller->private_data;
0135     u8 ch_num = hw_ep->epnum - 1;
0136 
0137     /* 8 DMA channels (0 - 7). Each DMA channel can only be allocated
0138      * to specified hw_ep. For example DMA channel 0 can only be allocated
0139      * to hw_ep 1 and 9.
0140      */
0141     if (ch_num > 7)
0142         ch_num -= 8;
0143 
0144     if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS)
0145         return NULL;
0146 
0147     ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
0148                 &(controller->rx_channel[ch_num]) ;
0149 
0150     /* Check if channel is already used. */
0151     if (ux500_channel->is_allocated)
0152         return NULL;
0153 
0154     ux500_channel->hw_ep = hw_ep;
0155     ux500_channel->is_allocated = 1;
0156 
0157     dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
0158         hw_ep->epnum, is_tx, ch_num);
0159 
0160     return &(ux500_channel->channel);
0161 }
0162 
0163 static void ux500_dma_channel_release(struct dma_channel *channel)
0164 {
0165     struct ux500_dma_channel *ux500_channel = channel->private_data;
0166     struct musb *musb = ux500_channel->controller->private_data;
0167 
0168     dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num);
0169 
0170     if (ux500_channel->is_allocated) {
0171         ux500_channel->is_allocated = 0;
0172         channel->status = MUSB_DMA_STATUS_FREE;
0173         channel->actual_len = 0;
0174     }
0175 }
0176 
0177 static int ux500_dma_is_compatible(struct dma_channel *channel,
0178         u16 maxpacket, void *buf, u32 length)
0179 {
0180     if ((maxpacket & 0x3)       ||
0181         ((unsigned long int) buf & 0x3) ||
0182         (length < 512)      ||
0183         (length & 0x3))
0184         return false;
0185     else
0186         return true;
0187 }
0188 
0189 static int ux500_dma_channel_program(struct dma_channel *channel,
0190                 u16 packet_sz, u8 mode,
0191                 dma_addr_t dma_addr, u32 len)
0192 {
0193     int ret;
0194 
0195     BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
0196         channel->status == MUSB_DMA_STATUS_BUSY);
0197 
0198     channel->status = MUSB_DMA_STATUS_BUSY;
0199     channel->actual_len = 0;
0200     ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
0201     if (!ret)
0202         channel->status = MUSB_DMA_STATUS_FREE;
0203 
0204     return ret;
0205 }
0206 
0207 static int ux500_dma_channel_abort(struct dma_channel *channel)
0208 {
0209     struct ux500_dma_channel *ux500_channel = channel->private_data;
0210     struct ux500_dma_controller *controller = ux500_channel->controller;
0211     struct musb *musb = controller->private_data;
0212     void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
0213     u16 csr;
0214 
0215     dev_dbg(musb->controller, "channel=%d, is_tx=%d\n",
0216         ux500_channel->ch_num, ux500_channel->is_tx);
0217 
0218     if (channel->status == MUSB_DMA_STATUS_BUSY) {
0219         if (ux500_channel->is_tx) {
0220             csr = musb_readw(epio, MUSB_TXCSR);
0221             csr &= ~(MUSB_TXCSR_AUTOSET |
0222                  MUSB_TXCSR_DMAENAB |
0223                  MUSB_TXCSR_DMAMODE);
0224             musb_writew(epio, MUSB_TXCSR, csr);
0225         } else {
0226             csr = musb_readw(epio, MUSB_RXCSR);
0227             csr &= ~(MUSB_RXCSR_AUTOCLEAR |
0228                  MUSB_RXCSR_DMAENAB |
0229                  MUSB_RXCSR_DMAMODE);
0230             musb_writew(epio, MUSB_RXCSR, csr);
0231         }
0232 
0233         dmaengine_terminate_all(ux500_channel->dma_chan);
0234         channel->status = MUSB_DMA_STATUS_FREE;
0235     }
0236     return 0;
0237 }
0238 
0239 static void ux500_dma_controller_stop(struct ux500_dma_controller *controller)
0240 {
0241     struct ux500_dma_channel *ux500_channel;
0242     struct dma_channel *channel;
0243     u8 ch_num;
0244 
0245     for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
0246         channel = &controller->rx_channel[ch_num].channel;
0247         ux500_channel = channel->private_data;
0248 
0249         ux500_dma_channel_release(channel);
0250 
0251         if (ux500_channel->dma_chan)
0252             dma_release_channel(ux500_channel->dma_chan);
0253     }
0254 
0255     for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
0256         channel = &controller->tx_channel[ch_num].channel;
0257         ux500_channel = channel->private_data;
0258 
0259         ux500_dma_channel_release(channel);
0260 
0261         if (ux500_channel->dma_chan)
0262             dma_release_channel(ux500_channel->dma_chan);
0263     }
0264 }
0265 
0266 static int ux500_dma_controller_start(struct ux500_dma_controller *controller)
0267 {
0268     struct ux500_dma_channel *ux500_channel = NULL;
0269     struct musb *musb = controller->private_data;
0270     struct device *dev = musb->controller;
0271     struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
0272     struct ux500_musb_board_data *data;
0273     struct dma_channel *dma_channel = NULL;
0274     char **chan_names;
0275     u32 ch_num;
0276     u8 dir;
0277     u8 is_tx = 0;
0278 
0279     void **param_array;
0280     struct ux500_dma_channel *channel_array;
0281     dma_cap_mask_t mask;
0282 
0283     if (!plat) {
0284         dev_err(musb->controller, "No platform data\n");
0285         return -EINVAL;
0286     }
0287 
0288     data = plat->board_data;
0289 
0290     dma_cap_zero(mask);
0291     dma_cap_set(DMA_SLAVE, mask);
0292 
0293     /* Prepare the loop for RX channels */
0294     channel_array = controller->rx_channel;
0295     param_array = data ? data->dma_rx_param_array : NULL;
0296     chan_names = (char **)iep_chan_names;
0297 
0298     for (dir = 0; dir < 2; dir++) {
0299         for (ch_num = 0;
0300              ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS;
0301              ch_num++) {
0302             ux500_channel = &channel_array[ch_num];
0303             ux500_channel->controller = controller;
0304             ux500_channel->ch_num = ch_num;
0305             ux500_channel->is_tx = is_tx;
0306 
0307             dma_channel = &(ux500_channel->channel);
0308             dma_channel->private_data = ux500_channel;
0309             dma_channel->status = MUSB_DMA_STATUS_FREE;
0310             dma_channel->max_len = SZ_16M;
0311 
0312             ux500_channel->dma_chan =
0313                 dma_request_chan(dev, chan_names[ch_num]);
0314 
0315             if (IS_ERR(ux500_channel->dma_chan))
0316                 ux500_channel->dma_chan =
0317                     dma_request_channel(mask,
0318                                 data ?
0319                                 data->dma_filter :
0320                                 NULL,
0321                                 param_array ?
0322                                 param_array[ch_num] :
0323                                 NULL);
0324 
0325             if (!ux500_channel->dma_chan) {
0326                 ERR("Dma pipe allocation error dir=%d ch=%d\n",
0327                     dir, ch_num);
0328 
0329                 /* Release already allocated channels */
0330                 ux500_dma_controller_stop(controller);
0331 
0332                 return -EBUSY;
0333             }
0334 
0335         }
0336 
0337         /* Prepare the loop for TX channels */
0338         channel_array = controller->tx_channel;
0339         param_array = data ? data->dma_tx_param_array : NULL;
0340         chan_names = (char **)oep_chan_names;
0341         is_tx = 1;
0342     }
0343 
0344     return 0;
0345 }
0346 
0347 void ux500_dma_controller_destroy(struct dma_controller *c)
0348 {
0349     struct ux500_dma_controller *controller = container_of(c,
0350             struct ux500_dma_controller, controller);
0351 
0352     ux500_dma_controller_stop(controller);
0353     kfree(controller);
0354 }
0355 EXPORT_SYMBOL_GPL(ux500_dma_controller_destroy);
0356 
0357 struct dma_controller *
0358 ux500_dma_controller_create(struct musb *musb, void __iomem *base)
0359 {
0360     struct ux500_dma_controller *controller;
0361     struct platform_device *pdev = to_platform_device(musb->controller);
0362     struct resource *iomem;
0363     int ret;
0364 
0365     controller = kzalloc(sizeof(*controller), GFP_KERNEL);
0366     if (!controller)
0367         goto kzalloc_fail;
0368 
0369     controller->private_data = musb;
0370 
0371     /* Save physical address for DMA controller. */
0372     iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0373     if (!iomem) {
0374         dev_err(musb->controller, "no memory resource defined\n");
0375         goto plat_get_fail;
0376     }
0377 
0378     controller->phy_base = (dma_addr_t) iomem->start;
0379 
0380     controller->controller.channel_alloc = ux500_dma_channel_allocate;
0381     controller->controller.channel_release = ux500_dma_channel_release;
0382     controller->controller.channel_program = ux500_dma_channel_program;
0383     controller->controller.channel_abort = ux500_dma_channel_abort;
0384     controller->controller.is_compatible = ux500_dma_is_compatible;
0385 
0386     ret = ux500_dma_controller_start(controller);
0387     if (ret)
0388         goto plat_get_fail;
0389     return &controller->controller;
0390 
0391 plat_get_fail:
0392     kfree(controller);
0393 kzalloc_fail:
0394     return NULL;
0395 }
0396 EXPORT_SYMBOL_GPL(ux500_dma_controller_create);
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