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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * TUSB6010 USB 2.0 OTG Dual Role controller
0004  *
0005  * Copyright (C) 2006 Nokia Corporation
0006  * Tony Lindgren <tony@atomide.com>
0007  *
0008  * Notes:
0009  * - Driver assumes that interface to external host (main CPU) is
0010  *   configured for NOR FLASH interface instead of VLYNQ serial
0011  *   interface.
0012  */
0013 
0014 #include <linux/module.h>
0015 #include <linux/kernel.h>
0016 #include <linux/errno.h>
0017 #include <linux/err.h>
0018 #include <linux/prefetch.h>
0019 #include <linux/usb.h>
0020 #include <linux/irq.h>
0021 #include <linux/io.h>
0022 #include <linux/device.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/dma-mapping.h>
0025 #include <linux/usb/usb_phy_generic.h>
0026 
0027 #include "musb_core.h"
0028 
0029 struct tusb6010_glue {
0030     struct device       *dev;
0031     struct platform_device  *musb;
0032     struct platform_device  *phy;
0033 };
0034 
0035 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
0036 
0037 #define TUSB_REV_MAJOR(reg_val)     ((reg_val >> 4) & 0xf)
0038 #define TUSB_REV_MINOR(reg_val)     (reg_val & 0xf)
0039 
0040 /*
0041  * Checks the revision. We need to use the DMA register as 3.0 does not
0042  * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
0043  */
0044 static u8 tusb_get_revision(struct musb *musb)
0045 {
0046     void __iomem    *tbase = musb->ctrl_base;
0047     u32     die_id;
0048     u8      rev;
0049 
0050     rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
0051     if (TUSB_REV_MAJOR(rev) == 3) {
0052         die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
0053                 TUSB_DIDR1_HI));
0054         if (die_id >= TUSB_DIDR1_HI_REV_31)
0055             rev |= 1;
0056     }
0057 
0058     return rev;
0059 }
0060 
0061 static void tusb_print_revision(struct musb *musb)
0062 {
0063     void __iomem    *tbase = musb->ctrl_base;
0064     u8      rev;
0065 
0066     rev = musb->tusb_revision;
0067 
0068     pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
0069         "prcm",
0070         TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
0071         TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
0072         "int",
0073         TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
0074         TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
0075         "gpio",
0076         TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
0077         TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
0078         "dma",
0079         TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
0080         TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
0081         "dieid",
0082         TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
0083         "rev",
0084         TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
0085 }
0086 
0087 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
0088                 | TUSB_PHY_OTG_CTRL_TESTM0)
0089 
0090 /*
0091  * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
0092  * Disables power detection in PHY for the duration of idle.
0093  */
0094 static void tusb_wbus_quirk(struct musb *musb, int enabled)
0095 {
0096     void __iomem    *tbase = musb->ctrl_base;
0097     static u32  phy_otg_ctrl, phy_otg_ena;
0098     u32     tmp;
0099 
0100     if (enabled) {
0101         phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
0102         phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
0103         tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
0104                 | phy_otg_ena | WBUS_QUIRK_MASK;
0105         musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
0106         tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
0107         tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
0108         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
0109         dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
0110             musb_readl(tbase, TUSB_PHY_OTG_CTRL),
0111             musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
0112     } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
0113                     & TUSB_PHY_OTG_CTRL_TESTM2) {
0114         tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
0115         musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
0116         tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
0117         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
0118         dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
0119             musb_readl(tbase, TUSB_PHY_OTG_CTRL),
0120             musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
0121         phy_otg_ctrl = 0;
0122         phy_otg_ena = 0;
0123     }
0124 }
0125 
0126 static u32 tusb_fifo_offset(u8 epnum)
0127 {
0128     return 0x200 + (epnum * 0x20);
0129 }
0130 
0131 static u32 tusb_ep_offset(u8 epnum, u16 offset)
0132 {
0133     return 0x10 + offset;
0134 }
0135 
0136 /* TUSB mapping: "flat" plus ep0 special cases */
0137 static void tusb_ep_select(void __iomem *mbase, u8 epnum)
0138 {
0139     musb_writeb(mbase, MUSB_INDEX, epnum);
0140 }
0141 
0142 /*
0143  * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
0144  */
0145 static u8 tusb_readb(void __iomem *addr, u32 offset)
0146 {
0147     u16 tmp;
0148     u8 val;
0149 
0150     tmp = __raw_readw(addr + (offset & ~1));
0151     if (offset & 1)
0152         val = (tmp >> 8);
0153     else
0154         val = tmp & 0xff;
0155 
0156     return val;
0157 }
0158 
0159 static void tusb_writeb(void __iomem *addr, u32 offset, u8 data)
0160 {
0161     u16 tmp;
0162 
0163     tmp = __raw_readw(addr + (offset & ~1));
0164     if (offset & 1)
0165         tmp = (data << 8) | (tmp & 0xff);
0166     else
0167         tmp = (tmp & 0xff00) | data;
0168 
0169     __raw_writew(tmp, addr + (offset & ~1));
0170 }
0171 
0172 /*
0173  * TUSB 6010 may use a parallel bus that doesn't support byte ops;
0174  * so both loading and unloading FIFOs need explicit byte counts.
0175  */
0176 
0177 static inline void
0178 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
0179 {
0180     u32     val;
0181     int     i;
0182 
0183     if (len > 4) {
0184         for (i = 0; i < (len >> 2); i++) {
0185             memcpy(&val, buf, 4);
0186             musb_writel(fifo, 0, val);
0187             buf += 4;
0188         }
0189         len %= 4;
0190     }
0191     if (len > 0) {
0192         /* Write the rest 1 - 3 bytes to FIFO */
0193         val = 0;
0194         memcpy(&val, buf, len);
0195         musb_writel(fifo, 0, val);
0196     }
0197 }
0198 
0199 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
0200                         void *buf, u16 len)
0201 {
0202     u32     val;
0203     int     i;
0204 
0205     if (len > 4) {
0206         for (i = 0; i < (len >> 2); i++) {
0207             val = musb_readl(fifo, 0);
0208             memcpy(buf, &val, 4);
0209             buf += 4;
0210         }
0211         len %= 4;
0212     }
0213     if (len > 0) {
0214         /* Read the rest 1 - 3 bytes from FIFO */
0215         val = musb_readl(fifo, 0);
0216         memcpy(buf, &val, len);
0217     }
0218 }
0219 
0220 static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
0221 {
0222     struct musb *musb = hw_ep->musb;
0223     void __iomem    *ep_conf = hw_ep->conf;
0224     void __iomem    *fifo = hw_ep->fifo;
0225     u8      epnum = hw_ep->epnum;
0226 
0227     prefetch(buf);
0228 
0229     dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
0230             'T', epnum, fifo, len, buf);
0231 
0232     if (epnum)
0233         musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
0234             TUSB_EP_CONFIG_XFR_SIZE(len));
0235     else
0236         musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
0237             TUSB_EP0_CONFIG_XFR_SIZE(len));
0238 
0239     if (likely((0x01 & (unsigned long) buf) == 0)) {
0240 
0241         /* Best case is 32bit-aligned destination address */
0242         if ((0x02 & (unsigned long) buf) == 0) {
0243             if (len >= 4) {
0244                 iowrite32_rep(fifo, buf, len >> 2);
0245                 buf += (len & ~0x03);
0246                 len &= 0x03;
0247             }
0248         } else {
0249             if (len >= 2) {
0250                 u32 val;
0251                 int i;
0252 
0253                 /* Cannot use writesw, fifo is 32-bit */
0254                 for (i = 0; i < (len >> 2); i++) {
0255                     val = (u32)(*(u16 *)buf);
0256                     buf += 2;
0257                     val |= (*(u16 *)buf) << 16;
0258                     buf += 2;
0259                     musb_writel(fifo, 0, val);
0260                 }
0261                 len &= 0x03;
0262             }
0263         }
0264     }
0265 
0266     if (len > 0)
0267         tusb_fifo_write_unaligned(fifo, buf, len);
0268 }
0269 
0270 static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
0271 {
0272     struct musb *musb = hw_ep->musb;
0273     void __iomem    *ep_conf = hw_ep->conf;
0274     void __iomem    *fifo = hw_ep->fifo;
0275     u8      epnum = hw_ep->epnum;
0276 
0277     dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
0278             'R', epnum, fifo, len, buf);
0279 
0280     if (epnum)
0281         musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
0282             TUSB_EP_CONFIG_XFR_SIZE(len));
0283     else
0284         musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
0285 
0286     if (likely((0x01 & (unsigned long) buf) == 0)) {
0287 
0288         /* Best case is 32bit-aligned destination address */
0289         if ((0x02 & (unsigned long) buf) == 0) {
0290             if (len >= 4) {
0291                 ioread32_rep(fifo, buf, len >> 2);
0292                 buf += (len & ~0x03);
0293                 len &= 0x03;
0294             }
0295         } else {
0296             if (len >= 2) {
0297                 u32 val;
0298                 int i;
0299 
0300                 /* Cannot use readsw, fifo is 32-bit */
0301                 for (i = 0; i < (len >> 2); i++) {
0302                     val = musb_readl(fifo, 0);
0303                     *(u16 *)buf = (u16)(val & 0xffff);
0304                     buf += 2;
0305                     *(u16 *)buf = (u16)(val >> 16);
0306                     buf += 2;
0307                 }
0308                 len &= 0x03;
0309             }
0310         }
0311     }
0312 
0313     if (len > 0)
0314         tusb_fifo_read_unaligned(fifo, buf, len);
0315 }
0316 
0317 static struct musb *the_musb;
0318 
0319 /* This is used by gadget drivers, and OTG transceiver logic, allowing
0320  * at most mA current to be drawn from VBUS during a Default-B session
0321  * (that is, while VBUS exceeds 4.4V).  In Default-A (including pure host
0322  * mode), or low power Default-B sessions, something else supplies power.
0323  * Caller must take care of locking.
0324  */
0325 static int tusb_draw_power(struct usb_phy *x, unsigned mA)
0326 {
0327     struct musb *musb = the_musb;
0328     void __iomem    *tbase = musb->ctrl_base;
0329     u32     reg;
0330 
0331     /* tps65030 seems to consume max 100mA, with maybe 60mA available
0332      * (measured on one board) for things other than tps and tusb.
0333      *
0334      * Boards sharing the CPU clock with CLKIN will need to prevent
0335      * certain idle sleep states while the USB link is active.
0336      *
0337      * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
0338      * The actual current usage would be very board-specific.  For now,
0339      * it's simpler to just use an aggregate (also board-specific).
0340      */
0341     if (x->otg->default_a || mA < (musb->min_power << 1))
0342         mA = 0;
0343 
0344     reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
0345     if (mA) {
0346         musb->is_bus_powered = 1;
0347         reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
0348     } else {
0349         musb->is_bus_powered = 0;
0350         reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
0351     }
0352     musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
0353 
0354     dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
0355     return 0;
0356 }
0357 
0358 /* workaround for issue 13:  change clock during chip idle
0359  * (to be fixed in rev3 silicon) ... symptoms include disconnect
0360  * or looping suspend/resume cycles
0361  */
0362 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
0363 {
0364     void __iomem    *tbase = musb->ctrl_base;
0365     u32     reg;
0366 
0367     reg = musb_readl(tbase, TUSB_PRCM_CONF);
0368     reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
0369 
0370     /* 0 = refclk (clkin, XI)
0371      * 1 = PHY 60 MHz (internal PLL)
0372      * 2 = not supported
0373      * 3 = what?
0374      */
0375     if (mode > 0)
0376         reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
0377 
0378     musb_writel(tbase, TUSB_PRCM_CONF, reg);
0379 
0380     /* FIXME tusb6010_platform_retime(mode == 0); */
0381 }
0382 
0383 /*
0384  * Idle TUSB6010 until next wake-up event; NOR access always wakes.
0385  * Other code ensures that we idle unless we're connected _and_ the
0386  * USB link is not suspended ... and tells us the relevant wakeup
0387  * events.  SW_EN for voltage is handled separately.
0388  */
0389 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
0390 {
0391     void __iomem    *tbase = musb->ctrl_base;
0392     u32     reg;
0393 
0394     if ((wakeup_enables & TUSB_PRCM_WBUS)
0395             && (musb->tusb_revision == TUSB_REV_30))
0396         tusb_wbus_quirk(musb, 1);
0397 
0398     tusb_set_clock_source(musb, 0);
0399 
0400     wakeup_enables |= TUSB_PRCM_WNORCS;
0401     musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
0402 
0403     /* REVISIT writeup of WID implies that if WID set and ID is grounded,
0404      * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
0405      * Presumably that's mostly to save power, hence WID is immaterial ...
0406      */
0407 
0408     reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
0409     /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
0410     if (is_host_active(musb)) {
0411         reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
0412         reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
0413     } else {
0414         reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
0415         reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
0416     }
0417     reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
0418     musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
0419 
0420     dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
0421 }
0422 
0423 /*
0424  * Updates cable VBUS status. Caller must take care of locking.
0425  */
0426 static int tusb_musb_vbus_status(struct musb *musb)
0427 {
0428     void __iomem    *tbase = musb->ctrl_base;
0429     u32     otg_stat, prcm_mngmt;
0430     int     ret = 0;
0431 
0432     otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
0433     prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
0434 
0435     /* Temporarily enable VBUS detection if it was disabled for
0436      * suspend mode. Unless it's enabled otg_stat and devctl will
0437      * not show correct VBUS state.
0438      */
0439     if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
0440         u32 tmp = prcm_mngmt;
0441         tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
0442         musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
0443         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
0444         musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
0445     }
0446 
0447     if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
0448         ret = 1;
0449 
0450     return ret;
0451 }
0452 
0453 static void musb_do_idle(struct timer_list *t)
0454 {
0455     struct musb *musb = from_timer(musb, t, dev_timer);
0456     unsigned long   flags;
0457 
0458     spin_lock_irqsave(&musb->lock, flags);
0459 
0460     switch (musb->xceiv->otg->state) {
0461     case OTG_STATE_A_WAIT_BCON:
0462         if ((musb->a_wait_bcon != 0)
0463             && (musb->idle_timeout == 0
0464                 || time_after(jiffies, musb->idle_timeout))) {
0465             dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
0466                     usb_otg_state_string(musb->xceiv->otg->state));
0467         }
0468         fallthrough;
0469     case OTG_STATE_A_IDLE:
0470         tusb_musb_set_vbus(musb, 0);
0471         break;
0472     default:
0473         break;
0474     }
0475 
0476     if (!musb->is_active) {
0477         u32 wakeups;
0478 
0479         /* wait until hub_wq handles port change status */
0480         if (is_host_active(musb) && (musb->port1_status >> 16))
0481             goto done;
0482 
0483         if (!musb->gadget_driver) {
0484             wakeups = 0;
0485         } else {
0486             wakeups = TUSB_PRCM_WHOSTDISCON
0487                 | TUSB_PRCM_WBUS
0488                     | TUSB_PRCM_WVBUS;
0489             wakeups |= TUSB_PRCM_WID;
0490         }
0491         tusb_allow_idle(musb, wakeups);
0492     }
0493 done:
0494     spin_unlock_irqrestore(&musb->lock, flags);
0495 }
0496 
0497 /*
0498  * Maybe put TUSB6010 into idle mode depending on USB link status,
0499  * like "disconnected" or "suspended".  We'll be woken out of it by
0500  * connect, resume, or disconnect.
0501  *
0502  * Needs to be called as the last function everywhere where there is
0503  * register access to TUSB6010 because of NOR flash wake-up.
0504  * Caller should own controller spinlock.
0505  *
0506  * Delay because peripheral enables D+ pullup 3msec after SE0, and
0507  * we don't want to treat that full speed J as a wakeup event.
0508  * ... peripherals must draw only suspend current after 10 msec.
0509  */
0510 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
0511 {
0512     unsigned long       default_timeout = jiffies + msecs_to_jiffies(3);
0513     static unsigned long    last_timer;
0514 
0515     if (timeout == 0)
0516         timeout = default_timeout;
0517 
0518     /* Never idle if active, or when VBUS timeout is not set as host */
0519     if (musb->is_active || ((musb->a_wait_bcon == 0)
0520             && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) {
0521         dev_dbg(musb->controller, "%s active, deleting timer\n",
0522             usb_otg_state_string(musb->xceiv->otg->state));
0523         del_timer(&musb->dev_timer);
0524         last_timer = jiffies;
0525         return;
0526     }
0527 
0528     if (time_after(last_timer, timeout)) {
0529         if (!timer_pending(&musb->dev_timer))
0530             last_timer = timeout;
0531         else {
0532             dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
0533             return;
0534         }
0535     }
0536     last_timer = timeout;
0537 
0538     dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
0539         usb_otg_state_string(musb->xceiv->otg->state),
0540         (unsigned long)jiffies_to_msecs(timeout - jiffies));
0541     mod_timer(&musb->dev_timer, timeout);
0542 }
0543 
0544 /* ticks of 60 MHz clock */
0545 #define DEVCLOCK        60000000
0546 #define OTG_TIMER_MS(msecs) ((msecs) \
0547         ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
0548                 | TUSB_DEV_OTG_TIMER_ENABLE) \
0549         : 0)
0550 
0551 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
0552 {
0553     void __iomem    *tbase = musb->ctrl_base;
0554     u32     conf, prcm, timer;
0555     u8      devctl;
0556     struct usb_otg  *otg = musb->xceiv->otg;
0557 
0558     /* HDRC controls CPEN, but beware current surges during device
0559      * connect.  They can trigger transient overcurrent conditions
0560      * that must be ignored.
0561      */
0562 
0563     prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
0564     conf = musb_readl(tbase, TUSB_DEV_CONF);
0565     devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
0566 
0567     if (is_on) {
0568         timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
0569         otg->default_a = 1;
0570         musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
0571         devctl |= MUSB_DEVCTL_SESSION;
0572 
0573         conf |= TUSB_DEV_CONF_USB_HOST_MODE;
0574         MUSB_HST_MODE(musb);
0575     } else {
0576         u32 otg_stat;
0577 
0578         timer = 0;
0579 
0580         /* If ID pin is grounded, we want to be a_idle */
0581         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
0582         if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
0583             switch (musb->xceiv->otg->state) {
0584             case OTG_STATE_A_WAIT_VRISE:
0585             case OTG_STATE_A_WAIT_BCON:
0586                 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
0587                 break;
0588             case OTG_STATE_A_WAIT_VFALL:
0589                 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
0590                 break;
0591             default:
0592                 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
0593             }
0594             musb->is_active = 0;
0595             otg->default_a = 1;
0596             MUSB_HST_MODE(musb);
0597         } else {
0598             musb->is_active = 0;
0599             otg->default_a = 0;
0600             musb->xceiv->otg->state = OTG_STATE_B_IDLE;
0601             MUSB_DEV_MODE(musb);
0602         }
0603 
0604         devctl &= ~MUSB_DEVCTL_SESSION;
0605         conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
0606     }
0607     prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
0608 
0609     musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
0610     musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
0611     musb_writel(tbase, TUSB_DEV_CONF, conf);
0612     musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
0613 
0614     dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
0615         usb_otg_state_string(musb->xceiv->otg->state),
0616         musb_readb(musb->mregs, MUSB_DEVCTL),
0617         musb_readl(tbase, TUSB_DEV_OTG_STAT),
0618         conf, prcm);
0619 }
0620 
0621 /*
0622  * Sets the mode to OTG, peripheral or host by changing the ID detection.
0623  * Caller must take care of locking.
0624  *
0625  * Note that if a mini-A cable is plugged in the ID line will stay down as
0626  * the weak ID pull-up is not able to pull the ID up.
0627  */
0628 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
0629 {
0630     void __iomem    *tbase = musb->ctrl_base;
0631     u32     otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
0632 
0633     otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
0634     phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
0635     phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
0636     dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
0637 
0638     switch (musb_mode) {
0639 
0640     case MUSB_HOST:     /* Disable PHY ID detect, ground ID */
0641         phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
0642         phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
0643         dev_conf |= TUSB_DEV_CONF_ID_SEL;
0644         dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
0645         break;
0646     case MUSB_PERIPHERAL:   /* Disable PHY ID detect, keep ID pull-up on */
0647         phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
0648         phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
0649         dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
0650         break;
0651     case MUSB_OTG:      /* Use PHY ID detection */
0652         phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
0653         phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
0654         dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
0655         break;
0656 
0657     default:
0658         dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
0659         return -EINVAL;
0660     }
0661 
0662     musb_writel(tbase, TUSB_PHY_OTG_CTRL,
0663             TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
0664     musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
0665             TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
0666     musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
0667 
0668     otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
0669     if ((musb_mode == MUSB_PERIPHERAL) &&
0670         !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
0671             INFO("Cannot be peripheral with mini-A cable "
0672             "otg_stat: %08x\n", otg_stat);
0673 
0674     return 0;
0675 }
0676 
0677 static inline unsigned long
0678 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
0679 {
0680     u32     otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
0681     unsigned long   idle_timeout = 0;
0682     struct usb_otg  *otg = musb->xceiv->otg;
0683 
0684     /* ID pin */
0685     if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
0686         int default_a;
0687 
0688         default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
0689         dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
0690         otg->default_a = default_a;
0691         tusb_musb_set_vbus(musb, default_a);
0692 
0693         /* Don't allow idling immediately */
0694         if (default_a)
0695             idle_timeout = jiffies + (HZ * 3);
0696     }
0697 
0698     /* VBUS state change */
0699     if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
0700 
0701         /* B-dev state machine:  no vbus ~= disconnect */
0702         if (!otg->default_a) {
0703             /* ? musb_root_disconnect(musb); */
0704             musb->port1_status &=
0705                 ~(USB_PORT_STAT_CONNECTION
0706                 | USB_PORT_STAT_ENABLE
0707                 | USB_PORT_STAT_LOW_SPEED
0708                 | USB_PORT_STAT_HIGH_SPEED
0709                 | USB_PORT_STAT_TEST
0710                 );
0711 
0712             if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
0713                 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
0714                 if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) {
0715                     /* INTR_DISCONNECT can hide... */
0716                     musb->xceiv->otg->state = OTG_STATE_B_IDLE;
0717                     musb->int_usb |= MUSB_INTR_DISCONNECT;
0718                 }
0719                 musb->is_active = 0;
0720             }
0721             dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
0722                 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
0723             idle_timeout = jiffies + (1 * HZ);
0724             schedule_delayed_work(&musb->irq_work, 0);
0725 
0726         } else /* A-dev state machine */ {
0727             dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
0728                 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
0729 
0730             switch (musb->xceiv->otg->state) {
0731             case OTG_STATE_A_IDLE:
0732                 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
0733                 musb_platform_set_vbus(musb, 1);
0734 
0735                 /* CONNECT can wake if a_wait_bcon is set */
0736                 if (musb->a_wait_bcon != 0)
0737                     musb->is_active = 0;
0738                 else
0739                     musb->is_active = 1;
0740 
0741                 /*
0742                  * OPT FS A TD.4.6 needs few seconds for
0743                  * A_WAIT_VRISE
0744                  */
0745                 idle_timeout = jiffies + (2 * HZ);
0746 
0747                 break;
0748             case OTG_STATE_A_WAIT_VRISE:
0749                 /* ignore; A-session-valid < VBUS_VALID/2,
0750                  * we monitor this with the timer
0751                  */
0752                 break;
0753             case OTG_STATE_A_WAIT_VFALL:
0754                 /* REVISIT this irq triggers during short
0755                  * spikes caused by enumeration ...
0756                  */
0757                 if (musb->vbuserr_retry) {
0758                     musb->vbuserr_retry--;
0759                     tusb_musb_set_vbus(musb, 1);
0760                 } else {
0761                     musb->vbuserr_retry
0762                         = VBUSERR_RETRY_COUNT;
0763                     tusb_musb_set_vbus(musb, 0);
0764                 }
0765                 break;
0766             default:
0767                 break;
0768             }
0769         }
0770     }
0771 
0772     /* OTG timer expiration */
0773     if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
0774         u8  devctl;
0775 
0776         dev_dbg(musb->controller, "%s timer, %03x\n",
0777             usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
0778 
0779         switch (musb->xceiv->otg->state) {
0780         case OTG_STATE_A_WAIT_VRISE:
0781             /* VBUS has probably been valid for a while now,
0782              * but may well have bounced out of range a bit
0783              */
0784             devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
0785             if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
0786                 if ((devctl & MUSB_DEVCTL_VBUS)
0787                         != MUSB_DEVCTL_VBUS) {
0788                     dev_dbg(musb->controller, "devctl %02x\n", devctl);
0789                     break;
0790                 }
0791                 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
0792                 musb->is_active = 0;
0793                 idle_timeout = jiffies
0794                     + msecs_to_jiffies(musb->a_wait_bcon);
0795             } else {
0796                 /* REVISIT report overcurrent to hub? */
0797                 ERR("vbus too slow, devctl %02x\n", devctl);
0798                 tusb_musb_set_vbus(musb, 0);
0799             }
0800             break;
0801         case OTG_STATE_A_WAIT_BCON:
0802             if (musb->a_wait_bcon != 0)
0803                 idle_timeout = jiffies
0804                     + msecs_to_jiffies(musb->a_wait_bcon);
0805             break;
0806         case OTG_STATE_A_SUSPEND:
0807             break;
0808         case OTG_STATE_B_WAIT_ACON:
0809             break;
0810         default:
0811             break;
0812         }
0813     }
0814     schedule_delayed_work(&musb->irq_work, 0);
0815 
0816     return idle_timeout;
0817 }
0818 
0819 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
0820 {
0821     struct musb *musb = __hci;
0822     void __iomem    *tbase = musb->ctrl_base;
0823     unsigned long   flags, idle_timeout = 0;
0824     u32     int_mask, int_src;
0825 
0826     spin_lock_irqsave(&musb->lock, flags);
0827 
0828     /* Mask all interrupts to allow using both edge and level GPIO irq */
0829     int_mask = musb_readl(tbase, TUSB_INT_MASK);
0830     musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
0831 
0832     int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
0833     dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
0834 
0835     musb->int_usb = (u8) int_src;
0836 
0837     /* Acknowledge wake-up source interrupts */
0838     if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
0839         u32 reg;
0840         u32 i;
0841 
0842         if (musb->tusb_revision == TUSB_REV_30)
0843             tusb_wbus_quirk(musb, 0);
0844 
0845         /* there are issues re-locking the PLL on wakeup ... */
0846 
0847         /* work around issue 8 */
0848         for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
0849             musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
0850             musb_writel(tbase, TUSB_SCRATCH_PAD, i);
0851             reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
0852             if (reg == i)
0853                 break;
0854             dev_dbg(musb->controller, "TUSB NOR not ready\n");
0855         }
0856 
0857         /* work around issue 13 (2nd half) */
0858         tusb_set_clock_source(musb, 1);
0859 
0860         reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
0861         musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
0862         if (reg & ~TUSB_PRCM_WNORCS) {
0863             musb->is_active = 1;
0864             schedule_delayed_work(&musb->irq_work, 0);
0865         }
0866         dev_dbg(musb->controller, "wake %sactive %02x\n",
0867                 musb->is_active ? "" : "in", reg);
0868 
0869         /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
0870     }
0871 
0872     if (int_src & TUSB_INT_SRC_USB_IP_CONN)
0873         del_timer(&musb->dev_timer);
0874 
0875     /* OTG state change reports (annoyingly) not issued by Mentor core */
0876     if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
0877                 | TUSB_INT_SRC_OTG_TIMEOUT
0878                 | TUSB_INT_SRC_ID_STATUS_CHNG))
0879         idle_timeout = tusb_otg_ints(musb, int_src, tbase);
0880 
0881     /*
0882      * Just clear the DMA interrupt if it comes as the completion for both
0883      * TX and RX is handled by the DMA callback in tusb6010_omap
0884      */
0885     if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
0886         u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
0887 
0888         dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
0889         musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
0890     }
0891 
0892     /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
0893     if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
0894         u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
0895 
0896         musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
0897         musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
0898         musb->int_tx = (musb_src & 0xffff);
0899     } else {
0900         musb->int_rx = 0;
0901         musb->int_tx = 0;
0902     }
0903 
0904     if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
0905         musb_interrupt(musb);
0906 
0907     /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
0908     musb_writel(tbase, TUSB_INT_SRC_CLEAR,
0909         int_src & ~TUSB_INT_MASK_RESERVED_BITS);
0910 
0911     tusb_musb_try_idle(musb, idle_timeout);
0912 
0913     musb_writel(tbase, TUSB_INT_MASK, int_mask);
0914     spin_unlock_irqrestore(&musb->lock, flags);
0915 
0916     return IRQ_HANDLED;
0917 }
0918 
0919 static int dma_off;
0920 
0921 /*
0922  * Enables TUSB6010. Caller must take care of locking.
0923  * REVISIT:
0924  * - Check what is unnecessary in MGC_HdrcStart()
0925  */
0926 static void tusb_musb_enable(struct musb *musb)
0927 {
0928     void __iomem    *tbase = musb->ctrl_base;
0929 
0930     /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
0931      * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
0932     musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
0933 
0934     /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
0935     musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
0936     musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
0937     musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
0938 
0939     /* Clear all subsystem interrups */
0940     musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
0941     musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
0942     musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
0943 
0944     /* Acknowledge pending interrupt(s) */
0945     musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
0946 
0947     /* Only 0 clock cycles for minimum interrupt de-assertion time and
0948      * interrupt polarity active low seems to work reliably here */
0949     musb_writel(tbase, TUSB_INT_CTRL_CONF,
0950             TUSB_INT_CTRL_CONF_INT_RELCYC(0));
0951 
0952     irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
0953 
0954     /* maybe force into the Default-A OTG state machine */
0955     if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
0956             & TUSB_DEV_OTG_STAT_ID_STATUS))
0957         musb_writel(tbase, TUSB_INT_SRC_SET,
0958                 TUSB_INT_SRC_ID_STATUS_CHNG);
0959 
0960     if (is_dma_capable() && dma_off)
0961         printk(KERN_WARNING "%s %s: dma not reactivated\n",
0962                 __FILE__, __func__);
0963     else
0964         dma_off = 1;
0965 }
0966 
0967 /*
0968  * Disables TUSB6010. Caller must take care of locking.
0969  */
0970 static void tusb_musb_disable(struct musb *musb)
0971 {
0972     void __iomem    *tbase = musb->ctrl_base;
0973 
0974     /* FIXME stop DMA, IRQs, timers, ... */
0975 
0976     /* disable all IRQs */
0977     musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
0978     musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
0979     musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
0980     musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
0981 
0982     del_timer(&musb->dev_timer);
0983 
0984     if (is_dma_capable() && !dma_off) {
0985         printk(KERN_WARNING "%s %s: dma still active\n",
0986                 __FILE__, __func__);
0987         dma_off = 1;
0988     }
0989 }
0990 
0991 /*
0992  * Sets up TUSB6010 CPU interface specific signals and registers
0993  * Note: Settings optimized for OMAP24xx
0994  */
0995 static void tusb_setup_cpu_interface(struct musb *musb)
0996 {
0997     void __iomem    *tbase = musb->ctrl_base;
0998 
0999     /*
1000      * Disable GPIO[5:0] pullups (used as output DMA requests)
1001      * Don't disable GPIO[7:6] as they are needed for wake-up.
1002      */
1003     musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1004 
1005     /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1006     musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1007 
1008     /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1009     musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1010 
1011     /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1012      * de-assertion time 2 system clocks p 62 */
1013     musb_writel(tbase, TUSB_DMA_REQ_CONF,
1014         TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1015         TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1016         TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1017 
1018     /* Set 0 wait count for synchronous burst access */
1019     musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1020 }
1021 
1022 static int tusb_musb_start(struct musb *musb)
1023 {
1024     void __iomem    *tbase = musb->ctrl_base;
1025     int     ret = 0;
1026     unsigned long   flags;
1027     u32     reg;
1028 
1029     if (musb->board_set_power)
1030         ret = musb->board_set_power(1);
1031     if (ret != 0) {
1032         printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1033         return ret;
1034     }
1035 
1036     spin_lock_irqsave(&musb->lock, flags);
1037 
1038     if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1039         TUSB_PROD_TEST_RESET_VAL) {
1040         printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1041         goto err;
1042     }
1043 
1044     musb->tusb_revision = tusb_get_revision(musb);
1045     tusb_print_revision(musb);
1046     if (musb->tusb_revision < 2) {
1047         printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1048                 musb->tusb_revision);
1049         goto err;
1050     }
1051 
1052     /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1053      * NOR FLASH interface is used */
1054     musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1055 
1056     /* Select PHY free running 60MHz as a system clock */
1057     tusb_set_clock_source(musb, 1);
1058 
1059     /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1060      * power saving, enable VBus detect and session end comparators,
1061      * enable IDpullup, enable VBus charging */
1062     musb_writel(tbase, TUSB_PRCM_MNGMT,
1063         TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1064         TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1065         TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1066         TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1067         TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1068     tusb_setup_cpu_interface(musb);
1069 
1070     /* simplify:  always sense/pullup ID pins, as if in OTG mode */
1071     reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1072     reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1073     musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1074 
1075     reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1076     reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1077     musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1078 
1079     spin_unlock_irqrestore(&musb->lock, flags);
1080 
1081     return 0;
1082 
1083 err:
1084     spin_unlock_irqrestore(&musb->lock, flags);
1085 
1086     if (musb->board_set_power)
1087         musb->board_set_power(0);
1088 
1089     return -ENODEV;
1090 }
1091 
1092 static int tusb_musb_init(struct musb *musb)
1093 {
1094     struct platform_device  *pdev;
1095     struct resource     *mem;
1096     void __iomem        *sync = NULL;
1097     int         ret;
1098 
1099     musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
1100     if (IS_ERR_OR_NULL(musb->xceiv))
1101         return -EPROBE_DEFER;
1102 
1103     pdev = to_platform_device(musb->controller);
1104 
1105     /* dma address for async dma */
1106     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1107     if (!mem) {
1108         pr_debug("no async dma resource?\n");
1109         ret = -ENODEV;
1110         goto done;
1111     }
1112     musb->async = mem->start;
1113 
1114     /* dma address for sync dma */
1115     mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1116     if (!mem) {
1117         pr_debug("no sync dma resource?\n");
1118         ret = -ENODEV;
1119         goto done;
1120     }
1121     musb->sync = mem->start;
1122 
1123     sync = ioremap(mem->start, resource_size(mem));
1124     if (!sync) {
1125         pr_debug("ioremap for sync failed\n");
1126         ret = -ENOMEM;
1127         goto done;
1128     }
1129     musb->sync_va = sync;
1130 
1131     /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1132      * FIFOs at 0x600, TUSB at 0x800
1133      */
1134     musb->mregs += TUSB_BASE_OFFSET;
1135 
1136     ret = tusb_musb_start(musb);
1137     if (ret) {
1138         printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1139                 ret);
1140         goto done;
1141     }
1142     musb->isr = tusb_musb_interrupt;
1143 
1144     musb->xceiv->set_power = tusb_draw_power;
1145     the_musb = musb;
1146 
1147     timer_setup(&musb->dev_timer, musb_do_idle, 0);
1148 
1149 done:
1150     if (ret < 0) {
1151         if (sync)
1152             iounmap(sync);
1153 
1154         usb_put_phy(musb->xceiv);
1155     }
1156     return ret;
1157 }
1158 
1159 static int tusb_musb_exit(struct musb *musb)
1160 {
1161     del_timer_sync(&musb->dev_timer);
1162     the_musb = NULL;
1163 
1164     if (musb->board_set_power)
1165         musb->board_set_power(0);
1166 
1167     iounmap(musb->sync_va);
1168 
1169     usb_put_phy(musb->xceiv);
1170     return 0;
1171 }
1172 
1173 static const struct musb_platform_ops tusb_ops = {
1174     .quirks     = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB |
1175               MUSB_G_NO_SKB_RESERVE,
1176     .init       = tusb_musb_init,
1177     .exit       = tusb_musb_exit,
1178 
1179     .ep_offset  = tusb_ep_offset,
1180     .ep_select  = tusb_ep_select,
1181     .fifo_offset    = tusb_fifo_offset,
1182     .readb      = tusb_readb,
1183     .writeb     = tusb_writeb,
1184     .read_fifo  = tusb_read_fifo,
1185     .write_fifo = tusb_write_fifo,
1186 #ifdef CONFIG_USB_TUSB_OMAP_DMA
1187     .dma_init   = tusb_dma_controller_create,
1188     .dma_exit   = tusb_dma_controller_destroy,
1189 #endif
1190     .enable     = tusb_musb_enable,
1191     .disable    = tusb_musb_disable,
1192 
1193     .set_mode   = tusb_musb_set_mode,
1194     .try_idle   = tusb_musb_try_idle,
1195 
1196     .vbus_status    = tusb_musb_vbus_status,
1197     .set_vbus   = tusb_musb_set_vbus,
1198 };
1199 
1200 static const struct platform_device_info tusb_dev_info = {
1201     .name       = "musb-hdrc",
1202     .id     = PLATFORM_DEVID_AUTO,
1203     .dma_mask   = DMA_BIT_MASK(32),
1204 };
1205 
1206 static int tusb_probe(struct platform_device *pdev)
1207 {
1208     struct resource musb_resources[3];
1209     struct musb_hdrc_platform_data  *pdata = dev_get_platdata(&pdev->dev);
1210     struct platform_device      *musb;
1211     struct tusb6010_glue        *glue;
1212     struct platform_device_info pinfo;
1213     int             ret;
1214 
1215     glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
1216     if (!glue)
1217         return -ENOMEM;
1218 
1219     glue->dev           = &pdev->dev;
1220 
1221     pdata->platform_ops     = &tusb_ops;
1222 
1223     usb_phy_generic_register();
1224     platform_set_drvdata(pdev, glue);
1225 
1226     memset(musb_resources, 0x00, sizeof(*musb_resources) *
1227             ARRAY_SIZE(musb_resources));
1228 
1229     musb_resources[0].name = pdev->resource[0].name;
1230     musb_resources[0].start = pdev->resource[0].start;
1231     musb_resources[0].end = pdev->resource[0].end;
1232     musb_resources[0].flags = pdev->resource[0].flags;
1233 
1234     musb_resources[1].name = pdev->resource[1].name;
1235     musb_resources[1].start = pdev->resource[1].start;
1236     musb_resources[1].end = pdev->resource[1].end;
1237     musb_resources[1].flags = pdev->resource[1].flags;
1238 
1239     musb_resources[2].name = pdev->resource[2].name;
1240     musb_resources[2].start = pdev->resource[2].start;
1241     musb_resources[2].end = pdev->resource[2].end;
1242     musb_resources[2].flags = pdev->resource[2].flags;
1243 
1244     pinfo = tusb_dev_info;
1245     pinfo.parent = &pdev->dev;
1246     pinfo.res = musb_resources;
1247     pinfo.num_res = ARRAY_SIZE(musb_resources);
1248     pinfo.data = pdata;
1249     pinfo.size_data = sizeof(*pdata);
1250 
1251     glue->musb = musb = platform_device_register_full(&pinfo);
1252     if (IS_ERR(musb)) {
1253         ret = PTR_ERR(musb);
1254         dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
1255         return ret;
1256     }
1257 
1258     return 0;
1259 }
1260 
1261 static int tusb_remove(struct platform_device *pdev)
1262 {
1263     struct tusb6010_glue        *glue = platform_get_drvdata(pdev);
1264 
1265     platform_device_unregister(glue->musb);
1266     usb_phy_generic_unregister(glue->phy);
1267 
1268     return 0;
1269 }
1270 
1271 static struct platform_driver tusb_driver = {
1272     .probe      = tusb_probe,
1273     .remove     = tusb_remove,
1274     .driver     = {
1275         .name   = "musb-tusb",
1276     },
1277 };
1278 
1279 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1280 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1281 MODULE_LICENSE("GPL v2");
1282 module_platform_driver(tusb_driver);
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