usb/musb/musbhsdma.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * MUSB OTG driver - support for Mentor's DMA controller
0004  *
0005  * Copyright 2005 Mentor Graphics Corporation
0006  * Copyright (C) 2005-2007 by Texas Instruments
0007  */
0008 #include <linux/device.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/slab.h>
0012 #include "musb_core.h"
0013 #include "musb_dma.h"
0014
0015 #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)       \
0016         (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
0017
0018 #define musb_read_hsdma_addr(mbase, bchannel)   \
0019     musb_readl(mbase,   \
0020            MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
0021
0022 #define musb_write_hsdma_addr(mbase, bchannel, addr) \
0023     musb_writel(mbase, \
0024             MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
0025             addr)
0026
0027 #define musb_read_hsdma_count(mbase, bchannel)  \
0028     musb_readl(mbase,   \
0029            MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
0030
0031 #define musb_write_hsdma_count(mbase, bchannel, len) \
0032     musb_writel(mbase, \
0033             MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
0034             len)
0035 /* control register (16-bit): */
0036 #define MUSB_HSDMA_ENABLE_SHIFT     0
0037 #define MUSB_HSDMA_TRANSMIT_SHIFT   1
0038 #define MUSB_HSDMA_MODE1_SHIFT      2
0039 #define MUSB_HSDMA_IRQENABLE_SHIFT  3
0040 #define MUSB_HSDMA_ENDPOINT_SHIFT   4
0041 #define MUSB_HSDMA_BUSERROR_SHIFT   8
0042 #define MUSB_HSDMA_BURSTMODE_SHIFT  9
0043 #define MUSB_HSDMA_BURSTMODE        (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
0044 #define MUSB_HSDMA_BURSTMODE_UNSPEC 0
0045 #define MUSB_HSDMA_BURSTMODE_INCR4  1
0046 #define MUSB_HSDMA_BURSTMODE_INCR8  2
0047 #define MUSB_HSDMA_BURSTMODE_INCR16 3
0048
0049 #define MUSB_HSDMA_CHANNELS     8
0050
0051 struct musb_dma_controller;
0052
0053 struct musb_dma_channel {
0054     struct dma_channel      channel;
0055     struct musb_dma_controller  *controller;
0056     u32             start_addr;
0057     u32             len;
0058     u16             max_packet_sz;
0059     u8              idx;
0060     u8              epnum;
0061     u8              transmit;
0062 };
0063
0064 struct musb_dma_controller {
0065     struct dma_controller       controller;
0066     struct musb_dma_channel     channel[MUSB_HSDMA_CHANNELS];
0067     void                *private_data;
0068     void __iomem            *base;
0069     u8              channel_count;
0070     u8              used_channels;
0071     int             irq;
0072 };
0073
0074 static void dma_channel_release(struct dma_channel *channel);
0075
0076 static void dma_controller_stop(struct musb_dma_controller *controller)
0077 {
0078     struct musb *musb = controller->private_data;
0079     struct dma_channel *channel;
0080     u8 bit;
0081
0082     if (controller->used_channels != 0) {
0083         dev_err(musb->controller,
0084             "Stopping DMA controller while channel active\n");
0085
0086         for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
0087             if (controller->used_channels & (1 << bit)) {
0088                 channel = &controller->channel[bit].channel;
0089                 dma_channel_release(channel);
0090
0091                 if (!controller->used_channels)
0092                     break;
0093             }
0094         }
0095     }
0096 }
0097
0098 static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
0099                 struct musb_hw_ep *hw_ep, u8 transmit)
0100 {
0101     struct musb_dma_controller *controller = container_of(c,
0102             struct musb_dma_controller, controller);
0103     struct musb_dma_channel *musb_channel = NULL;
0104     struct dma_channel *channel = NULL;
0105     u8 bit;
0106
0107     for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
0108         if (!(controller->used_channels & (1 << bit))) {
0109             controller->used_channels |= (1 << bit);
0110             musb_channel = &(controller->channel[bit]);
0111             musb_channel->controller = controller;
0112             musb_channel->idx = bit;
0113             musb_channel->epnum = hw_ep->epnum;
0114             musb_channel->transmit = transmit;
0115             channel = &(musb_channel->channel);
0116             channel->private_data = musb_channel;
0117             channel->status = MUSB_DMA_STATUS_FREE;
0118             channel->max_len = 0x100000;
0119             /* Tx => mode 1; Rx => mode 0 */
0120             channel->desired_mode = transmit;
0121             channel->actual_len = 0;
0122             break;
0123         }
0124     }
0125
0126     return channel;
0127 }
0128
0129 static void dma_channel_release(struct dma_channel *channel)
0130 {
0131     struct musb_dma_channel *musb_channel = channel->private_data;
0132
0133     channel->actual_len = 0;
0134     musb_channel->start_addr = 0;
0135     musb_channel->len = 0;
0136
0137     musb_channel->controller->used_channels &=
0138         ~(1 << musb_channel->idx);
0139
0140     channel->status = MUSB_DMA_STATUS_UNKNOWN;
0141 }
0142
0143 static void configure_channel(struct dma_channel *channel,
0144                 u16 packet_sz, u8 mode,
0145                 dma_addr_t dma_addr, u32 len)
0146 {
0147     struct musb_dma_channel *musb_channel = channel->private_data;
0148     struct musb_dma_controller *controller = musb_channel->controller;
0149     struct musb *musb = controller->private_data;
0150     void __iomem *mbase = controller->base;
0151     u8 bchannel = musb_channel->idx;
0152     u16 csr = 0;
0153
0154     musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
0155             channel, packet_sz, &dma_addr, len, mode);
0156
0157     if (mode) {
0158         csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
0159         BUG_ON(len < packet_sz);
0160     }
0161     csr |= MUSB_HSDMA_BURSTMODE_INCR16
0162                 << MUSB_HSDMA_BURSTMODE_SHIFT;
0163
0164     csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
0165         | (1 << MUSB_HSDMA_ENABLE_SHIFT)
0166         | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
0167         | (musb_channel->transmit
0168                 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
0169                 : 0);
0170
0171     /* address/count */
0172     musb_write_hsdma_addr(mbase, bchannel, dma_addr);
0173     musb_write_hsdma_count(mbase, bchannel, len);
0174
0175     /* control (this should start things) */
0176     musb_writew(mbase,
0177         MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
0178         csr);
0179 }
0180
0181 static int dma_channel_program(struct dma_channel *channel,
0182                 u16 packet_sz, u8 mode,
0183                 dma_addr_t dma_addr, u32 len)
0184 {
0185     struct musb_dma_channel *musb_channel = channel->private_data;
0186     struct musb_dma_controller *controller = musb_channel->controller;
0187     struct musb *musb = controller->private_data;
0188
0189     musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
0190         musb_channel->epnum,
0191         musb_channel->transmit ? "Tx" : "Rx",
0192         packet_sz, &dma_addr, len, mode);
0193
0194     BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
0195         channel->status == MUSB_DMA_STATUS_BUSY);
0196
0197     /*
0198      * The DMA engine in RTL1.8 and above cannot handle
0199      * DMA addresses that are not aligned to a 4 byte boundary.
0200      * It ends up masking the last two bits of the address
0201      * programmed in DMA_ADDR.
0202      *
0203      * Fail such DMA transfers, so that the backup PIO mode
0204      * can carry out the transfer
0205      */
0206     if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
0207         return false;
0208
0209     channel->actual_len = 0;
0210     musb_channel->start_addr = dma_addr;
0211     musb_channel->len = len;
0212     musb_channel->max_packet_sz = packet_sz;
0213     channel->status = MUSB_DMA_STATUS_BUSY;
0214
0215     configure_channel(channel, packet_sz, mode, dma_addr, len);
0216
0217     return true;
0218 }
0219
0220 static int dma_channel_abort(struct dma_channel *channel)
0221 {
0222     struct musb_dma_channel *musb_channel = channel->private_data;
0223     void __iomem *mbase = musb_channel->controller->base;
0224     struct musb *musb = musb_channel->controller->private_data;
0225
0226     u8 bchannel = musb_channel->idx;
0227     int offset;
0228     u16 csr;
0229
0230     if (channel->status == MUSB_DMA_STATUS_BUSY) {
0231         if (musb_channel->transmit) {
0232             offset = musb->io.ep_offset(musb_channel->epnum,
0233                         MUSB_TXCSR);
0234
0235             /*
0236              * The programming guide says that we must clear
0237              * the DMAENAB bit before the DMAMODE bit...
0238              */
0239             csr = musb_readw(mbase, offset);
0240             csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
0241             musb_writew(mbase, offset, csr);
0242             csr &= ~MUSB_TXCSR_DMAMODE;
0243             musb_writew(mbase, offset, csr);
0244         } else {
0245             offset = musb->io.ep_offset(musb_channel->epnum,
0246                         MUSB_RXCSR);
0247
0248             csr = musb_readw(mbase, offset);
0249             csr &= ~(MUSB_RXCSR_AUTOCLEAR |
0250                  MUSB_RXCSR_DMAENAB |
0251                  MUSB_RXCSR_DMAMODE);
0252             musb_writew(mbase, offset, csr);
0253         }
0254
0255         musb_writew(mbase,
0256             MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
0257             0);
0258         musb_write_hsdma_addr(mbase, bchannel, 0);
0259         musb_write_hsdma_count(mbase, bchannel, 0);
0260         channel->status = MUSB_DMA_STATUS_FREE;
0261     }
0262
0263     return 0;
0264 }
0265
0266 irqreturn_t dma_controller_irq(int irq, void *private_data)
0267 {
0268     struct musb_dma_controller *controller = private_data;
0269     struct musb *musb = controller->private_data;
0270     struct musb_dma_channel *musb_channel;
0271     struct dma_channel *channel;
0272
0273     void __iomem *mbase = controller->base;
0274
0275     irqreturn_t retval = IRQ_NONE;
0276
0277     unsigned long flags;
0278
0279     u8 bchannel;
0280     u8 int_hsdma;
0281
0282     u32 addr, count;
0283     u16 csr;
0284
0285     spin_lock_irqsave(&musb->lock, flags);
0286
0287     int_hsdma = musb_clearb(mbase, MUSB_HSDMA_INTR);
0288
0289     if (!int_hsdma) {
0290         musb_dbg(musb, "spurious DMA irq");
0291
0292         for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
0293             musb_channel = (struct musb_dma_channel *)
0294                     &(controller->channel[bchannel]);
0295             channel = &musb_channel->channel;
0296             if (channel->status == MUSB_DMA_STATUS_BUSY) {
0297                 count = musb_read_hsdma_count(mbase, bchannel);
0298
0299                 if (count == 0)
0300                     int_hsdma |= (1 << bchannel);
0301             }
0302         }
0303
0304         musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);
0305
0306         if (!int_hsdma)
0307             goto done;
0308     }
0309
0310     for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
0311         if (int_hsdma & (1 << bchannel)) {
0312             musb_channel = (struct musb_dma_channel *)
0313                     &(controller->channel[bchannel]);
0314             channel = &musb_channel->channel;
0315
0316             csr = musb_readw(mbase,
0317                     MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
0318                             MUSB_HSDMA_CONTROL));
0319
0320             if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
0321                 musb_channel->channel.status =
0322                     MUSB_DMA_STATUS_BUS_ABORT;
0323             } else {
0324                 addr = musb_read_hsdma_addr(mbase,
0325                         bchannel);
0326                 channel->actual_len = addr
0327                     - musb_channel->start_addr;
0328
0329                 musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
0330                     channel, musb_channel->start_addr,
0331                     addr, channel->actual_len,
0332                     musb_channel->len,
0333                     (channel->actual_len
0334                         < musb_channel->len) ?
0335                     "=> reconfig 0" : "=> complete");
0336
0337                 channel->status = MUSB_DMA_STATUS_FREE;
0338
0339                 /* completed */
0340                 if (musb_channel->transmit &&
0341                     (!channel->desired_mode ||
0342                     (channel->actual_len %
0343                         musb_channel->max_packet_sz))) {
0344                     u8  epnum  = musb_channel->epnum;
0345                     int offset = musb->io.ep_offset(epnum,
0346                                     MUSB_TXCSR);
0347                     u16 txcsr;
0348
0349                     /*
0350                      * The programming guide says that we
0351                      * must clear DMAENAB before DMAMODE.
0352                      */
0353                     musb_ep_select(mbase, epnum);
0354                     txcsr = musb_readw(mbase, offset);
0355                     if (channel->desired_mode == 1) {
0356                         txcsr &= ~(MUSB_TXCSR_DMAENAB
0357                             | MUSB_TXCSR_AUTOSET);
0358                         musb_writew(mbase, offset, txcsr);
0359                         /* Send out the packet */
0360                         txcsr &= ~MUSB_TXCSR_DMAMODE;
0361                         txcsr |= MUSB_TXCSR_DMAENAB;
0362                     }
0363                     txcsr |=  MUSB_TXCSR_TXPKTRDY;
0364                     musb_writew(mbase, offset, txcsr);
0365                 }
0366                 musb_dma_completion(musb, musb_channel->epnum,
0367                             musb_channel->transmit);
0368             }
0369         }
0370     }
0371
0372     retval = IRQ_HANDLED;
0373 done:
0374     spin_unlock_irqrestore(&musb->lock, flags);
0375     return retval;
0376 }
0377 EXPORT_SYMBOL_GPL(dma_controller_irq);
0378
0379 void musbhs_dma_controller_destroy(struct dma_controller *c)
0380 {
0381     struct musb_dma_controller *controller = container_of(c,
0382             struct musb_dma_controller, controller);
0383
0384     dma_controller_stop(controller);
0385
0386     if (controller->irq)
0387         free_irq(controller->irq, c);
0388
0389     kfree(controller);
0390 }
0391 EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);
0392
0393 static struct musb_dma_controller *
0394 dma_controller_alloc(struct musb *musb, void __iomem *base)
0395 {
0396     struct musb_dma_controller *controller;
0397
0398     controller = kzalloc(sizeof(*controller), GFP_KERNEL);
0399     if (!controller)
0400         return NULL;
0401
0402     controller->channel_count = MUSB_HSDMA_CHANNELS;
0403     controller->private_data = musb;
0404     controller->base = base;
0405
0406     controller->controller.channel_alloc = dma_channel_allocate;
0407     controller->controller.channel_release = dma_channel_release;
0408     controller->controller.channel_program = dma_channel_program;
0409     controller->controller.channel_abort = dma_channel_abort;
0410     return controller;
0411 }
0412
0413 struct dma_controller *
0414 musbhs_dma_controller_create(struct musb *musb, void __iomem *base)
0415 {
0416     struct musb_dma_controller *controller;
0417     struct device *dev = musb->controller;
0418     struct platform_device *pdev = to_platform_device(dev);
0419     int irq = platform_get_irq_byname(pdev, "dma");
0420
0421     if (irq <= 0) {
0422         dev_err(dev, "No DMA interrupt line!\n");
0423         return NULL;
0424     }
0425
0426     controller = dma_controller_alloc(musb, base);
0427     if (!controller)
0428         return NULL;
0429
0430     if (request_irq(irq, dma_controller_irq, 0,
0431             dev_name(musb->controller), controller)) {
0432         dev_err(dev, "request_irq %d failed!\n", irq);
0433         musb_dma_controller_destroy(&controller->controller);
0434
0435         return NULL;
0436     }
0437
0438     controller->irq = irq;
0439
0440     return &controller->controller;
0441 }
0442 EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);
0443
0444 struct dma_controller *
0445 musbhs_dma_controller_create_noirq(struct musb *musb, void __iomem *base)
0446 {
0447     struct musb_dma_controller *controller;
0448
0449     controller = dma_controller_alloc(musb, base);
0450     if (!controller)
0451         return NULL;
0452
0453     return &controller->controller;
0454 }
0455 EXPORT_SYMBOL_GPL(musbhs_dma_controller_create_noirq);