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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * MUSB OTG driver register defines
0004  *
0005  * Copyright 2005 Mentor Graphics Corporation
0006  * Copyright (C) 2005-2006 by Texas Instruments
0007  * Copyright (C) 2006-2007 Nokia Corporation
0008  */
0009 
0010 #ifndef __MUSB_REGS_H__
0011 #define __MUSB_REGS_H__
0012 
0013 #define MUSB_EP0_FIFOSIZE   64  /* This is non-configurable */
0014 
0015 /*
0016  * MUSB Register bits
0017  */
0018 
0019 /* POWER */
0020 #define MUSB_POWER_ISOUPDATE    0x80
0021 #define MUSB_POWER_SOFTCONN 0x40
0022 #define MUSB_POWER_HSENAB   0x20
0023 #define MUSB_POWER_HSMODE   0x10
0024 #define MUSB_POWER_RESET    0x08
0025 #define MUSB_POWER_RESUME   0x04
0026 #define MUSB_POWER_SUSPENDM 0x02
0027 #define MUSB_POWER_ENSUSPEND    0x01
0028 
0029 /* INTRUSB */
0030 #define MUSB_INTR_SUSPEND   0x01
0031 #define MUSB_INTR_RESUME    0x02
0032 #define MUSB_INTR_RESET     0x04
0033 #define MUSB_INTR_BABBLE    0x04
0034 #define MUSB_INTR_SOF       0x08
0035 #define MUSB_INTR_CONNECT   0x10
0036 #define MUSB_INTR_DISCONNECT    0x20
0037 #define MUSB_INTR_SESSREQ   0x40
0038 #define MUSB_INTR_VBUSERROR 0x80    /* For SESSION end */
0039 
0040 /* DEVCTL */
0041 #define MUSB_DEVCTL_BDEVICE 0x80
0042 #define MUSB_DEVCTL_FSDEV   0x40
0043 #define MUSB_DEVCTL_LSDEV   0x20
0044 #define MUSB_DEVCTL_VBUS    0x18
0045 #define MUSB_DEVCTL_VBUS_SHIFT  3
0046 #define MUSB_DEVCTL_HM      0x04
0047 #define MUSB_DEVCTL_HR      0x02
0048 #define MUSB_DEVCTL_SESSION 0x01
0049 
0050 /* BABBLE_CTL */
0051 #define MUSB_BABBLE_FORCE_TXIDLE    0x80
0052 #define MUSB_BABBLE_SW_SESSION_CTRL 0x40
0053 #define MUSB_BABBLE_STUCK_J     0x20
0054 #define MUSB_BABBLE_RCV_DISABLE     0x04
0055 
0056 /* MUSB ULPI VBUSCONTROL */
0057 #define MUSB_ULPI_USE_EXTVBUS   0x01
0058 #define MUSB_ULPI_USE_EXTVBUSIND 0x02
0059 /* ULPI_REG_CONTROL */
0060 #define MUSB_ULPI_REG_REQ   (1 << 0)
0061 #define MUSB_ULPI_REG_CMPLT (1 << 1)
0062 #define MUSB_ULPI_RDN_WR    (1 << 2)
0063 
0064 /* TESTMODE */
0065 #define MUSB_TEST_FORCE_HOST    0x80
0066 #define MUSB_TEST_FIFO_ACCESS   0x40
0067 #define MUSB_TEST_FORCE_FS  0x20
0068 #define MUSB_TEST_FORCE_HS  0x10
0069 #define MUSB_TEST_PACKET    0x08
0070 #define MUSB_TEST_K     0x04
0071 #define MUSB_TEST_J     0x02
0072 #define MUSB_TEST_SE0_NAK   0x01
0073 
0074 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
0075 #define MUSB_FIFOSZ_DPB 0x10
0076 /* Allocation size (8, 16, 32, ... 4096) */
0077 #define MUSB_FIFOSZ_SIZE    0x0f
0078 
0079 /* CSR0 */
0080 #define MUSB_CSR0_FLUSHFIFO 0x0100
0081 #define MUSB_CSR0_TXPKTRDY  0x0002
0082 #define MUSB_CSR0_RXPKTRDY  0x0001
0083 
0084 /* CSR0 in Peripheral mode */
0085 #define MUSB_CSR0_P_SVDSETUPEND 0x0080
0086 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
0087 #define MUSB_CSR0_P_SENDSTALL   0x0020
0088 #define MUSB_CSR0_P_SETUPEND    0x0010
0089 #define MUSB_CSR0_P_DATAEND 0x0008
0090 #define MUSB_CSR0_P_SENTSTALL   0x0004
0091 
0092 /* CSR0 in Host mode */
0093 #define MUSB_CSR0_H_DIS_PING        0x0800
0094 #define MUSB_CSR0_H_WR_DATATOGGLE   0x0400  /* Set to allow setting: */
0095 #define MUSB_CSR0_H_DATATOGGLE      0x0200  /* Data toggle control */
0096 #define MUSB_CSR0_H_NAKTIMEOUT      0x0080
0097 #define MUSB_CSR0_H_STATUSPKT       0x0040
0098 #define MUSB_CSR0_H_REQPKT      0x0020
0099 #define MUSB_CSR0_H_ERROR       0x0010
0100 #define MUSB_CSR0_H_SETUPPKT        0x0008
0101 #define MUSB_CSR0_H_RXSTALL     0x0004
0102 
0103 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
0104 #define MUSB_CSR0_P_WZC_BITS    \
0105     (MUSB_CSR0_P_SENTSTALL)
0106 #define MUSB_CSR0_H_WZC_BITS    \
0107     (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
0108     | MUSB_CSR0_RXPKTRDY)
0109 
0110 /* TxType/RxType */
0111 #define MUSB_TYPE_SPEED     0xc0
0112 #define MUSB_TYPE_SPEED_SHIFT   6
0113 #define MUSB_TYPE_PROTO     0x30    /* Implicitly zero for ep0 */
0114 #define MUSB_TYPE_PROTO_SHIFT   4
0115 #define MUSB_TYPE_REMOTE_END    0xf /* Implicitly zero for ep0 */
0116 
0117 /* CONFIGDATA */
0118 #define MUSB_CONFIGDATA_MPRXE       0x80    /* Auto bulk pkt combining */
0119 #define MUSB_CONFIGDATA_MPTXE       0x40    /* Auto bulk pkt splitting */
0120 #define MUSB_CONFIGDATA_BIGENDIAN   0x20
0121 #define MUSB_CONFIGDATA_HBRXE       0x10    /* HB-ISO for RX */
0122 #define MUSB_CONFIGDATA_HBTXE       0x08    /* HB-ISO for TX */
0123 #define MUSB_CONFIGDATA_DYNFIFO     0x04    /* Dynamic FIFO sizing */
0124 #define MUSB_CONFIGDATA_SOFTCONE    0x02    /* SoftConnect */
0125 #define MUSB_CONFIGDATA_UTMIDW      0x01    /* Data width 0/1 => 8/16bits */
0126 
0127 /* TXCSR in Peripheral and Host mode */
0128 #define MUSB_TXCSR_AUTOSET      0x8000
0129 #define MUSB_TXCSR_DMAENAB      0x1000
0130 #define MUSB_TXCSR_FRCDATATOG       0x0800
0131 #define MUSB_TXCSR_DMAMODE      0x0400
0132 #define MUSB_TXCSR_CLRDATATOG       0x0040
0133 #define MUSB_TXCSR_FLUSHFIFO        0x0008
0134 #define MUSB_TXCSR_FIFONOTEMPTY     0x0002
0135 #define MUSB_TXCSR_TXPKTRDY     0x0001
0136 
0137 /* TXCSR in Peripheral mode */
0138 #define MUSB_TXCSR_P_ISO        0x4000
0139 #define MUSB_TXCSR_P_INCOMPTX       0x0080
0140 #define MUSB_TXCSR_P_SENTSTALL      0x0020
0141 #define MUSB_TXCSR_P_SENDSTALL      0x0010
0142 #define MUSB_TXCSR_P_UNDERRUN       0x0004
0143 
0144 /* TXCSR in Host mode */
0145 #define MUSB_TXCSR_H_WR_DATATOGGLE  0x0200
0146 #define MUSB_TXCSR_H_DATATOGGLE     0x0100
0147 #define MUSB_TXCSR_H_NAKTIMEOUT     0x0080
0148 #define MUSB_TXCSR_H_RXSTALL        0x0020
0149 #define MUSB_TXCSR_H_ERROR      0x0004
0150 
0151 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
0152 #define MUSB_TXCSR_P_WZC_BITS   \
0153     (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
0154     | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
0155 #define MUSB_TXCSR_H_WZC_BITS   \
0156     (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
0157     | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
0158 
0159 /* RXCSR in Peripheral and Host mode */
0160 #define MUSB_RXCSR_AUTOCLEAR        0x8000
0161 #define MUSB_RXCSR_DMAENAB      0x2000
0162 #define MUSB_RXCSR_DISNYET      0x1000
0163 #define MUSB_RXCSR_PID_ERR      0x1000
0164 #define MUSB_RXCSR_DMAMODE      0x0800
0165 #define MUSB_RXCSR_INCOMPRX     0x0100
0166 #define MUSB_RXCSR_CLRDATATOG       0x0080
0167 #define MUSB_RXCSR_FLUSHFIFO        0x0010
0168 #define MUSB_RXCSR_DATAERROR        0x0008
0169 #define MUSB_RXCSR_FIFOFULL     0x0002
0170 #define MUSB_RXCSR_RXPKTRDY     0x0001
0171 
0172 /* RXCSR in Peripheral mode */
0173 #define MUSB_RXCSR_P_ISO        0x4000
0174 #define MUSB_RXCSR_P_SENTSTALL      0x0040
0175 #define MUSB_RXCSR_P_SENDSTALL      0x0020
0176 #define MUSB_RXCSR_P_OVERRUN        0x0004
0177 
0178 /* RXCSR in Host mode */
0179 #define MUSB_RXCSR_H_AUTOREQ        0x4000
0180 #define MUSB_RXCSR_H_WR_DATATOGGLE  0x0400
0181 #define MUSB_RXCSR_H_DATATOGGLE     0x0200
0182 #define MUSB_RXCSR_H_RXSTALL        0x0040
0183 #define MUSB_RXCSR_H_REQPKT     0x0020
0184 #define MUSB_RXCSR_H_ERROR      0x0004
0185 
0186 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
0187 #define MUSB_RXCSR_P_WZC_BITS   \
0188     (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
0189     | MUSB_RXCSR_RXPKTRDY)
0190 #define MUSB_RXCSR_H_WZC_BITS   \
0191     (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
0192     | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
0193 
0194 /* HUBADDR */
0195 #define MUSB_HUBADDR_MULTI_TT       0x80
0196 
0197 
0198 /*
0199  * Common USB registers
0200  */
0201 
0202 #define MUSB_FADDR      0x00    /* 8-bit */
0203 #define MUSB_POWER      0x01    /* 8-bit */
0204 
0205 #define MUSB_INTRTX     0x02    /* 16-bit */
0206 #define MUSB_INTRRX     0x04
0207 #define MUSB_INTRTXE        0x06
0208 #define MUSB_INTRRXE        0x08
0209 #define MUSB_INTRUSB        0x0A    /* 8 bit */
0210 #define MUSB_INTRUSBE       0x0B    /* 8 bit */
0211 #define MUSB_FRAME      0x0C
0212 #define MUSB_INDEX      0x0E    /* 8 bit */
0213 #define MUSB_TESTMODE       0x0F    /* 8 bit */
0214 
0215 /*
0216  * Additional Control Registers
0217  */
0218 
0219 #define MUSB_DEVCTL     0x60    /* 8 bit */
0220 #define MUSB_BABBLE_CTL     0x61    /* 8 bit */
0221 
0222 /* These are always controlled through the INDEX register */
0223 #define MUSB_TXFIFOSZ       0x62    /* 8-bit (see masks) */
0224 #define MUSB_RXFIFOSZ       0x63    /* 8-bit (see masks) */
0225 #define MUSB_TXFIFOADD      0x64    /* 16-bit offset shifted right 3 */
0226 #define MUSB_RXFIFOADD      0x66    /* 16-bit offset shifted right 3 */
0227 
0228 /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
0229 #define MUSB_HWVERS     0x6C    /* 8 bit */
0230 #define MUSB_ULPI_BUSCONTROL    0x70    /* 8 bit */
0231 #define MUSB_ULPI_INT_MASK  0x72    /* 8 bit */
0232 #define MUSB_ULPI_INT_SRC   0x73    /* 8 bit */
0233 #define MUSB_ULPI_REG_DATA  0x74    /* 8 bit */
0234 #define MUSB_ULPI_REG_ADDR  0x75    /* 8 bit */
0235 #define MUSB_ULPI_REG_CONTROL   0x76    /* 8 bit */
0236 #define MUSB_ULPI_RAW_DATA  0x77    /* 8 bit */
0237 
0238 #define MUSB_EPINFO     0x78    /* 8 bit */
0239 #define MUSB_RAMINFO        0x79    /* 8 bit */
0240 #define MUSB_LINKINFO       0x7a    /* 8 bit */
0241 #define MUSB_VPLEN      0x7b    /* 8 bit */
0242 #define MUSB_HS_EOF1        0x7c    /* 8 bit */
0243 #define MUSB_FS_EOF1        0x7d    /* 8 bit */
0244 #define MUSB_LS_EOF1        0x7e    /* 8 bit */
0245 
0246 /* Offsets to endpoint registers */
0247 #define MUSB_TXMAXP     0x00
0248 #define MUSB_TXCSR      0x02
0249 #define MUSB_CSR0       MUSB_TXCSR  /* Re-used for EP0 */
0250 #define MUSB_RXMAXP     0x04
0251 #define MUSB_RXCSR      0x06
0252 #define MUSB_RXCOUNT        0x08
0253 #define MUSB_COUNT0     MUSB_RXCOUNT    /* Re-used for EP0 */
0254 #define MUSB_TXTYPE     0x0A
0255 #define MUSB_TYPE0      MUSB_TXTYPE /* Re-used for EP0 */
0256 #define MUSB_TXINTERVAL     0x0B
0257 #define MUSB_NAKLIMIT0      MUSB_TXINTERVAL /* Re-used for EP0 */
0258 #define MUSB_RXTYPE     0x0C
0259 #define MUSB_RXINTERVAL     0x0D
0260 #define MUSB_FIFOSIZE       0x0F
0261 #define MUSB_CONFIGDATA     MUSB_FIFOSIZE   /* Re-used for EP0 */
0262 
0263 #include "tusb6010.h"       /* Needed "only" for TUSB_EP0_CONF */
0264 
0265 #define MUSB_TXCSR_MODE         0x2000
0266 
0267 /* "bus control"/target registers, for host side multipoint (external hubs) */
0268 #define MUSB_TXFUNCADDR     0x00
0269 #define MUSB_TXHUBADDR      0x02
0270 #define MUSB_TXHUBPORT      0x03
0271 
0272 #define MUSB_RXFUNCADDR     0x04
0273 #define MUSB_RXHUBADDR      0x06
0274 #define MUSB_RXHUBPORT      0x07
0275 
0276 static inline u8 musb_read_configdata(void __iomem *mbase)
0277 {
0278     musb_writeb(mbase, MUSB_INDEX, 0);
0279     return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
0280 }
0281 
0282 static inline void musb_write_rxfunaddr(struct musb *musb, u8 epnum,
0283         u8 qh_addr_reg)
0284 {
0285     musb_writeb(musb->mregs,
0286             musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR),
0287             qh_addr_reg);
0288 }
0289 
0290 static inline void musb_write_rxhubaddr(struct musb *musb, u8 epnum,
0291         u8 qh_h_addr_reg)
0292 {
0293     musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBADDR),
0294             qh_h_addr_reg);
0295 }
0296 
0297 static inline void musb_write_rxhubport(struct musb *musb, u8 epnum,
0298         u8 qh_h_port_reg)
0299 {
0300     musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBPORT),
0301             qh_h_port_reg);
0302 }
0303 
0304 static inline void musb_write_txfunaddr(struct musb *musb, u8 epnum,
0305         u8 qh_addr_reg)
0306 {
0307     musb_writeb(musb->mregs,
0308             musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR),
0309             qh_addr_reg);
0310 }
0311 
0312 static inline void musb_write_txhubaddr(struct musb *musb, u8 epnum,
0313         u8 qh_addr_reg)
0314 {
0315     musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBADDR),
0316             qh_addr_reg);
0317 }
0318 
0319 static inline void musb_write_txhubport(struct musb *musb, u8 epnum,
0320         u8 qh_h_port_reg)
0321 {
0322     musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBPORT),
0323             qh_h_port_reg);
0324 }
0325 
0326 static inline u8 musb_read_rxfunaddr(struct musb *musb, u8 epnum)
0327 {
0328     return musb_readb(musb->mregs,
0329               musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR));
0330 }
0331 
0332 static inline u8 musb_read_rxhubaddr(struct musb *musb, u8 epnum)
0333 {
0334     return musb_readb(musb->mregs,
0335               musb->io.busctl_offset(epnum, MUSB_RXHUBADDR));
0336 }
0337 
0338 static inline u8 musb_read_rxhubport(struct musb *musb, u8 epnum)
0339 {
0340     return musb_readb(musb->mregs,
0341               musb->io.busctl_offset(epnum, MUSB_RXHUBPORT));
0342 }
0343 
0344 static inline u8 musb_read_txfunaddr(struct musb *musb, u8 epnum)
0345 {
0346     return musb_readb(musb->mregs,
0347               musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR));
0348 }
0349 
0350 static inline u8 musb_read_txhubaddr(struct musb *musb, u8 epnum)
0351 {
0352     return musb_readb(musb->mregs,
0353               musb->io.busctl_offset(epnum, MUSB_TXHUBADDR));
0354 }
0355 
0356 static inline u8 musb_read_txhubport(struct musb *musb, u8 epnum)
0357 {
0358     return musb_readb(musb->mregs,
0359               musb->io.busctl_offset(epnum, MUSB_TXHUBPORT));
0360 }
0361 
0362 #endif  /* __MUSB_REGS_H__ */
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