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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * MUSB OTG driver peripheral support
0004  *
0005  * Copyright 2005 Mentor Graphics Corporation
0006  * Copyright (C) 2005-2006 by Texas Instruments
0007  * Copyright (C) 2006-2007 Nokia Corporation
0008  * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
0009  */
0010 
0011 #include <linux/kernel.h>
0012 #include <linux/list.h>
0013 #include <linux/timer.h>
0014 #include <linux/module.h>
0015 #include <linux/smp.h>
0016 #include <linux/spinlock.h>
0017 #include <linux/delay.h>
0018 #include <linux/dma-mapping.h>
0019 #include <linux/slab.h>
0020 
0021 #include "musb_core.h"
0022 #include "musb_trace.h"
0023 
0024 
0025 /* ----------------------------------------------------------------------- */
0026 
0027 #define is_buffer_mapped(req) (is_dma_capable() && \
0028                     (req->map_state != UN_MAPPED))
0029 
0030 /* Maps the buffer to dma  */
0031 
0032 static inline void map_dma_buffer(struct musb_request *request,
0033             struct musb *musb, struct musb_ep *musb_ep)
0034 {
0035     int compatible = true;
0036     struct dma_controller *dma = musb->dma_controller;
0037 
0038     request->map_state = UN_MAPPED;
0039 
0040     if (!is_dma_capable() || !musb_ep->dma)
0041         return;
0042 
0043     /* Check if DMA engine can handle this request.
0044      * DMA code must reject the USB request explicitly.
0045      * Default behaviour is to map the request.
0046      */
0047     if (dma->is_compatible)
0048         compatible = dma->is_compatible(musb_ep->dma,
0049                 musb_ep->packet_sz, request->request.buf,
0050                 request->request.length);
0051     if (!compatible)
0052         return;
0053 
0054     if (request->request.dma == DMA_ADDR_INVALID) {
0055         dma_addr_t dma_addr;
0056         int ret;
0057 
0058         dma_addr = dma_map_single(
0059                 musb->controller,
0060                 request->request.buf,
0061                 request->request.length,
0062                 request->tx
0063                     ? DMA_TO_DEVICE
0064                     : DMA_FROM_DEVICE);
0065         ret = dma_mapping_error(musb->controller, dma_addr);
0066         if (ret)
0067             return;
0068 
0069         request->request.dma = dma_addr;
0070         request->map_state = MUSB_MAPPED;
0071     } else {
0072         dma_sync_single_for_device(musb->controller,
0073             request->request.dma,
0074             request->request.length,
0075             request->tx
0076                 ? DMA_TO_DEVICE
0077                 : DMA_FROM_DEVICE);
0078         request->map_state = PRE_MAPPED;
0079     }
0080 }
0081 
0082 /* Unmap the buffer from dma and maps it back to cpu */
0083 static inline void unmap_dma_buffer(struct musb_request *request,
0084                 struct musb *musb)
0085 {
0086     struct musb_ep *musb_ep = request->ep;
0087 
0088     if (!is_buffer_mapped(request) || !musb_ep->dma)
0089         return;
0090 
0091     if (request->request.dma == DMA_ADDR_INVALID) {
0092         dev_vdbg(musb->controller,
0093                 "not unmapping a never mapped buffer\n");
0094         return;
0095     }
0096     if (request->map_state == MUSB_MAPPED) {
0097         dma_unmap_single(musb->controller,
0098             request->request.dma,
0099             request->request.length,
0100             request->tx
0101                 ? DMA_TO_DEVICE
0102                 : DMA_FROM_DEVICE);
0103         request->request.dma = DMA_ADDR_INVALID;
0104     } else { /* PRE_MAPPED */
0105         dma_sync_single_for_cpu(musb->controller,
0106             request->request.dma,
0107             request->request.length,
0108             request->tx
0109                 ? DMA_TO_DEVICE
0110                 : DMA_FROM_DEVICE);
0111     }
0112     request->map_state = UN_MAPPED;
0113 }
0114 
0115 /*
0116  * Immediately complete a request.
0117  *
0118  * @param request the request to complete
0119  * @param status the status to complete the request with
0120  * Context: controller locked, IRQs blocked.
0121  */
0122 void musb_g_giveback(
0123     struct musb_ep      *ep,
0124     struct usb_request  *request,
0125     int         status)
0126 __releases(ep->musb->lock)
0127 __acquires(ep->musb->lock)
0128 {
0129     struct musb_request *req;
0130     struct musb     *musb;
0131     int         busy = ep->busy;
0132 
0133     req = to_musb_request(request);
0134 
0135     list_del(&req->list);
0136     if (req->request.status == -EINPROGRESS)
0137         req->request.status = status;
0138     musb = req->musb;
0139 
0140     ep->busy = 1;
0141     spin_unlock(&musb->lock);
0142 
0143     if (!dma_mapping_error(&musb->g.dev, request->dma))
0144         unmap_dma_buffer(req, musb);
0145 
0146     trace_musb_req_gb(req);
0147     usb_gadget_giveback_request(&req->ep->end_point, &req->request);
0148     spin_lock(&musb->lock);
0149     ep->busy = busy;
0150 }
0151 
0152 /* ----------------------------------------------------------------------- */
0153 
0154 /*
0155  * Abort requests queued to an endpoint using the status. Synchronous.
0156  * caller locked controller and blocked irqs, and selected this ep.
0157  */
0158 static void nuke(struct musb_ep *ep, const int status)
0159 {
0160     struct musb     *musb = ep->musb;
0161     struct musb_request *req = NULL;
0162     void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
0163 
0164     ep->busy = 1;
0165 
0166     if (is_dma_capable() && ep->dma) {
0167         struct dma_controller   *c = ep->musb->dma_controller;
0168         int value;
0169 
0170         if (ep->is_in) {
0171             /*
0172              * The programming guide says that we must not clear
0173              * the DMAMODE bit before DMAENAB, so we only
0174              * clear it in the second write...
0175              */
0176             musb_writew(epio, MUSB_TXCSR,
0177                     MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
0178             musb_writew(epio, MUSB_TXCSR,
0179                     0 | MUSB_TXCSR_FLUSHFIFO);
0180         } else {
0181             musb_writew(epio, MUSB_RXCSR,
0182                     0 | MUSB_RXCSR_FLUSHFIFO);
0183             musb_writew(epio, MUSB_RXCSR,
0184                     0 | MUSB_RXCSR_FLUSHFIFO);
0185         }
0186 
0187         value = c->channel_abort(ep->dma);
0188         musb_dbg(musb, "%s: abort DMA --> %d", ep->name, value);
0189         c->channel_release(ep->dma);
0190         ep->dma = NULL;
0191     }
0192 
0193     while (!list_empty(&ep->req_list)) {
0194         req = list_first_entry(&ep->req_list, struct musb_request, list);
0195         musb_g_giveback(ep, &req->request, status);
0196     }
0197 }
0198 
0199 /* ----------------------------------------------------------------------- */
0200 
0201 /* Data transfers - pure PIO, pure DMA, or mixed mode */
0202 
0203 /*
0204  * This assumes the separate CPPI engine is responding to DMA requests
0205  * from the usb core ... sequenced a bit differently from mentor dma.
0206  */
0207 
0208 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
0209 {
0210     if (can_bulk_split(musb, ep->type))
0211         return ep->hw_ep->max_packet_sz_tx;
0212     else
0213         return ep->packet_sz;
0214 }
0215 
0216 /*
0217  * An endpoint is transmitting data. This can be called either from
0218  * the IRQ routine or from ep.queue() to kickstart a request on an
0219  * endpoint.
0220  *
0221  * Context: controller locked, IRQs blocked, endpoint selected
0222  */
0223 static void txstate(struct musb *musb, struct musb_request *req)
0224 {
0225     u8          epnum = req->epnum;
0226     struct musb_ep      *musb_ep;
0227     void __iomem        *epio = musb->endpoints[epnum].regs;
0228     struct usb_request  *request;
0229     u16         fifo_count = 0, csr;
0230     int         use_dma = 0;
0231 
0232     musb_ep = req->ep;
0233 
0234     /* Check if EP is disabled */
0235     if (!musb_ep->desc) {
0236         musb_dbg(musb, "ep:%s disabled - ignore request",
0237                         musb_ep->end_point.name);
0238         return;
0239     }
0240 
0241     /* we shouldn't get here while DMA is active ... but we do ... */
0242     if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
0243         musb_dbg(musb, "dma pending...");
0244         return;
0245     }
0246 
0247     /* read TXCSR before */
0248     csr = musb_readw(epio, MUSB_TXCSR);
0249 
0250     request = &req->request;
0251     fifo_count = min(max_ep_writesize(musb, musb_ep),
0252             (int)(request->length - request->actual));
0253 
0254     if (csr & MUSB_TXCSR_TXPKTRDY) {
0255         musb_dbg(musb, "%s old packet still ready , txcsr %03x",
0256                 musb_ep->end_point.name, csr);
0257         return;
0258     }
0259 
0260     if (csr & MUSB_TXCSR_P_SENDSTALL) {
0261         musb_dbg(musb, "%s stalling, txcsr %03x",
0262                 musb_ep->end_point.name, csr);
0263         return;
0264     }
0265 
0266     musb_dbg(musb, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x",
0267             epnum, musb_ep->packet_sz, fifo_count,
0268             csr);
0269 
0270 #ifndef CONFIG_MUSB_PIO_ONLY
0271     if (is_buffer_mapped(req)) {
0272         struct dma_controller   *c = musb->dma_controller;
0273         size_t request_size;
0274 
0275         /* setup DMA, then program endpoint CSR */
0276         request_size = min_t(size_t, request->length - request->actual,
0277                     musb_ep->dma->max_len);
0278 
0279         use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
0280 
0281         /* MUSB_TXCSR_P_ISO is still set correctly */
0282 
0283         if (musb_dma_inventra(musb) || musb_dma_ux500(musb)) {
0284             if (request_size < musb_ep->packet_sz)
0285                 musb_ep->dma->desired_mode = 0;
0286             else
0287                 musb_ep->dma->desired_mode = 1;
0288 
0289             use_dma = use_dma && c->channel_program(
0290                     musb_ep->dma, musb_ep->packet_sz,
0291                     musb_ep->dma->desired_mode,
0292                     request->dma + request->actual, request_size);
0293             if (use_dma) {
0294                 if (musb_ep->dma->desired_mode == 0) {
0295                     /*
0296                      * We must not clear the DMAMODE bit
0297                      * before the DMAENAB bit -- and the
0298                      * latter doesn't always get cleared
0299                      * before we get here...
0300                      */
0301                     csr &= ~(MUSB_TXCSR_AUTOSET
0302                         | MUSB_TXCSR_DMAENAB);
0303                     musb_writew(epio, MUSB_TXCSR, csr
0304                         | MUSB_TXCSR_P_WZC_BITS);
0305                     csr &= ~MUSB_TXCSR_DMAMODE;
0306                     csr |= (MUSB_TXCSR_DMAENAB |
0307                             MUSB_TXCSR_MODE);
0308                     /* against programming guide */
0309                 } else {
0310                     csr |= (MUSB_TXCSR_DMAENAB
0311                             | MUSB_TXCSR_DMAMODE
0312                             | MUSB_TXCSR_MODE);
0313                     /*
0314                      * Enable Autoset according to table
0315                      * below
0316                      * bulk_split hb_mult   Autoset_Enable
0317                      *  0   0   Yes(Normal)
0318                      *  0   >0  No(High BW ISO)
0319                      *  1   0   Yes(HS bulk)
0320                      *  1   >0  Yes(FS bulk)
0321                      */
0322                     if (!musb_ep->hb_mult ||
0323                         can_bulk_split(musb,
0324                                musb_ep->type))
0325                         csr |= MUSB_TXCSR_AUTOSET;
0326                 }
0327                 csr &= ~MUSB_TXCSR_P_UNDERRUN;
0328 
0329                 musb_writew(epio, MUSB_TXCSR, csr);
0330             }
0331         }
0332 
0333         if (is_cppi_enabled(musb)) {
0334             /* program endpoint CSR first, then setup DMA */
0335             csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
0336             csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
0337                 MUSB_TXCSR_MODE;
0338             musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS &
0339                         ~MUSB_TXCSR_P_UNDERRUN) | csr);
0340 
0341             /* ensure writebuffer is empty */
0342             csr = musb_readw(epio, MUSB_TXCSR);
0343 
0344             /*
0345              * NOTE host side sets DMAENAB later than this; both are
0346              * OK since the transfer dma glue (between CPPI and
0347              * Mentor fifos) just tells CPPI it could start. Data
0348              * only moves to the USB TX fifo when both fifos are
0349              * ready.
0350              */
0351             /*
0352              * "mode" is irrelevant here; handle terminating ZLPs
0353              * like PIO does, since the hardware RNDIS mode seems
0354              * unreliable except for the
0355              * last-packet-is-already-short case.
0356              */
0357             use_dma = use_dma && c->channel_program(
0358                     musb_ep->dma, musb_ep->packet_sz,
0359                     0,
0360                     request->dma + request->actual,
0361                     request_size);
0362             if (!use_dma) {
0363                 c->channel_release(musb_ep->dma);
0364                 musb_ep->dma = NULL;
0365                 csr &= ~MUSB_TXCSR_DMAENAB;
0366                 musb_writew(epio, MUSB_TXCSR, csr);
0367                 /* invariant: prequest->buf is non-null */
0368             }
0369         } else if (tusb_dma_omap(musb))
0370             use_dma = use_dma && c->channel_program(
0371                     musb_ep->dma, musb_ep->packet_sz,
0372                     request->zero,
0373                     request->dma + request->actual,
0374                     request_size);
0375     }
0376 #endif
0377 
0378     if (!use_dma) {
0379         /*
0380          * Unmap the dma buffer back to cpu if dma channel
0381          * programming fails
0382          */
0383         unmap_dma_buffer(req, musb);
0384 
0385         musb_write_fifo(musb_ep->hw_ep, fifo_count,
0386                 (u8 *) (request->buf + request->actual));
0387         request->actual += fifo_count;
0388         csr |= MUSB_TXCSR_TXPKTRDY;
0389         csr &= ~MUSB_TXCSR_P_UNDERRUN;
0390         musb_writew(epio, MUSB_TXCSR, csr);
0391     }
0392 
0393     /* host may already have the data when this message shows... */
0394     musb_dbg(musb, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d",
0395             musb_ep->end_point.name, use_dma ? "dma" : "pio",
0396             request->actual, request->length,
0397             musb_readw(epio, MUSB_TXCSR),
0398             fifo_count,
0399             musb_readw(epio, MUSB_TXMAXP));
0400 }
0401 
0402 /*
0403  * FIFO state update (e.g. data ready).
0404  * Called from IRQ,  with controller locked.
0405  */
0406 void musb_g_tx(struct musb *musb, u8 epnum)
0407 {
0408     u16         csr;
0409     struct musb_request *req;
0410     struct usb_request  *request;
0411     u8 __iomem      *mbase = musb->mregs;
0412     struct musb_ep      *musb_ep = &musb->endpoints[epnum].ep_in;
0413     void __iomem        *epio = musb->endpoints[epnum].regs;
0414     struct dma_channel  *dma;
0415 
0416     musb_ep_select(mbase, epnum);
0417     req = next_request(musb_ep);
0418     request = &req->request;
0419 
0420     csr = musb_readw(epio, MUSB_TXCSR);
0421     musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr);
0422 
0423     dma = is_dma_capable() ? musb_ep->dma : NULL;
0424 
0425     /*
0426      * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
0427      * probably rates reporting as a host error.
0428      */
0429     if (csr & MUSB_TXCSR_P_SENTSTALL) {
0430         csr |=  MUSB_TXCSR_P_WZC_BITS;
0431         csr &= ~MUSB_TXCSR_P_SENTSTALL;
0432         musb_writew(epio, MUSB_TXCSR, csr);
0433         return;
0434     }
0435 
0436     if (csr & MUSB_TXCSR_P_UNDERRUN) {
0437         /* We NAKed, no big deal... little reason to care. */
0438         csr |=   MUSB_TXCSR_P_WZC_BITS;
0439         csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
0440         musb_writew(epio, MUSB_TXCSR, csr);
0441         dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
0442                 epnum, request);
0443     }
0444 
0445     if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
0446         /*
0447          * SHOULD NOT HAPPEN... has with CPPI though, after
0448          * changing SENDSTALL (and other cases); harmless?
0449          */
0450         musb_dbg(musb, "%s dma still busy?", musb_ep->end_point.name);
0451         return;
0452     }
0453 
0454     if (req) {
0455 
0456         trace_musb_req_tx(req);
0457 
0458         if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
0459             csr |= MUSB_TXCSR_P_WZC_BITS;
0460             csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
0461                  MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
0462             musb_writew(epio, MUSB_TXCSR, csr);
0463             /* Ensure writebuffer is empty. */
0464             csr = musb_readw(epio, MUSB_TXCSR);
0465             request->actual += musb_ep->dma->actual_len;
0466             musb_dbg(musb, "TXCSR%d %04x, DMA off, len %zu, req %p",
0467                 epnum, csr, musb_ep->dma->actual_len, request);
0468         }
0469 
0470         /*
0471          * First, maybe a terminating short packet. Some DMA
0472          * engines might handle this by themselves.
0473          */
0474         if ((request->zero && request->length)
0475             && (request->length % musb_ep->packet_sz == 0)
0476             && (request->actual == request->length)) {
0477 
0478             /*
0479              * On DMA completion, FIFO may not be
0480              * available yet...
0481              */
0482             if (csr & MUSB_TXCSR_TXPKTRDY)
0483                 return;
0484 
0485             musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
0486                     | MUSB_TXCSR_TXPKTRDY);
0487             request->zero = 0;
0488         }
0489 
0490         if (request->actual == request->length) {
0491             musb_g_giveback(musb_ep, request, 0);
0492             /*
0493              * In the giveback function the MUSB lock is
0494              * released and acquired after sometime. During
0495              * this time period the INDEX register could get
0496              * changed by the gadget_queue function especially
0497              * on SMP systems. Reselect the INDEX to be sure
0498              * we are reading/modifying the right registers
0499              */
0500             musb_ep_select(mbase, epnum);
0501             req = musb_ep->desc ? next_request(musb_ep) : NULL;
0502             if (!req) {
0503                 musb_dbg(musb, "%s idle now",
0504                     musb_ep->end_point.name);
0505                 return;
0506             }
0507         }
0508 
0509         txstate(musb, req);
0510     }
0511 }
0512 
0513 /* ------------------------------------------------------------ */
0514 
0515 /*
0516  * Context: controller locked, IRQs blocked, endpoint selected
0517  */
0518 static void rxstate(struct musb *musb, struct musb_request *req)
0519 {
0520     const u8        epnum = req->epnum;
0521     struct usb_request  *request = &req->request;
0522     struct musb_ep      *musb_ep;
0523     void __iomem        *epio = musb->endpoints[epnum].regs;
0524     unsigned        len = 0;
0525     u16         fifo_count;
0526     u16         csr = musb_readw(epio, MUSB_RXCSR);
0527     struct musb_hw_ep   *hw_ep = &musb->endpoints[epnum];
0528     u8          use_mode_1;
0529 
0530     if (hw_ep->is_shared_fifo)
0531         musb_ep = &hw_ep->ep_in;
0532     else
0533         musb_ep = &hw_ep->ep_out;
0534 
0535     fifo_count = musb_ep->packet_sz;
0536 
0537     /* Check if EP is disabled */
0538     if (!musb_ep->desc) {
0539         musb_dbg(musb, "ep:%s disabled - ignore request",
0540                         musb_ep->end_point.name);
0541         return;
0542     }
0543 
0544     /* We shouldn't get here while DMA is active, but we do... */
0545     if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
0546         musb_dbg(musb, "DMA pending...");
0547         return;
0548     }
0549 
0550     if (csr & MUSB_RXCSR_P_SENDSTALL) {
0551         musb_dbg(musb, "%s stalling, RXCSR %04x",
0552             musb_ep->end_point.name, csr);
0553         return;
0554     }
0555 
0556     if (is_cppi_enabled(musb) && is_buffer_mapped(req)) {
0557         struct dma_controller   *c = musb->dma_controller;
0558         struct dma_channel  *channel = musb_ep->dma;
0559 
0560         /* NOTE:  CPPI won't actually stop advancing the DMA
0561          * queue after short packet transfers, so this is almost
0562          * always going to run as IRQ-per-packet DMA so that
0563          * faults will be handled correctly.
0564          */
0565         if (c->channel_program(channel,
0566                 musb_ep->packet_sz,
0567                 !request->short_not_ok,
0568                 request->dma + request->actual,
0569                 request->length - request->actual)) {
0570 
0571             /* make sure that if an rxpkt arrived after the irq,
0572              * the cppi engine will be ready to take it as soon
0573              * as DMA is enabled
0574              */
0575             csr &= ~(MUSB_RXCSR_AUTOCLEAR
0576                     | MUSB_RXCSR_DMAMODE);
0577             csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
0578             musb_writew(epio, MUSB_RXCSR, csr);
0579             return;
0580         }
0581     }
0582 
0583     if (csr & MUSB_RXCSR_RXPKTRDY) {
0584         fifo_count = musb_readw(epio, MUSB_RXCOUNT);
0585 
0586         /*
0587          * Enable Mode 1 on RX transfers only when short_not_ok flag
0588          * is set. Currently short_not_ok flag is set only from
0589          * file_storage and f_mass_storage drivers
0590          */
0591 
0592         if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
0593             use_mode_1 = 1;
0594         else
0595             use_mode_1 = 0;
0596 
0597         if (request->actual < request->length) {
0598             if (!is_buffer_mapped(req))
0599                 goto buffer_aint_mapped;
0600 
0601             if (musb_dma_inventra(musb)) {
0602                 struct dma_controller   *c;
0603                 struct dma_channel  *channel;
0604                 int         use_dma = 0;
0605                 unsigned int transfer_size;
0606 
0607                 c = musb->dma_controller;
0608                 channel = musb_ep->dma;
0609 
0610     /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
0611      * mode 0 only. So we do not get endpoint interrupts due to DMA
0612      * completion. We only get interrupts from DMA controller.
0613      *
0614      * We could operate in DMA mode 1 if we knew the size of the transfer
0615      * in advance. For mass storage class, request->length = what the host
0616      * sends, so that'd work.  But for pretty much everything else,
0617      * request->length is routinely more than what the host sends. For
0618      * most these gadgets, end of is signified either by a short packet,
0619      * or filling the last byte of the buffer.  (Sending extra data in
0620      * that last pckate should trigger an overflow fault.)  But in mode 1,
0621      * we don't get DMA completion interrupt for short packets.
0622      *
0623      * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
0624      * to get endpoint interrupt on every DMA req, but that didn't seem
0625      * to work reliably.
0626      *
0627      * REVISIT an updated g_file_storage can set req->short_not_ok, which
0628      * then becomes usable as a runtime "use mode 1" hint...
0629      */
0630 
0631                 /* Experimental: Mode1 works with mass storage use cases */
0632                 if (use_mode_1) {
0633                     csr |= MUSB_RXCSR_AUTOCLEAR;
0634                     musb_writew(epio, MUSB_RXCSR, csr);
0635                     csr |= MUSB_RXCSR_DMAENAB;
0636                     musb_writew(epio, MUSB_RXCSR, csr);
0637 
0638                     /*
0639                      * this special sequence (enabling and then
0640                      * disabling MUSB_RXCSR_DMAMODE) is required
0641                      * to get DMAReq to activate
0642                      */
0643                     musb_writew(epio, MUSB_RXCSR,
0644                         csr | MUSB_RXCSR_DMAMODE);
0645                     musb_writew(epio, MUSB_RXCSR, csr);
0646 
0647                     transfer_size = min_t(unsigned int,
0648                             request->length -
0649                             request->actual,
0650                             channel->max_len);
0651                     musb_ep->dma->desired_mode = 1;
0652                 } else {
0653                     if (!musb_ep->hb_mult &&
0654                         musb_ep->hw_ep->rx_double_buffered)
0655                         csr |= MUSB_RXCSR_AUTOCLEAR;
0656                     csr |= MUSB_RXCSR_DMAENAB;
0657                     musb_writew(epio, MUSB_RXCSR, csr);
0658 
0659                     transfer_size = min(request->length - request->actual,
0660                             (unsigned)fifo_count);
0661                     musb_ep->dma->desired_mode = 0;
0662                 }
0663 
0664                 use_dma = c->channel_program(
0665                         channel,
0666                         musb_ep->packet_sz,
0667                         channel->desired_mode,
0668                         request->dma
0669                         + request->actual,
0670                         transfer_size);
0671 
0672                 if (use_dma)
0673                     return;
0674             }
0675 
0676             if ((musb_dma_ux500(musb)) &&
0677                 (request->actual < request->length)) {
0678 
0679                 struct dma_controller *c;
0680                 struct dma_channel *channel;
0681                 unsigned int transfer_size = 0;
0682 
0683                 c = musb->dma_controller;
0684                 channel = musb_ep->dma;
0685 
0686                 /* In case first packet is short */
0687                 if (fifo_count < musb_ep->packet_sz)
0688                     transfer_size = fifo_count;
0689                 else if (request->short_not_ok)
0690                     transfer_size = min_t(unsigned int,
0691                             request->length -
0692                             request->actual,
0693                             channel->max_len);
0694                 else
0695                     transfer_size = min_t(unsigned int,
0696                             request->length -
0697                             request->actual,
0698                             (unsigned)fifo_count);
0699 
0700                 csr &= ~MUSB_RXCSR_DMAMODE;
0701                 csr |= (MUSB_RXCSR_DMAENAB |
0702                     MUSB_RXCSR_AUTOCLEAR);
0703 
0704                 musb_writew(epio, MUSB_RXCSR, csr);
0705 
0706                 if (transfer_size <= musb_ep->packet_sz) {
0707                     musb_ep->dma->desired_mode = 0;
0708                 } else {
0709                     musb_ep->dma->desired_mode = 1;
0710                     /* Mode must be set after DMAENAB */
0711                     csr |= MUSB_RXCSR_DMAMODE;
0712                     musb_writew(epio, MUSB_RXCSR, csr);
0713                 }
0714 
0715                 if (c->channel_program(channel,
0716                             musb_ep->packet_sz,
0717                             channel->desired_mode,
0718                             request->dma
0719                             + request->actual,
0720                             transfer_size))
0721 
0722                     return;
0723             }
0724 
0725             len = request->length - request->actual;
0726             musb_dbg(musb, "%s OUT/RX pio fifo %d/%d, maxpacket %d",
0727                     musb_ep->end_point.name,
0728                     fifo_count, len,
0729                     musb_ep->packet_sz);
0730 
0731             fifo_count = min_t(unsigned, len, fifo_count);
0732 
0733             if (tusb_dma_omap(musb)) {
0734                 struct dma_controller *c = musb->dma_controller;
0735                 struct dma_channel *channel = musb_ep->dma;
0736                 u32 dma_addr = request->dma + request->actual;
0737                 int ret;
0738 
0739                 ret = c->channel_program(channel,
0740                         musb_ep->packet_sz,
0741                         channel->desired_mode,
0742                         dma_addr,
0743                         fifo_count);
0744                 if (ret)
0745                     return;
0746             }
0747 
0748             /*
0749              * Unmap the dma buffer back to cpu if dma channel
0750              * programming fails. This buffer is mapped if the
0751              * channel allocation is successful
0752              */
0753             unmap_dma_buffer(req, musb);
0754 
0755             /*
0756              * Clear DMAENAB and AUTOCLEAR for the
0757              * PIO mode transfer
0758              */
0759             csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
0760             musb_writew(epio, MUSB_RXCSR, csr);
0761 
0762 buffer_aint_mapped:
0763             musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
0764                     (request->buf + request->actual));
0765             request->actual += fifo_count;
0766 
0767             /* REVISIT if we left anything in the fifo, flush
0768              * it and report -EOVERFLOW
0769              */
0770 
0771             /* ack the read! */
0772             csr |= MUSB_RXCSR_P_WZC_BITS;
0773             csr &= ~MUSB_RXCSR_RXPKTRDY;
0774             musb_writew(epio, MUSB_RXCSR, csr);
0775         }
0776     }
0777 
0778     /* reach the end or short packet detected */
0779     if (request->actual == request->length ||
0780         fifo_count < musb_ep->packet_sz)
0781         musb_g_giveback(musb_ep, request, 0);
0782 }
0783 
0784 /*
0785  * Data ready for a request; called from IRQ
0786  */
0787 void musb_g_rx(struct musb *musb, u8 epnum)
0788 {
0789     u16         csr;
0790     struct musb_request *req;
0791     struct usb_request  *request;
0792     void __iomem        *mbase = musb->mregs;
0793     struct musb_ep      *musb_ep;
0794     void __iomem        *epio = musb->endpoints[epnum].regs;
0795     struct dma_channel  *dma;
0796     struct musb_hw_ep   *hw_ep = &musb->endpoints[epnum];
0797 
0798     if (hw_ep->is_shared_fifo)
0799         musb_ep = &hw_ep->ep_in;
0800     else
0801         musb_ep = &hw_ep->ep_out;
0802 
0803     musb_ep_select(mbase, epnum);
0804 
0805     req = next_request(musb_ep);
0806     if (!req)
0807         return;
0808 
0809     trace_musb_req_rx(req);
0810     request = &req->request;
0811 
0812     csr = musb_readw(epio, MUSB_RXCSR);
0813     dma = is_dma_capable() ? musb_ep->dma : NULL;
0814 
0815     musb_dbg(musb, "<== %s, rxcsr %04x%s %p", musb_ep->end_point.name,
0816             csr, dma ? " (dma)" : "", request);
0817 
0818     if (csr & MUSB_RXCSR_P_SENTSTALL) {
0819         csr |= MUSB_RXCSR_P_WZC_BITS;
0820         csr &= ~MUSB_RXCSR_P_SENTSTALL;
0821         musb_writew(epio, MUSB_RXCSR, csr);
0822         return;
0823     }
0824 
0825     if (csr & MUSB_RXCSR_P_OVERRUN) {
0826         /* csr |= MUSB_RXCSR_P_WZC_BITS; */
0827         csr &= ~MUSB_RXCSR_P_OVERRUN;
0828         musb_writew(epio, MUSB_RXCSR, csr);
0829 
0830         musb_dbg(musb, "%s iso overrun on %p", musb_ep->name, request);
0831         if (request->status == -EINPROGRESS)
0832             request->status = -EOVERFLOW;
0833     }
0834     if (csr & MUSB_RXCSR_INCOMPRX) {
0835         /* REVISIT not necessarily an error */
0836         musb_dbg(musb, "%s, incomprx", musb_ep->end_point.name);
0837     }
0838 
0839     if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
0840         /* "should not happen"; likely RXPKTRDY pending for DMA */
0841         musb_dbg(musb, "%s busy, csr %04x",
0842             musb_ep->end_point.name, csr);
0843         return;
0844     }
0845 
0846     if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
0847         csr &= ~(MUSB_RXCSR_AUTOCLEAR
0848                 | MUSB_RXCSR_DMAENAB
0849                 | MUSB_RXCSR_DMAMODE);
0850         musb_writew(epio, MUSB_RXCSR,
0851             MUSB_RXCSR_P_WZC_BITS | csr);
0852 
0853         request->actual += musb_ep->dma->actual_len;
0854 
0855 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
0856     defined(CONFIG_USB_UX500_DMA)
0857         /* Autoclear doesn't clear RxPktRdy for short packets */
0858         if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
0859                 || (dma->actual_len
0860                     & (musb_ep->packet_sz - 1))) {
0861             /* ack the read! */
0862             csr &= ~MUSB_RXCSR_RXPKTRDY;
0863             musb_writew(epio, MUSB_RXCSR, csr);
0864         }
0865 
0866         /* incomplete, and not short? wait for next IN packet */
0867         if ((request->actual < request->length)
0868                 && (musb_ep->dma->actual_len
0869                     == musb_ep->packet_sz)) {
0870             /* In double buffer case, continue to unload fifo if
0871              * there is Rx packet in FIFO.
0872              **/
0873             csr = musb_readw(epio, MUSB_RXCSR);
0874             if ((csr & MUSB_RXCSR_RXPKTRDY) &&
0875                 hw_ep->rx_double_buffered)
0876                 goto exit;
0877             return;
0878         }
0879 #endif
0880         musb_g_giveback(musb_ep, request, 0);
0881         /*
0882          * In the giveback function the MUSB lock is
0883          * released and acquired after sometime. During
0884          * this time period the INDEX register could get
0885          * changed by the gadget_queue function especially
0886          * on SMP systems. Reselect the INDEX to be sure
0887          * we are reading/modifying the right registers
0888          */
0889         musb_ep_select(mbase, epnum);
0890 
0891         req = next_request(musb_ep);
0892         if (!req)
0893             return;
0894     }
0895 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
0896     defined(CONFIG_USB_UX500_DMA)
0897 exit:
0898 #endif
0899     /* Analyze request */
0900     rxstate(musb, req);
0901 }
0902 
0903 /* ------------------------------------------------------------ */
0904 
0905 static int musb_gadget_enable(struct usb_ep *ep,
0906             const struct usb_endpoint_descriptor *desc)
0907 {
0908     unsigned long       flags;
0909     struct musb_ep      *musb_ep;
0910     struct musb_hw_ep   *hw_ep;
0911     void __iomem        *regs;
0912     struct musb     *musb;
0913     void __iomem    *mbase;
0914     u8      epnum;
0915     u16     csr;
0916     unsigned    tmp;
0917     int     status = -EINVAL;
0918 
0919     if (!ep || !desc)
0920         return -EINVAL;
0921 
0922     musb_ep = to_musb_ep(ep);
0923     hw_ep = musb_ep->hw_ep;
0924     regs = hw_ep->regs;
0925     musb = musb_ep->musb;
0926     mbase = musb->mregs;
0927     epnum = musb_ep->current_epnum;
0928 
0929     spin_lock_irqsave(&musb->lock, flags);
0930 
0931     if (musb_ep->desc) {
0932         status = -EBUSY;
0933         goto fail;
0934     }
0935     musb_ep->type = usb_endpoint_type(desc);
0936 
0937     /* check direction and (later) maxpacket size against endpoint */
0938     if (usb_endpoint_num(desc) != epnum)
0939         goto fail;
0940 
0941     /* REVISIT this rules out high bandwidth periodic transfers */
0942     tmp = usb_endpoint_maxp_mult(desc) - 1;
0943     if (tmp) {
0944         int ok;
0945 
0946         if (usb_endpoint_dir_in(desc))
0947             ok = musb->hb_iso_tx;
0948         else
0949             ok = musb->hb_iso_rx;
0950 
0951         if (!ok) {
0952             musb_dbg(musb, "no support for high bandwidth ISO");
0953             goto fail;
0954         }
0955         musb_ep->hb_mult = tmp;
0956     } else {
0957         musb_ep->hb_mult = 0;
0958     }
0959 
0960     musb_ep->packet_sz = usb_endpoint_maxp(desc);
0961     tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
0962 
0963     /* enable the interrupts for the endpoint, set the endpoint
0964      * packet size (or fail), set the mode, clear the fifo
0965      */
0966     musb_ep_select(mbase, epnum);
0967     if (usb_endpoint_dir_in(desc)) {
0968 
0969         if (hw_ep->is_shared_fifo)
0970             musb_ep->is_in = 1;
0971         if (!musb_ep->is_in)
0972             goto fail;
0973 
0974         if (tmp > hw_ep->max_packet_sz_tx) {
0975             musb_dbg(musb, "packet size beyond hardware FIFO size");
0976             goto fail;
0977         }
0978 
0979         musb->intrtxe |= (1 << epnum);
0980         musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
0981 
0982         /* REVISIT if can_bulk_split(), use by updating "tmp";
0983          * likewise high bandwidth periodic tx
0984          */
0985         /* Set TXMAXP with the FIFO size of the endpoint
0986          * to disable double buffering mode.
0987          */
0988         if (can_bulk_split(musb, musb_ep->type))
0989             musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
0990                         musb_ep->packet_sz) - 1;
0991         musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
0992                 | (musb_ep->hb_mult << 11));
0993 
0994         csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
0995         if (musb_readw(regs, MUSB_TXCSR)
0996                 & MUSB_TXCSR_FIFONOTEMPTY)
0997             csr |= MUSB_TXCSR_FLUSHFIFO;
0998         if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
0999             csr |= MUSB_TXCSR_P_ISO;
1000 
1001         /* set twice in case of double buffering */
1002         musb_writew(regs, MUSB_TXCSR, csr);
1003         /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1004         musb_writew(regs, MUSB_TXCSR, csr);
1005 
1006     } else {
1007 
1008         if (hw_ep->is_shared_fifo)
1009             musb_ep->is_in = 0;
1010         if (musb_ep->is_in)
1011             goto fail;
1012 
1013         if (tmp > hw_ep->max_packet_sz_rx) {
1014             musb_dbg(musb, "packet size beyond hardware FIFO size");
1015             goto fail;
1016         }
1017 
1018         musb->intrrxe |= (1 << epnum);
1019         musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe);
1020 
1021         /* REVISIT if can_bulk_combine() use by updating "tmp"
1022          * likewise high bandwidth periodic rx
1023          */
1024         /* Set RXMAXP with the FIFO size of the endpoint
1025          * to disable double buffering mode.
1026          */
1027         musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1028                 | (musb_ep->hb_mult << 11));
1029 
1030         /* force shared fifo to OUT-only mode */
1031         if (hw_ep->is_shared_fifo) {
1032             csr = musb_readw(regs, MUSB_TXCSR);
1033             csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1034             musb_writew(regs, MUSB_TXCSR, csr);
1035         }
1036 
1037         csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1038         if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1039             csr |= MUSB_RXCSR_P_ISO;
1040         else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1041             csr |= MUSB_RXCSR_DISNYET;
1042 
1043         /* set twice in case of double buffering */
1044         musb_writew(regs, MUSB_RXCSR, csr);
1045         musb_writew(regs, MUSB_RXCSR, csr);
1046     }
1047 
1048     /* NOTE:  all the I/O code _should_ work fine without DMA, in case
1049      * for some reason you run out of channels here.
1050      */
1051     if (is_dma_capable() && musb->dma_controller) {
1052         struct dma_controller   *c = musb->dma_controller;
1053 
1054         musb_ep->dma = c->channel_alloc(c, hw_ep,
1055                 (desc->bEndpointAddress & USB_DIR_IN));
1056     } else
1057         musb_ep->dma = NULL;
1058 
1059     musb_ep->desc = desc;
1060     musb_ep->busy = 0;
1061     musb_ep->wedged = 0;
1062     status = 0;
1063 
1064     pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1065             musb_driver_name, musb_ep->end_point.name,
1066             musb_ep_xfertype_string(musb_ep->type),
1067             musb_ep->is_in ? "IN" : "OUT",
1068             musb_ep->dma ? "dma, " : "",
1069             musb_ep->packet_sz);
1070 
1071     schedule_delayed_work(&musb->irq_work, 0);
1072 
1073 fail:
1074     spin_unlock_irqrestore(&musb->lock, flags);
1075     return status;
1076 }
1077 
1078 /*
1079  * Disable an endpoint flushing all requests queued.
1080  */
1081 static int musb_gadget_disable(struct usb_ep *ep)
1082 {
1083     unsigned long   flags;
1084     struct musb *musb;
1085     u8      epnum;
1086     struct musb_ep  *musb_ep;
1087     void __iomem    *epio;
1088 
1089     musb_ep = to_musb_ep(ep);
1090     musb = musb_ep->musb;
1091     epnum = musb_ep->current_epnum;
1092     epio = musb->endpoints[epnum].regs;
1093 
1094     spin_lock_irqsave(&musb->lock, flags);
1095     musb_ep_select(musb->mregs, epnum);
1096 
1097     /* zero the endpoint sizes */
1098     if (musb_ep->is_in) {
1099         musb->intrtxe &= ~(1 << epnum);
1100         musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
1101         musb_writew(epio, MUSB_TXMAXP, 0);
1102     } else {
1103         musb->intrrxe &= ~(1 << epnum);
1104         musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
1105         musb_writew(epio, MUSB_RXMAXP, 0);
1106     }
1107 
1108     /* abort all pending DMA and requests */
1109     nuke(musb_ep, -ESHUTDOWN);
1110 
1111     musb_ep->desc = NULL;
1112     musb_ep->end_point.desc = NULL;
1113 
1114     schedule_delayed_work(&musb->irq_work, 0);
1115 
1116     spin_unlock_irqrestore(&(musb->lock), flags);
1117 
1118     musb_dbg(musb, "%s", musb_ep->end_point.name);
1119 
1120     return 0;
1121 }
1122 
1123 /*
1124  * Allocate a request for an endpoint.
1125  * Reused by ep0 code.
1126  */
1127 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1128 {
1129     struct musb_ep      *musb_ep = to_musb_ep(ep);
1130     struct musb_request *request = NULL;
1131 
1132     request = kzalloc(sizeof *request, gfp_flags);
1133     if (!request)
1134         return NULL;
1135 
1136     request->request.dma = DMA_ADDR_INVALID;
1137     request->epnum = musb_ep->current_epnum;
1138     request->ep = musb_ep;
1139 
1140     trace_musb_req_alloc(request);
1141     return &request->request;
1142 }
1143 
1144 /*
1145  * Free a request
1146  * Reused by ep0 code.
1147  */
1148 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1149 {
1150     struct musb_request *request = to_musb_request(req);
1151 
1152     trace_musb_req_free(request);
1153     kfree(request);
1154 }
1155 
1156 static LIST_HEAD(buffers);
1157 
1158 struct free_record {
1159     struct list_head    list;
1160     struct device       *dev;
1161     unsigned        bytes;
1162     dma_addr_t      dma;
1163 };
1164 
1165 /*
1166  * Context: controller locked, IRQs blocked.
1167  */
1168 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1169 {
1170     trace_musb_req_start(req);
1171     musb_ep_select(musb->mregs, req->epnum);
1172     if (req->tx)
1173         txstate(musb, req);
1174     else
1175         rxstate(musb, req);
1176 }
1177 
1178 static int musb_ep_restart_resume_work(struct musb *musb, void *data)
1179 {
1180     struct musb_request *req = data;
1181 
1182     musb_ep_restart(musb, req);
1183 
1184     return 0;
1185 }
1186 
1187 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1188             gfp_t gfp_flags)
1189 {
1190     struct musb_ep      *musb_ep;
1191     struct musb_request *request;
1192     struct musb     *musb;
1193     int         status;
1194     unsigned long       lockflags;
1195 
1196     if (!ep || !req)
1197         return -EINVAL;
1198     if (!req->buf)
1199         return -ENODATA;
1200 
1201     musb_ep = to_musb_ep(ep);
1202     musb = musb_ep->musb;
1203 
1204     request = to_musb_request(req);
1205     request->musb = musb;
1206 
1207     if (request->ep != musb_ep)
1208         return -EINVAL;
1209 
1210     status = pm_runtime_get(musb->controller);
1211     if ((status != -EINPROGRESS) && status < 0) {
1212         dev_err(musb->controller,
1213             "pm runtime get failed in %s\n",
1214             __func__);
1215         pm_runtime_put_noidle(musb->controller);
1216 
1217         return status;
1218     }
1219     status = 0;
1220 
1221     trace_musb_req_enq(request);
1222 
1223     /* request is mine now... */
1224     request->request.actual = 0;
1225     request->request.status = -EINPROGRESS;
1226     request->epnum = musb_ep->current_epnum;
1227     request->tx = musb_ep->is_in;
1228 
1229     map_dma_buffer(request, musb, musb_ep);
1230 
1231     spin_lock_irqsave(&musb->lock, lockflags);
1232 
1233     /* don't queue if the ep is down */
1234     if (!musb_ep->desc) {
1235         musb_dbg(musb, "req %p queued to %s while ep %s",
1236                 req, ep->name, "disabled");
1237         status = -ESHUTDOWN;
1238         unmap_dma_buffer(request, musb);
1239         goto unlock;
1240     }
1241 
1242     /* add request to the list */
1243     list_add_tail(&request->list, &musb_ep->req_list);
1244 
1245     /* it this is the head of the queue, start i/o ... */
1246     if (!musb_ep->busy && &request->list == musb_ep->req_list.next) {
1247         status = musb_queue_resume_work(musb,
1248                         musb_ep_restart_resume_work,
1249                         request);
1250         if (status < 0) {
1251             dev_err(musb->controller, "%s resume work: %i\n",
1252                 __func__, status);
1253             list_del(&request->list);
1254         }
1255     }
1256 
1257 unlock:
1258     spin_unlock_irqrestore(&musb->lock, lockflags);
1259     pm_runtime_mark_last_busy(musb->controller);
1260     pm_runtime_put_autosuspend(musb->controller);
1261 
1262     return status;
1263 }
1264 
1265 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1266 {
1267     struct musb_ep      *musb_ep = to_musb_ep(ep);
1268     struct musb_request *req = to_musb_request(request);
1269     struct musb_request *r;
1270     unsigned long       flags;
1271     int         status = 0;
1272     struct musb     *musb = musb_ep->musb;
1273 
1274     if (!ep || !request || req->ep != musb_ep)
1275         return -EINVAL;
1276 
1277     trace_musb_req_deq(req);
1278 
1279     spin_lock_irqsave(&musb->lock, flags);
1280 
1281     list_for_each_entry(r, &musb_ep->req_list, list) {
1282         if (r == req)
1283             break;
1284     }
1285     if (r != req) {
1286         dev_err(musb->controller, "request %p not queued to %s\n",
1287                 request, ep->name);
1288         status = -EINVAL;
1289         goto done;
1290     }
1291 
1292     /* if the hardware doesn't have the request, easy ... */
1293     if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1294         musb_g_giveback(musb_ep, request, -ECONNRESET);
1295 
1296     /* ... else abort the dma transfer ... */
1297     else if (is_dma_capable() && musb_ep->dma) {
1298         struct dma_controller   *c = musb->dma_controller;
1299 
1300         musb_ep_select(musb->mregs, musb_ep->current_epnum);
1301         if (c->channel_abort)
1302             status = c->channel_abort(musb_ep->dma);
1303         else
1304             status = -EBUSY;
1305         if (status == 0)
1306             musb_g_giveback(musb_ep, request, -ECONNRESET);
1307     } else {
1308         /* NOTE: by sticking to easily tested hardware/driver states,
1309          * we leave counting of in-flight packets imprecise.
1310          */
1311         musb_g_giveback(musb_ep, request, -ECONNRESET);
1312     }
1313 
1314 done:
1315     spin_unlock_irqrestore(&musb->lock, flags);
1316     return status;
1317 }
1318 
1319 /*
1320  * Set or clear the halt bit of an endpoint. A halted endpoint won't tx/rx any
1321  * data but will queue requests.
1322  *
1323  * exported to ep0 code
1324  */
1325 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1326 {
1327     struct musb_ep      *musb_ep = to_musb_ep(ep);
1328     u8          epnum = musb_ep->current_epnum;
1329     struct musb     *musb = musb_ep->musb;
1330     void __iomem        *epio = musb->endpoints[epnum].regs;
1331     void __iomem        *mbase;
1332     unsigned long       flags;
1333     u16         csr;
1334     struct musb_request *request;
1335     int         status = 0;
1336 
1337     if (!ep)
1338         return -EINVAL;
1339     mbase = musb->mregs;
1340 
1341     spin_lock_irqsave(&musb->lock, flags);
1342 
1343     if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1344         status = -EINVAL;
1345         goto done;
1346     }
1347 
1348     musb_ep_select(mbase, epnum);
1349 
1350     request = next_request(musb_ep);
1351     if (value) {
1352         if (request) {
1353             musb_dbg(musb, "request in progress, cannot halt %s",
1354                 ep->name);
1355             status = -EAGAIN;
1356             goto done;
1357         }
1358         /* Cannot portably stall with non-empty FIFO */
1359         if (musb_ep->is_in) {
1360             csr = musb_readw(epio, MUSB_TXCSR);
1361             if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1362                 musb_dbg(musb, "FIFO busy, cannot halt %s",
1363                         ep->name);
1364                 status = -EAGAIN;
1365                 goto done;
1366             }
1367         }
1368     } else
1369         musb_ep->wedged = 0;
1370 
1371     /* set/clear the stall and toggle bits */
1372     musb_dbg(musb, "%s: %s stall", ep->name, value ? "set" : "clear");
1373     if (musb_ep->is_in) {
1374         csr = musb_readw(epio, MUSB_TXCSR);
1375         csr |= MUSB_TXCSR_P_WZC_BITS
1376             | MUSB_TXCSR_CLRDATATOG;
1377         if (value)
1378             csr |= MUSB_TXCSR_P_SENDSTALL;
1379         else
1380             csr &= ~(MUSB_TXCSR_P_SENDSTALL
1381                 | MUSB_TXCSR_P_SENTSTALL);
1382         csr &= ~MUSB_TXCSR_TXPKTRDY;
1383         musb_writew(epio, MUSB_TXCSR, csr);
1384     } else {
1385         csr = musb_readw(epio, MUSB_RXCSR);
1386         csr |= MUSB_RXCSR_P_WZC_BITS
1387             | MUSB_RXCSR_FLUSHFIFO
1388             | MUSB_RXCSR_CLRDATATOG;
1389         if (value)
1390             csr |= MUSB_RXCSR_P_SENDSTALL;
1391         else
1392             csr &= ~(MUSB_RXCSR_P_SENDSTALL
1393                 | MUSB_RXCSR_P_SENTSTALL);
1394         musb_writew(epio, MUSB_RXCSR, csr);
1395     }
1396 
1397     /* maybe start the first request in the queue */
1398     if (!musb_ep->busy && !value && request) {
1399         musb_dbg(musb, "restarting the request");
1400         musb_ep_restart(musb, request);
1401     }
1402 
1403 done:
1404     spin_unlock_irqrestore(&musb->lock, flags);
1405     return status;
1406 }
1407 
1408 /*
1409  * Sets the halt feature with the clear requests ignored
1410  */
1411 static int musb_gadget_set_wedge(struct usb_ep *ep)
1412 {
1413     struct musb_ep      *musb_ep = to_musb_ep(ep);
1414 
1415     if (!ep)
1416         return -EINVAL;
1417 
1418     musb_ep->wedged = 1;
1419 
1420     return usb_ep_set_halt(ep);
1421 }
1422 
1423 static int musb_gadget_fifo_status(struct usb_ep *ep)
1424 {
1425     struct musb_ep      *musb_ep = to_musb_ep(ep);
1426     void __iomem        *epio = musb_ep->hw_ep->regs;
1427     int         retval = -EINVAL;
1428 
1429     if (musb_ep->desc && !musb_ep->is_in) {
1430         struct musb     *musb = musb_ep->musb;
1431         int         epnum = musb_ep->current_epnum;
1432         void __iomem        *mbase = musb->mregs;
1433         unsigned long       flags;
1434 
1435         spin_lock_irqsave(&musb->lock, flags);
1436 
1437         musb_ep_select(mbase, epnum);
1438         /* FIXME return zero unless RXPKTRDY is set */
1439         retval = musb_readw(epio, MUSB_RXCOUNT);
1440 
1441         spin_unlock_irqrestore(&musb->lock, flags);
1442     }
1443     return retval;
1444 }
1445 
1446 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1447 {
1448     struct musb_ep  *musb_ep = to_musb_ep(ep);
1449     struct musb *musb = musb_ep->musb;
1450     u8      epnum = musb_ep->current_epnum;
1451     void __iomem    *epio = musb->endpoints[epnum].regs;
1452     void __iomem    *mbase;
1453     unsigned long   flags;
1454     u16     csr;
1455 
1456     mbase = musb->mregs;
1457 
1458     spin_lock_irqsave(&musb->lock, flags);
1459     musb_ep_select(mbase, (u8) epnum);
1460 
1461     /* disable interrupts */
1462     musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum));
1463 
1464     if (musb_ep->is_in) {
1465         csr = musb_readw(epio, MUSB_TXCSR);
1466         if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1467             csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1468             /*
1469              * Setting both TXPKTRDY and FLUSHFIFO makes controller
1470              * to interrupt current FIFO loading, but not flushing
1471              * the already loaded ones.
1472              */
1473             csr &= ~MUSB_TXCSR_TXPKTRDY;
1474             musb_writew(epio, MUSB_TXCSR, csr);
1475             /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1476             musb_writew(epio, MUSB_TXCSR, csr);
1477         }
1478     } else {
1479         csr = musb_readw(epio, MUSB_RXCSR);
1480         csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1481         musb_writew(epio, MUSB_RXCSR, csr);
1482         musb_writew(epio, MUSB_RXCSR, csr);
1483     }
1484 
1485     /* re-enable interrupt */
1486     musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1487     spin_unlock_irqrestore(&musb->lock, flags);
1488 }
1489 
1490 static const struct usb_ep_ops musb_ep_ops = {
1491     .enable     = musb_gadget_enable,
1492     .disable    = musb_gadget_disable,
1493     .alloc_request  = musb_alloc_request,
1494     .free_request   = musb_free_request,
1495     .queue      = musb_gadget_queue,
1496     .dequeue    = musb_gadget_dequeue,
1497     .set_halt   = musb_gadget_set_halt,
1498     .set_wedge  = musb_gadget_set_wedge,
1499     .fifo_status    = musb_gadget_fifo_status,
1500     .fifo_flush = musb_gadget_fifo_flush
1501 };
1502 
1503 /* ----------------------------------------------------------------------- */
1504 
1505 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1506 {
1507     struct musb *musb = gadget_to_musb(gadget);
1508 
1509     return (int)musb_readw(musb->mregs, MUSB_FRAME);
1510 }
1511 
1512 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1513 {
1514     struct musb *musb = gadget_to_musb(gadget);
1515     void __iomem    *mregs = musb->mregs;
1516     unsigned long   flags;
1517     int     status = -EINVAL;
1518     u8      power, devctl;
1519     int     retries;
1520 
1521     spin_lock_irqsave(&musb->lock, flags);
1522 
1523     switch (musb->xceiv->otg->state) {
1524     case OTG_STATE_B_PERIPHERAL:
1525         /* NOTE:  OTG state machine doesn't include B_SUSPENDED;
1526          * that's part of the standard usb 1.1 state machine, and
1527          * doesn't affect OTG transitions.
1528          */
1529         if (musb->may_wakeup && musb->is_suspended)
1530             break;
1531         goto done;
1532     case OTG_STATE_B_IDLE:
1533         /* Start SRP ... OTG not required. */
1534         devctl = musb_readb(mregs, MUSB_DEVCTL);
1535         musb_dbg(musb, "Sending SRP: devctl: %02x", devctl);
1536         devctl |= MUSB_DEVCTL_SESSION;
1537         musb_writeb(mregs, MUSB_DEVCTL, devctl);
1538         devctl = musb_readb(mregs, MUSB_DEVCTL);
1539         retries = 100;
1540         while (!(devctl & MUSB_DEVCTL_SESSION)) {
1541             devctl = musb_readb(mregs, MUSB_DEVCTL);
1542             if (retries-- < 1)
1543                 break;
1544         }
1545         retries = 10000;
1546         while (devctl & MUSB_DEVCTL_SESSION) {
1547             devctl = musb_readb(mregs, MUSB_DEVCTL);
1548             if (retries-- < 1)
1549                 break;
1550         }
1551 
1552         spin_unlock_irqrestore(&musb->lock, flags);
1553         otg_start_srp(musb->xceiv->otg);
1554         spin_lock_irqsave(&musb->lock, flags);
1555 
1556         /* Block idling for at least 1s */
1557         musb_platform_try_idle(musb,
1558             jiffies + msecs_to_jiffies(1 * HZ));
1559 
1560         status = 0;
1561         goto done;
1562     default:
1563         musb_dbg(musb, "Unhandled wake: %s",
1564             usb_otg_state_string(musb->xceiv->otg->state));
1565         goto done;
1566     }
1567 
1568     status = 0;
1569 
1570     power = musb_readb(mregs, MUSB_POWER);
1571     power |= MUSB_POWER_RESUME;
1572     musb_writeb(mregs, MUSB_POWER, power);
1573     musb_dbg(musb, "issue wakeup");
1574 
1575     /* FIXME do this next chunk in a timer callback, no udelay */
1576     mdelay(2);
1577 
1578     power = musb_readb(mregs, MUSB_POWER);
1579     power &= ~MUSB_POWER_RESUME;
1580     musb_writeb(mregs, MUSB_POWER, power);
1581 done:
1582     spin_unlock_irqrestore(&musb->lock, flags);
1583     return status;
1584 }
1585 
1586 static int
1587 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1588 {
1589     gadget->is_selfpowered = !!is_selfpowered;
1590     return 0;
1591 }
1592 
1593 static void musb_pullup(struct musb *musb, int is_on)
1594 {
1595     u8 power;
1596 
1597     power = musb_readb(musb->mregs, MUSB_POWER);
1598     if (is_on)
1599         power |= MUSB_POWER_SOFTCONN;
1600     else
1601         power &= ~MUSB_POWER_SOFTCONN;
1602 
1603     /* FIXME if on, HdrcStart; if off, HdrcStop */
1604 
1605     musb_dbg(musb, "gadget D+ pullup %s",
1606         is_on ? "on" : "off");
1607     musb_writeb(musb->mregs, MUSB_POWER, power);
1608 }
1609 
1610 #if 0
1611 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1612 {
1613     musb_dbg(musb, "<= %s =>\n", __func__);
1614 
1615     /*
1616      * FIXME iff driver's softconnect flag is set (as it is during probe,
1617      * though that can clear it), just musb_pullup().
1618      */
1619 
1620     return -EINVAL;
1621 }
1622 #endif
1623 
1624 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1625 {
1626     struct musb *musb = gadget_to_musb(gadget);
1627 
1628     if (!musb->xceiv->set_power)
1629         return -EOPNOTSUPP;
1630     return usb_phy_set_power(musb->xceiv, mA);
1631 }
1632 
1633 static void musb_gadget_work(struct work_struct *work)
1634 {
1635     struct musb *musb;
1636     unsigned long flags;
1637 
1638     musb = container_of(work, struct musb, gadget_work.work);
1639     pm_runtime_get_sync(musb->controller);
1640     spin_lock_irqsave(&musb->lock, flags);
1641     musb_pullup(musb, musb->softconnect);
1642     spin_unlock_irqrestore(&musb->lock, flags);
1643     pm_runtime_mark_last_busy(musb->controller);
1644     pm_runtime_put_autosuspend(musb->controller);
1645 }
1646 
1647 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1648 {
1649     struct musb *musb = gadget_to_musb(gadget);
1650     unsigned long   flags;
1651 
1652     is_on = !!is_on;
1653 
1654     /* NOTE: this assumes we are sensing vbus; we'd rather
1655      * not pullup unless the B-session is active.
1656      */
1657     spin_lock_irqsave(&musb->lock, flags);
1658     if (is_on != musb->softconnect) {
1659         musb->softconnect = is_on;
1660         schedule_delayed_work(&musb->gadget_work, 0);
1661     }
1662     spin_unlock_irqrestore(&musb->lock, flags);
1663 
1664     return 0;
1665 }
1666 
1667 static int musb_gadget_start(struct usb_gadget *g,
1668         struct usb_gadget_driver *driver);
1669 static int musb_gadget_stop(struct usb_gadget *g);
1670 
1671 static const struct usb_gadget_ops musb_gadget_operations = {
1672     .get_frame      = musb_gadget_get_frame,
1673     .wakeup         = musb_gadget_wakeup,
1674     .set_selfpowered    = musb_gadget_set_self_powered,
1675     /* .vbus_session        = musb_gadget_vbus_session, */
1676     .vbus_draw      = musb_gadget_vbus_draw,
1677     .pullup         = musb_gadget_pullup,
1678     .udc_start      = musb_gadget_start,
1679     .udc_stop       = musb_gadget_stop,
1680 };
1681 
1682 /* ----------------------------------------------------------------------- */
1683 
1684 /* Registration */
1685 
1686 /* Only this registration code "knows" the rule (from USB standards)
1687  * about there being only one external upstream port.  It assumes
1688  * all peripheral ports are external...
1689  */
1690 
1691 static void
1692 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1693 {
1694     struct musb_hw_ep   *hw_ep = musb->endpoints + epnum;
1695 
1696     memset(ep, 0, sizeof *ep);
1697 
1698     ep->current_epnum = epnum;
1699     ep->musb = musb;
1700     ep->hw_ep = hw_ep;
1701     ep->is_in = is_in;
1702 
1703     INIT_LIST_HEAD(&ep->req_list);
1704 
1705     sprintf(ep->name, "ep%d%s", epnum,
1706             (!epnum || hw_ep->is_shared_fifo) ? "" : (
1707                 is_in ? "in" : "out"));
1708     ep->end_point.name = ep->name;
1709     INIT_LIST_HEAD(&ep->end_point.ep_list);
1710     if (!epnum) {
1711         usb_ep_set_maxpacket_limit(&ep->end_point, 64);
1712         ep->end_point.caps.type_control = true;
1713         ep->end_point.ops = &musb_g_ep0_ops;
1714         musb->g.ep0 = &ep->end_point;
1715     } else {
1716         if (is_in)
1717             usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_tx);
1718         else
1719             usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_rx);
1720         ep->end_point.caps.type_iso = true;
1721         ep->end_point.caps.type_bulk = true;
1722         ep->end_point.caps.type_int = true;
1723         ep->end_point.ops = &musb_ep_ops;
1724         list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1725     }
1726 
1727     if (!epnum || hw_ep->is_shared_fifo) {
1728         ep->end_point.caps.dir_in = true;
1729         ep->end_point.caps.dir_out = true;
1730     } else if (is_in)
1731         ep->end_point.caps.dir_in = true;
1732     else
1733         ep->end_point.caps.dir_out = true;
1734 }
1735 
1736 /*
1737  * Initialize the endpoints exposed to peripheral drivers, with backlinks
1738  * to the rest of the driver state.
1739  */
1740 static inline void musb_g_init_endpoints(struct musb *musb)
1741 {
1742     u8          epnum;
1743     struct musb_hw_ep   *hw_ep;
1744     unsigned        count = 0;
1745 
1746     /* initialize endpoint list just once */
1747     INIT_LIST_HEAD(&(musb->g.ep_list));
1748 
1749     for (epnum = 0, hw_ep = musb->endpoints;
1750             epnum < musb->nr_endpoints;
1751             epnum++, hw_ep++) {
1752         if (hw_ep->is_shared_fifo /* || !epnum */) {
1753             init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1754             count++;
1755         } else {
1756             if (hw_ep->max_packet_sz_tx) {
1757                 init_peripheral_ep(musb, &hw_ep->ep_in,
1758                             epnum, 1);
1759                 count++;
1760             }
1761             if (hw_ep->max_packet_sz_rx) {
1762                 init_peripheral_ep(musb, &hw_ep->ep_out,
1763                             epnum, 0);
1764                 count++;
1765             }
1766         }
1767     }
1768 }
1769 
1770 /* called once during driver setup to initialize and link into
1771  * the driver model; memory is zeroed.
1772  */
1773 int musb_gadget_setup(struct musb *musb)
1774 {
1775     int status;
1776 
1777     /* REVISIT minor race:  if (erroneously) setting up two
1778      * musb peripherals at the same time, only the bus lock
1779      * is probably held.
1780      */
1781 
1782     musb->g.ops = &musb_gadget_operations;
1783     musb->g.max_speed = USB_SPEED_HIGH;
1784     musb->g.speed = USB_SPEED_UNKNOWN;
1785 
1786     MUSB_DEV_MODE(musb);
1787     musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1788 
1789     /* this "gadget" abstracts/virtualizes the controller */
1790     musb->g.name = musb_driver_name;
1791     /* don't support otg protocols */
1792     musb->g.is_otg = 0;
1793     INIT_DELAYED_WORK(&musb->gadget_work, musb_gadget_work);
1794     musb_g_init_endpoints(musb);
1795 
1796     musb->is_active = 0;
1797     musb_platform_try_idle(musb, 0);
1798 
1799     status = usb_add_gadget_udc(musb->controller, &musb->g);
1800     if (status)
1801         goto err;
1802 
1803     return 0;
1804 err:
1805     musb->g.dev.parent = NULL;
1806     device_unregister(&musb->g.dev);
1807     return status;
1808 }
1809 
1810 void musb_gadget_cleanup(struct musb *musb)
1811 {
1812     if (musb->port_mode == MUSB_HOST)
1813         return;
1814 
1815     cancel_delayed_work_sync(&musb->gadget_work);
1816     usb_del_gadget_udc(&musb->g);
1817 }
1818 
1819 /*
1820  * Register the gadget driver. Used by gadget drivers when
1821  * registering themselves with the controller.
1822  *
1823  * -EINVAL something went wrong (not driver)
1824  * -EBUSY another gadget is already using the controller
1825  * -ENOMEM no memory to perform the operation
1826  *
1827  * @param driver the gadget driver
1828  * @return <0 if error, 0 if everything is fine
1829  */
1830 static int musb_gadget_start(struct usb_gadget *g,
1831         struct usb_gadget_driver *driver)
1832 {
1833     struct musb     *musb = gadget_to_musb(g);
1834     struct usb_otg      *otg = musb->xceiv->otg;
1835     unsigned long       flags;
1836     int         retval = 0;
1837 
1838     if (driver->max_speed < USB_SPEED_HIGH) {
1839         retval = -EINVAL;
1840         goto err;
1841     }
1842 
1843     pm_runtime_get_sync(musb->controller);
1844 
1845     musb->softconnect = 0;
1846     musb->gadget_driver = driver;
1847 
1848     spin_lock_irqsave(&musb->lock, flags);
1849     musb->is_active = 1;
1850 
1851     otg_set_peripheral(otg, &musb->g);
1852     musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1853     spin_unlock_irqrestore(&musb->lock, flags);
1854 
1855     musb_start(musb);
1856 
1857     /* REVISIT:  funcall to other code, which also
1858      * handles power budgeting ... this way also
1859      * ensures HdrcStart is indirectly called.
1860      */
1861     if (musb->xceiv->last_event == USB_EVENT_ID)
1862         musb_platform_set_vbus(musb, 1);
1863 
1864     pm_runtime_mark_last_busy(musb->controller);
1865     pm_runtime_put_autosuspend(musb->controller);
1866 
1867     return 0;
1868 
1869 err:
1870     return retval;
1871 }
1872 
1873 /*
1874  * Unregister the gadget driver. Used by gadget drivers when
1875  * unregistering themselves from the controller.
1876  *
1877  * @param driver the gadget driver to unregister
1878  */
1879 static int musb_gadget_stop(struct usb_gadget *g)
1880 {
1881     struct musb *musb = gadget_to_musb(g);
1882     unsigned long   flags;
1883 
1884     pm_runtime_get_sync(musb->controller);
1885 
1886     /*
1887      * REVISIT always use otg_set_peripheral() here too;
1888      * this needs to shut down the OTG engine.
1889      */
1890 
1891     spin_lock_irqsave(&musb->lock, flags);
1892 
1893     musb_hnp_stop(musb);
1894 
1895     (void) musb_gadget_vbus_draw(&musb->g, 0);
1896 
1897     musb->xceiv->otg->state = OTG_STATE_UNDEFINED;
1898     musb_stop(musb);
1899     otg_set_peripheral(musb->xceiv->otg, NULL);
1900 
1901     musb->is_active = 0;
1902     musb->gadget_driver = NULL;
1903     musb_platform_try_idle(musb, 0);
1904     spin_unlock_irqrestore(&musb->lock, flags);
1905 
1906     /*
1907      * FIXME we need to be able to register another
1908      * gadget driver here and have everything work;
1909      * that currently misbehaves.
1910      */
1911 
1912     /* Force check of devctl register for PM runtime */
1913     pm_runtime_mark_last_busy(musb->controller);
1914     pm_runtime_put_autosuspend(musb->controller);
1915 
1916     return 0;
1917 }
1918 
1919 /* ----------------------------------------------------------------------- */
1920 
1921 /* lifecycle operations called through plat_uds.c */
1922 
1923 void musb_g_resume(struct musb *musb)
1924 {
1925     musb->is_suspended = 0;
1926     switch (musb->xceiv->otg->state) {
1927     case OTG_STATE_B_IDLE:
1928         break;
1929     case OTG_STATE_B_WAIT_ACON:
1930     case OTG_STATE_B_PERIPHERAL:
1931         musb->is_active = 1;
1932         if (musb->gadget_driver && musb->gadget_driver->resume) {
1933             spin_unlock(&musb->lock);
1934             musb->gadget_driver->resume(&musb->g);
1935             spin_lock(&musb->lock);
1936         }
1937         break;
1938     default:
1939         WARNING("unhandled RESUME transition (%s)\n",
1940                 usb_otg_state_string(musb->xceiv->otg->state));
1941     }
1942 }
1943 
1944 /* called when SOF packets stop for 3+ msec */
1945 void musb_g_suspend(struct musb *musb)
1946 {
1947     u8  devctl;
1948 
1949     devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1950     musb_dbg(musb, "musb_g_suspend: devctl %02x", devctl);
1951 
1952     switch (musb->xceiv->otg->state) {
1953     case OTG_STATE_B_IDLE:
1954         if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1955             musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1956         break;
1957     case OTG_STATE_B_PERIPHERAL:
1958         musb->is_suspended = 1;
1959         if (musb->gadget_driver && musb->gadget_driver->suspend) {
1960             spin_unlock(&musb->lock);
1961             musb->gadget_driver->suspend(&musb->g);
1962             spin_lock(&musb->lock);
1963         }
1964         break;
1965     default:
1966         /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1967          * A_PERIPHERAL may need care too
1968          */
1969         WARNING("unhandled SUSPEND transition (%s)",
1970                 usb_otg_state_string(musb->xceiv->otg->state));
1971     }
1972 }
1973 
1974 /* Called during SRP */
1975 void musb_g_wakeup(struct musb *musb)
1976 {
1977     musb_gadget_wakeup(&musb->g);
1978 }
1979 
1980 /* called when VBUS drops below session threshold, and in other cases */
1981 void musb_g_disconnect(struct musb *musb)
1982 {
1983     void __iomem    *mregs = musb->mregs;
1984     u8  devctl = musb_readb(mregs, MUSB_DEVCTL);
1985 
1986     musb_dbg(musb, "musb_g_disconnect: devctl %02x", devctl);
1987 
1988     /* clear HR */
1989     musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
1990 
1991     /* don't draw vbus until new b-default session */
1992     (void) musb_gadget_vbus_draw(&musb->g, 0);
1993 
1994     musb->g.speed = USB_SPEED_UNKNOWN;
1995     if (musb->gadget_driver && musb->gadget_driver->disconnect) {
1996         spin_unlock(&musb->lock);
1997         musb->gadget_driver->disconnect(&musb->g);
1998         spin_lock(&musb->lock);
1999     }
2000 
2001     switch (musb->xceiv->otg->state) {
2002     default:
2003         musb_dbg(musb, "Unhandled disconnect %s, setting a_idle",
2004             usb_otg_state_string(musb->xceiv->otg->state));
2005         musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2006         MUSB_HST_MODE(musb);
2007         break;
2008     case OTG_STATE_A_PERIPHERAL:
2009         musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
2010         MUSB_HST_MODE(musb);
2011         break;
2012     case OTG_STATE_B_WAIT_ACON:
2013     case OTG_STATE_B_HOST:
2014     case OTG_STATE_B_PERIPHERAL:
2015     case OTG_STATE_B_IDLE:
2016         musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2017         break;
2018     case OTG_STATE_B_SRP_INIT:
2019         break;
2020     }
2021 
2022     musb->is_active = 0;
2023 }
2024 
2025 void musb_g_reset(struct musb *musb)
2026 __releases(musb->lock)
2027 __acquires(musb->lock)
2028 {
2029     void __iomem    *mbase = musb->mregs;
2030     u8      devctl = musb_readb(mbase, MUSB_DEVCTL);
2031     u8      power;
2032 
2033     musb_dbg(musb, "<== %s driver '%s'",
2034             (devctl & MUSB_DEVCTL_BDEVICE)
2035                 ? "B-Device" : "A-Device",
2036             musb->gadget_driver
2037                 ? musb->gadget_driver->driver.name
2038                 : NULL
2039             );
2040 
2041     /* report reset, if we didn't already (flushing EP state) */
2042     if (musb->gadget_driver && musb->g.speed != USB_SPEED_UNKNOWN) {
2043         spin_unlock(&musb->lock);
2044         usb_gadget_udc_reset(&musb->g, musb->gadget_driver);
2045         spin_lock(&musb->lock);
2046     }
2047 
2048     /* clear HR */
2049     else if (devctl & MUSB_DEVCTL_HR)
2050         musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2051 
2052 
2053     /* what speed did we negotiate? */
2054     power = musb_readb(mbase, MUSB_POWER);
2055     musb->g.speed = (power & MUSB_POWER_HSMODE)
2056             ? USB_SPEED_HIGH : USB_SPEED_FULL;
2057 
2058     /* start in USB_STATE_DEFAULT */
2059     musb->is_active = 1;
2060     musb->is_suspended = 0;
2061     MUSB_DEV_MODE(musb);
2062     musb->address = 0;
2063     musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2064 
2065     musb->may_wakeup = 0;
2066     musb->g.b_hnp_enable = 0;
2067     musb->g.a_alt_hnp_support = 0;
2068     musb->g.a_hnp_support = 0;
2069     musb->g.quirk_zlp_not_supp = 1;
2070 
2071     /* Normal reset, as B-Device;
2072      * or else after HNP, as A-Device
2073      */
2074     if (!musb->g.is_otg) {
2075         /* USB device controllers that are not OTG compatible
2076          * may not have DEVCTL register in silicon.
2077          * In that case, do not rely on devctl for setting
2078          * peripheral mode.
2079          */
2080         musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2081         musb->g.is_a_peripheral = 0;
2082     } else if (devctl & MUSB_DEVCTL_BDEVICE) {
2083         musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2084         musb->g.is_a_peripheral = 0;
2085     } else {
2086         musb->xceiv->otg->state = OTG_STATE_A_PERIPHERAL;
2087         musb->g.is_a_peripheral = 1;
2088     }
2089 
2090     /* start with default limits on VBUS power draw */
2091     (void) musb_gadget_vbus_draw(&musb->g, 8);
2092 }
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