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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * MUSB OTG driver defines
0004  *
0005  * Copyright 2005 Mentor Graphics Corporation
0006  * Copyright (C) 2005-2006 by Texas Instruments
0007  * Copyright (C) 2006-2007 Nokia Corporation
0008  */
0009 
0010 #ifndef __MUSB_CORE_H__
0011 #define __MUSB_CORE_H__
0012 
0013 #include <linux/slab.h>
0014 #include <linux/list.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/errno.h>
0017 #include <linux/timer.h>
0018 #include <linux/device.h>
0019 #include <linux/usb/ch9.h>
0020 #include <linux/usb/gadget.h>
0021 #include <linux/usb.h>
0022 #include <linux/usb/otg.h>
0023 #include <linux/usb/musb.h>
0024 #include <linux/phy/phy.h>
0025 #include <linux/workqueue.h>
0026 
0027 struct musb;
0028 struct musb_hw_ep;
0029 struct musb_ep;
0030 struct musb_qh;
0031 
0032 /* Helper defines for struct musb->hwvers */
0033 #define MUSB_HWVERS_MAJOR(x)    ((x >> 10) & 0x1f)
0034 #define MUSB_HWVERS_MINOR(x)    (x & 0x3ff)
0035 #define MUSB_HWVERS_RC      0x8000
0036 #define MUSB_HWVERS_1300    0x52C
0037 #define MUSB_HWVERS_1400    0x590
0038 #define MUSB_HWVERS_1800    0x720
0039 #define MUSB_HWVERS_1900    0x784
0040 #define MUSB_HWVERS_2000    0x800
0041 
0042 #include "musb_debug.h"
0043 #include "musb_dma.h"
0044 
0045 #include "musb_io.h"
0046 
0047 #include "musb_gadget.h"
0048 #include <linux/usb/hcd.h>
0049 #include "musb_host.h"
0050 
0051 /* NOTE:  otg and peripheral-only state machines start at B_IDLE.
0052  * OTG or host-only go to A_IDLE when ID is sensed.
0053  */
0054 #define is_peripheral_active(m)     (!(m)->is_host)
0055 #define is_host_active(m)       ((m)->is_host)
0056 
0057 /****************************** CONSTANTS ********************************/
0058 
0059 #ifndef MUSB_C_NUM_EPS
0060 #define MUSB_C_NUM_EPS ((u8)16)
0061 #endif
0062 
0063 #ifndef MUSB_MAX_END0_PACKET
0064 #define MUSB_MAX_END0_PACKET ((u16)MUSB_EP0_FIFOSIZE)
0065 #endif
0066 
0067 /* host side ep0 states */
0068 enum musb_h_ep0_state {
0069     MUSB_EP0_IDLE,
0070     MUSB_EP0_START,         /* expect ack of setup */
0071     MUSB_EP0_IN,            /* expect IN DATA */
0072     MUSB_EP0_OUT,           /* expect ack of OUT DATA */
0073     MUSB_EP0_STATUS,        /* expect ack of STATUS */
0074 } __attribute__ ((packed));
0075 
0076 /* peripheral side ep0 states */
0077 enum musb_g_ep0_state {
0078     MUSB_EP0_STAGE_IDLE,        /* idle, waiting for SETUP */
0079     MUSB_EP0_STAGE_SETUP,       /* received SETUP */
0080     MUSB_EP0_STAGE_TX,      /* IN data */
0081     MUSB_EP0_STAGE_RX,      /* OUT data */
0082     MUSB_EP0_STAGE_STATUSIN,    /* (after OUT data) */
0083     MUSB_EP0_STAGE_STATUSOUT,   /* (after IN data) */
0084     MUSB_EP0_STAGE_ACKWAIT,     /* after zlp, before statusin */
0085 } __attribute__ ((packed));
0086 
0087 /*
0088  * OTG protocol constants.  See USB OTG 1.3 spec,
0089  * sections 5.5 "Device Timings" and 6.6.5 "Timers".
0090  */
0091 #define OTG_TIME_A_WAIT_VRISE   100     /* msec (max) */
0092 #define OTG_TIME_A_WAIT_BCON    1100        /* min 1 second */
0093 #define OTG_TIME_A_AIDL_BDIS    200     /* min 200 msec */
0094 #define OTG_TIME_B_ASE0_BRST    100     /* min 3.125 ms */
0095 
0096 /****************************** FUNCTIONS ********************************/
0097 
0098 #define MUSB_HST_MODE(_musb)\
0099     { (_musb)->is_host = true; }
0100 #define MUSB_DEV_MODE(_musb) \
0101     { (_musb)->is_host = false; }
0102 
0103 #define test_devctl_hst_mode(_x) \
0104     (musb_readb((_x)->mregs, MUSB_DEVCTL)&MUSB_DEVCTL_HM)
0105 
0106 #define MUSB_MODE(musb) ((musb)->is_host ? "Host" : "Peripheral")
0107 
0108 /******************************** TYPES *************************************/
0109 
0110 struct musb_io;
0111 
0112 /**
0113  * struct musb_platform_ops - Operations passed to musb_core by HW glue layer
0114  * @quirks: flags for platform specific quirks
0115  * @enable: enable device
0116  * @disable:    disable device
0117  * @ep_offset:  returns the end point offset
0118  * @ep_select:  selects the specified end point
0119  * @fifo_mode:  sets the fifo mode
0120  * @fifo_offset: returns the fifo offset
0121  * @readb:  read 8 bits
0122  * @writeb: write 8 bits
0123  * @clearb: could be clear-on-readb or W1C
0124  * @readw:  read 16 bits
0125  * @writew: write 16 bits
0126  * @clearw: could be clear-on-readw or W1C
0127  * @read_fifo:  reads the fifo
0128  * @write_fifo: writes to fifo
0129  * @get_toggle: platform specific get toggle function
0130  * @set_toggle: platform specific set toggle function
0131  * @dma_init:   platform specific dma init function
0132  * @dma_exit:   platform specific dma exit function
0133  * @init:   turns on clocks, sets up platform-specific registers, etc
0134  * @exit:   undoes @init
0135  * @set_mode:   forcefully changes operating mode
0136  * @try_idle:   tries to idle the IP
0137  * @recover:    platform-specific babble recovery
0138  * @vbus_status: returns vbus status if possible
0139  * @set_vbus:   forces vbus status
0140  * @pre_root_reset_end: called before the root usb port reset flag gets cleared
0141  * @post_root_reset_end: called after the root usb port reset flag gets cleared
0142  * @phy_callback: optional callback function for the phy to call
0143  */
0144 struct musb_platform_ops {
0145 
0146 #define MUSB_G_NO_SKB_RESERVE   BIT(9)
0147 #define MUSB_DA8XX      BIT(8)
0148 #define MUSB_PRESERVE_SESSION   BIT(7)
0149 #define MUSB_DMA_UX500      BIT(6)
0150 #define MUSB_DMA_CPPI41     BIT(5)
0151 #define MUSB_DMA_CPPI       BIT(4)
0152 #define MUSB_DMA_TUSB_OMAP  BIT(3)
0153 #define MUSB_DMA_INVENTRA   BIT(2)
0154 #define MUSB_IN_TUSB        BIT(1)
0155 #define MUSB_INDEXED_EP     BIT(0)
0156     u32 quirks;
0157 
0158     int (*init)(struct musb *musb);
0159     int (*exit)(struct musb *musb);
0160 
0161     void    (*enable)(struct musb *musb);
0162     void    (*disable)(struct musb *musb);
0163 
0164     u32 (*ep_offset)(u8 epnum, u16 offset);
0165     void    (*ep_select)(void __iomem *mbase, u8 epnum);
0166     u16 fifo_mode;
0167     u32 (*fifo_offset)(u8 epnum);
0168     u32 (*busctl_offset)(u8 epnum, u16 offset);
0169     u8  (*readb)(void __iomem *addr, u32 offset);
0170     void    (*writeb)(void __iomem *addr, u32 offset, u8 data);
0171     u8  (*clearb)(void __iomem *addr, u32 offset);
0172     u16 (*readw)(void __iomem *addr, u32 offset);
0173     void    (*writew)(void __iomem *addr, u32 offset, u16 data);
0174     u16 (*clearw)(void __iomem *addr, u32 offset);
0175     void    (*read_fifo)(struct musb_hw_ep *hw_ep, u16 len, u8 *buf);
0176     void    (*write_fifo)(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf);
0177     u16 (*get_toggle)(struct musb_qh *qh, int is_out);
0178     u16 (*set_toggle)(struct musb_qh *qh, int is_out, struct urb *urb);
0179     struct dma_controller *
0180         (*dma_init) (struct musb *musb, void __iomem *base);
0181     void    (*dma_exit)(struct dma_controller *c);
0182     int (*set_mode)(struct musb *musb, u8 mode);
0183     void    (*try_idle)(struct musb *musb, unsigned long timeout);
0184     int (*recover)(struct musb *musb);
0185 
0186     int (*vbus_status)(struct musb *musb);
0187     void    (*set_vbus)(struct musb *musb, int on);
0188 
0189     void    (*pre_root_reset_end)(struct musb *musb);
0190     void    (*post_root_reset_end)(struct musb *musb);
0191     int (*phy_callback)(enum musb_vbus_id_status status);
0192     void    (*clear_ep_rxintr)(struct musb *musb, int epnum);
0193 };
0194 
0195 /*
0196  * struct musb_hw_ep - endpoint hardware (bidirectional)
0197  *
0198  * Ordered slightly for better cacheline locality.
0199  */
0200 struct musb_hw_ep {
0201     struct musb     *musb;
0202     void __iomem        *fifo;
0203     void __iomem        *regs;
0204 
0205 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
0206     void __iomem        *conf;
0207 #endif
0208 
0209     /* index in musb->endpoints[]  */
0210     u8          epnum;
0211 
0212     /* hardware configuration, possibly dynamic */
0213     bool            is_shared_fifo;
0214     bool            tx_double_buffered;
0215     bool            rx_double_buffered;
0216     u16         max_packet_sz_tx;
0217     u16         max_packet_sz_rx;
0218 
0219     struct dma_channel  *tx_channel;
0220     struct dma_channel  *rx_channel;
0221 
0222 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
0223     /* TUSB has "asynchronous" and "synchronous" dma modes */
0224     dma_addr_t      fifo_async;
0225     dma_addr_t      fifo_sync;
0226     void __iomem        *fifo_sync_va;
0227 #endif
0228 
0229     /* currently scheduled peripheral endpoint */
0230     struct musb_qh      *in_qh;
0231     struct musb_qh      *out_qh;
0232 
0233     u8          rx_reinit;
0234     u8          tx_reinit;
0235 
0236     /* peripheral side */
0237     struct musb_ep      ep_in;          /* TX */
0238     struct musb_ep      ep_out;         /* RX */
0239 };
0240 
0241 static inline struct musb_request *next_in_request(struct musb_hw_ep *hw_ep)
0242 {
0243     return next_request(&hw_ep->ep_in);
0244 }
0245 
0246 static inline struct musb_request *next_out_request(struct musb_hw_ep *hw_ep)
0247 {
0248     return next_request(&hw_ep->ep_out);
0249 }
0250 
0251 struct musb_csr_regs {
0252     /* FIFO registers */
0253     u16 txmaxp, txcsr, rxmaxp, rxcsr;
0254     u16 rxfifoadd, txfifoadd;
0255     u8 txtype, txinterval, rxtype, rxinterval;
0256     u8 rxfifosz, txfifosz;
0257     u8 txfunaddr, txhubaddr, txhubport;
0258     u8 rxfunaddr, rxhubaddr, rxhubport;
0259 };
0260 
0261 struct musb_context_registers {
0262 
0263     u8 power;
0264     u8 intrusbe;
0265     u16 frame;
0266     u8 index, testmode;
0267 
0268     u8 devctl, busctl, misc;
0269     u32 otg_interfsel;
0270 
0271     struct musb_csr_regs index_regs[MUSB_C_NUM_EPS];
0272 };
0273 
0274 /*
0275  * struct musb - Driver instance data.
0276  */
0277 struct musb {
0278     /* device lock */
0279     spinlock_t      lock;
0280     spinlock_t      list_lock;  /* resume work list lock */
0281 
0282     struct musb_io      io;
0283     const struct musb_platform_ops *ops;
0284     struct musb_context_registers context;
0285 
0286     irqreturn_t     (*isr)(int, void *);
0287     struct delayed_work irq_work;
0288     struct delayed_work deassert_reset_work;
0289     struct delayed_work finish_resume_work;
0290     struct delayed_work gadget_work;
0291     u16         hwvers;
0292 
0293     u16         intrrxe;
0294     u16         intrtxe;
0295 /* this hub status bit is reserved by USB 2.0 and not seen by usbcore */
0296 #define MUSB_PORT_STAT_RESUME   (1 << 31)
0297 
0298     u32         port1_status;
0299 
0300     unsigned long       rh_timer;
0301 
0302     enum musb_h_ep0_state   ep0_stage;
0303 
0304     /* bulk traffic normally dedicates endpoint hardware, and each
0305      * direction has its own ring of host side endpoints.
0306      * we try to progress the transfer at the head of each endpoint's
0307      * queue until it completes or NAKs too much; then we try the next
0308      * endpoint.
0309      */
0310     struct musb_hw_ep   *bulk_ep;
0311 
0312     struct list_head    control;    /* of musb_qh */
0313     struct list_head    in_bulk;    /* of musb_qh */
0314     struct list_head    out_bulk;   /* of musb_qh */
0315     struct list_head    pending_list;   /* pending work list */
0316 
0317     struct timer_list   otg_timer;
0318     struct timer_list   dev_timer;
0319     struct notifier_block   nb;
0320 
0321     struct dma_controller   *dma_controller;
0322 
0323     struct device       *controller;
0324     void __iomem        *ctrl_base;
0325     void __iomem        *mregs;
0326 
0327 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
0328     dma_addr_t      async;
0329     dma_addr_t      sync;
0330     void __iomem        *sync_va;
0331     u8          tusb_revision;
0332 #endif
0333 
0334     /* passed down from chip/board specific irq handlers */
0335     u8          int_usb;
0336     u16         int_rx;
0337     u16         int_tx;
0338 
0339     struct usb_phy      *xceiv;
0340     struct phy      *phy;
0341 
0342     int nIrq;
0343     unsigned        irq_wake:1;
0344 
0345     struct musb_hw_ep    endpoints[MUSB_C_NUM_EPS];
0346 #define control_ep      endpoints
0347 
0348 #define VBUSERR_RETRY_COUNT 3
0349     u16         vbuserr_retry;
0350     u16 epmask;
0351     u8 nr_endpoints;
0352 
0353     int         (*board_set_power)(int state);
0354 
0355     u8          min_power;  /* vbus for periph, in mA/2 */
0356 
0357     enum musb_mode      port_mode;
0358     bool            session;
0359     unsigned long       quirk_retries;
0360     bool            is_host;
0361 
0362     int         a_wait_bcon;    /* VBUS timeout in msecs */
0363     unsigned long       idle_timeout;   /* Next timeout in jiffies */
0364 
0365     unsigned        is_initialized:1;
0366     unsigned        is_runtime_suspended:1;
0367 
0368     /* active means connected and not suspended */
0369     unsigned        is_active:1;
0370 
0371     unsigned is_multipoint:1;
0372 
0373     unsigned        hb_iso_rx:1;    /* high bandwidth iso rx? */
0374     unsigned        hb_iso_tx:1;    /* high bandwidth iso tx? */
0375     unsigned        dyn_fifo:1; /* dynamic FIFO supported? */
0376 
0377     unsigned        bulk_split:1;
0378 #define can_bulk_split(musb, type) \
0379     (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_split)
0380 
0381     unsigned        bulk_combine:1;
0382 #define can_bulk_combine(musb, type) \
0383     (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_combine)
0384 
0385     /* is_suspended means USB B_PERIPHERAL suspend */
0386     unsigned        is_suspended:1;
0387 
0388     /* may_wakeup means remote wakeup is enabled */
0389     unsigned        may_wakeup:1;
0390 
0391     /* is_self_powered is reported in device status and the
0392      * config descriptor.  is_bus_powered means B_PERIPHERAL
0393      * draws some VBUS current; both can be true.
0394      */
0395     unsigned        is_self_powered:1;
0396     unsigned        is_bus_powered:1;
0397 
0398     unsigned        set_address:1;
0399     unsigned        test_mode:1;
0400     unsigned        softconnect:1;
0401 
0402     unsigned        flush_irq_work:1;
0403 
0404     u8          address;
0405     u8          test_mode_nr;
0406     u16         ackpend;        /* ep0 */
0407     enum musb_g_ep0_state   ep0_state;
0408     struct usb_gadget   g;          /* the gadget */
0409     struct usb_gadget_driver *gadget_driver;    /* its driver */
0410     struct usb_hcd      *hcd;           /* the usb hcd */
0411 
0412     const struct musb_hdrc_config *config;
0413 
0414     int         xceiv_old_state;
0415 #ifdef CONFIG_DEBUG_FS
0416     struct dentry       *debugfs_root;
0417 #endif
0418 };
0419 
0420 /* This must be included after struct musb is defined */
0421 #include "musb_regs.h"
0422 
0423 static inline struct musb *gadget_to_musb(struct usb_gadget *g)
0424 {
0425     return container_of(g, struct musb, g);
0426 }
0427 
0428 static inline char *musb_ep_xfertype_string(u8 type)
0429 {
0430     char *s;
0431 
0432     switch (type) {
0433     case USB_ENDPOINT_XFER_CONTROL:
0434         s = "ctrl";
0435         break;
0436     case USB_ENDPOINT_XFER_ISOC:
0437         s = "iso";
0438         break;
0439     case USB_ENDPOINT_XFER_BULK:
0440         s = "bulk";
0441         break;
0442     case USB_ENDPOINT_XFER_INT:
0443         s = "int";
0444         break;
0445     default:
0446         s = "";
0447         break;
0448     }
0449     return s;
0450 }
0451 
0452 static inline int musb_read_fifosize(struct musb *musb,
0453         struct musb_hw_ep *hw_ep, u8 epnum)
0454 {
0455     void __iomem *mbase = musb->mregs;
0456     u8 reg = 0;
0457 
0458     /* read from core using indexed model */
0459     reg = musb_readb(mbase, musb->io.ep_offset(epnum, MUSB_FIFOSIZE));
0460     /* 0's returned when no more endpoints */
0461     if (!reg)
0462         return -ENODEV;
0463 
0464     musb->nr_endpoints++;
0465     musb->epmask |= (1 << epnum);
0466 
0467     hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
0468 
0469     /* shared TX/RX FIFO? */
0470     if ((reg & 0xf0) == 0xf0) {
0471         hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
0472         hw_ep->is_shared_fifo = true;
0473         return 0;
0474     } else {
0475         hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
0476         hw_ep->is_shared_fifo = false;
0477     }
0478 
0479     return 0;
0480 }
0481 
0482 static inline void musb_configure_ep0(struct musb *musb)
0483 {
0484     musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
0485     musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
0486     musb->endpoints[0].is_shared_fifo = true;
0487 }
0488 
0489 /***************************** Glue it together *****************************/
0490 
0491 extern const char musb_driver_name[];
0492 
0493 extern void musb_stop(struct musb *musb);
0494 extern void musb_start(struct musb *musb);
0495 
0496 extern void musb_write_fifo(struct musb_hw_ep *ep, u16 len, const u8 *src);
0497 extern void musb_read_fifo(struct musb_hw_ep *ep, u16 len, u8 *dst);
0498 
0499 extern int musb_set_host(struct musb *musb);
0500 extern int musb_set_peripheral(struct musb *musb);
0501 
0502 extern void musb_load_testpacket(struct musb *);
0503 
0504 extern irqreturn_t musb_interrupt(struct musb *);
0505 
0506 extern void musb_hnp_stop(struct musb *musb);
0507 
0508 int musb_queue_resume_work(struct musb *musb,
0509                int (*callback)(struct musb *musb, void *data),
0510                void *data);
0511 
0512 static inline void musb_platform_set_vbus(struct musb *musb, int is_on)
0513 {
0514     if (musb->ops->set_vbus)
0515         musb->ops->set_vbus(musb, is_on);
0516 }
0517 
0518 static inline void musb_platform_enable(struct musb *musb)
0519 {
0520     if (musb->ops->enable)
0521         musb->ops->enable(musb);
0522 }
0523 
0524 static inline void musb_platform_disable(struct musb *musb)
0525 {
0526     if (musb->ops->disable)
0527         musb->ops->disable(musb);
0528 }
0529 
0530 static inline int musb_platform_set_mode(struct musb *musb, u8 mode)
0531 {
0532     if (!musb->ops->set_mode)
0533         return 0;
0534 
0535     return musb->ops->set_mode(musb, mode);
0536 }
0537 
0538 static inline void musb_platform_try_idle(struct musb *musb,
0539         unsigned long timeout)
0540 {
0541     if (musb->ops->try_idle)
0542         musb->ops->try_idle(musb, timeout);
0543 }
0544 
0545 static inline int  musb_platform_recover(struct musb *musb)
0546 {
0547     if (!musb->ops->recover)
0548         return 0;
0549 
0550     return musb->ops->recover(musb);
0551 }
0552 
0553 static inline int musb_platform_get_vbus_status(struct musb *musb)
0554 {
0555     if (!musb->ops->vbus_status)
0556         return -EINVAL;
0557 
0558     return musb->ops->vbus_status(musb);
0559 }
0560 
0561 static inline int musb_platform_init(struct musb *musb)
0562 {
0563     if (!musb->ops->init)
0564         return -EINVAL;
0565 
0566     return musb->ops->init(musb);
0567 }
0568 
0569 static inline int musb_platform_exit(struct musb *musb)
0570 {
0571     if (!musb->ops->exit)
0572         return -EINVAL;
0573 
0574     return musb->ops->exit(musb);
0575 }
0576 
0577 static inline void musb_platform_pre_root_reset_end(struct musb *musb)
0578 {
0579     if (musb->ops->pre_root_reset_end)
0580         musb->ops->pre_root_reset_end(musb);
0581 }
0582 
0583 static inline void musb_platform_post_root_reset_end(struct musb *musb)
0584 {
0585     if (musb->ops->post_root_reset_end)
0586         musb->ops->post_root_reset_end(musb);
0587 }
0588 
0589 static inline void musb_platform_clear_ep_rxintr(struct musb *musb, int epnum)
0590 {
0591     if (musb->ops->clear_ep_rxintr)
0592         musb->ops->clear_ep_rxintr(musb, epnum);
0593 }
0594 
0595 /*
0596  * gets the "dr_mode" property from DT and converts it into musb_mode
0597  * if the property is not found or not recognized returns MUSB_OTG
0598  */
0599 extern enum musb_mode musb_get_mode(struct device *dev);
0600 
0601 #endif  /* __MUSB_CORE_H__ */
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