usb/musb/mpfs.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PolarFire SoC (MPFS) MUSB Glue Layer
0004  *
0005  * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
0006  * Based on {omap2430,tusb6010,ux500}.c
0007  *
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/dma-mapping.h>
0012 #include <linux/err.h>
0013 #include <linux/io.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/usb/usb_phy_generic.h>
0018 #include "musb_core.h"
0019 #include "musb_dma.h"
0020
0021 #define MPFS_MUSB_MAX_EP_NUM    8
0022 #define MPFS_MUSB_RAM_BITS  12
0023
0024 struct mpfs_glue {
0025     struct device *dev;
0026     struct platform_device *musb;
0027     struct platform_device *phy;
0028     struct clk *clk;
0029 };
0030
0031 static struct musb_fifo_cfg mpfs_musb_mode_cfg[] = {
0032     { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
0033     { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
0034     { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
0035     { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
0036     { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
0037     { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
0038     { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 1024, },
0039     { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 4096, },
0040 };
0041
0042 static const struct musb_hdrc_config mpfs_musb_hdrc_config = {
0043     .fifo_cfg = mpfs_musb_mode_cfg,
0044     .fifo_cfg_size = ARRAY_SIZE(mpfs_musb_mode_cfg),
0045     .multipoint = true,
0046     .dyn_fifo = true,
0047     .num_eps = MPFS_MUSB_MAX_EP_NUM,
0048     .ram_bits = MPFS_MUSB_RAM_BITS,
0049 };
0050
0051 static irqreturn_t mpfs_musb_interrupt(int irq, void *__hci)
0052 {
0053     unsigned long flags;
0054     irqreturn_t ret = IRQ_NONE;
0055     struct musb *musb = __hci;
0056
0057     spin_lock_irqsave(&musb->lock, flags);
0058
0059     musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
0060     musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
0061     musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
0062
0063     if (musb->int_usb || musb->int_tx || musb->int_rx) {
0064         musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
0065         musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
0066         musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
0067         ret = musb_interrupt(musb);
0068     }
0069
0070     spin_unlock_irqrestore(&musb->lock, flags);
0071
0072     return ret;
0073 }
0074
0075 static void mpfs_musb_set_vbus(struct musb *musb, int is_on)
0076 {
0077     u8 devctl;
0078
0079     /*
0080      * HDRC controls CPEN, but beware current surges during device
0081      * connect.  They can trigger transient overcurrent conditions
0082      * that must be ignored.
0083      */
0084     devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
0085
0086     if (is_on) {
0087         musb->is_active = 1;
0088         musb->xceiv->otg->default_a = 1;
0089         musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
0090         devctl |= MUSB_DEVCTL_SESSION;
0091         MUSB_HST_MODE(musb);
0092     } else {
0093         musb->is_active = 0;
0094
0095         /*
0096          * NOTE:  skipping A_WAIT_VFALL -> A_IDLE and
0097          * jumping right to B_IDLE...
0098          */
0099         musb->xceiv->otg->default_a = 0;
0100         musb->xceiv->otg->state = OTG_STATE_B_IDLE;
0101         devctl &= ~MUSB_DEVCTL_SESSION;
0102
0103         MUSB_DEV_MODE(musb);
0104     }
0105
0106     musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
0107
0108     dev_dbg(musb->controller, "VBUS %s, devctl %02x\n",
0109         usb_otg_state_string(musb->xceiv->otg->state),
0110         musb_readb(musb->mregs, MUSB_DEVCTL));
0111 }
0112
0113 static int mpfs_musb_init(struct musb *musb)
0114 {
0115     struct device *dev = musb->controller;
0116
0117     musb->xceiv = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
0118     if (IS_ERR(musb->xceiv)) {
0119         dev_err(dev, "HS UDC: no transceiver configured\n");
0120         return PTR_ERR(musb->xceiv);
0121     }
0122
0123     musb->dyn_fifo = true;
0124     musb->isr = mpfs_musb_interrupt;
0125
0126     musb_platform_set_vbus(musb, 1);
0127
0128     return 0;
0129 }
0130
0131 static const struct musb_platform_ops mpfs_ops = {
0132     .quirks     = MUSB_DMA_INVENTRA,
0133     .init       = mpfs_musb_init,
0134     .fifo_mode  = 2,
0135 #ifdef CONFIG_USB_INVENTRA_DMA
0136     .dma_init   = musbhs_dma_controller_create,
0137     .dma_exit   = musbhs_dma_controller_destroy,
0138 #endif
0139     .set_vbus   = mpfs_musb_set_vbus
0140 };
0141
0142 static int mpfs_probe(struct platform_device *pdev)
0143 {
0144     struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
0145     struct mpfs_glue *glue;
0146     struct platform_device *musb_pdev;
0147     struct device *dev = &pdev->dev;
0148     struct clk *clk;
0149     int ret;
0150
0151     glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
0152     if (!glue)
0153         return -ENOMEM;
0154
0155     musb_pdev = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
0156     if (!musb_pdev) {
0157         dev_err(dev, "failed to allocate musb device\n");
0158         return -ENOMEM;
0159     }
0160
0161     clk = devm_clk_get(&pdev->dev, NULL);
0162     if (IS_ERR(clk)) {
0163         dev_err(&pdev->dev, "failed to get clock\n");
0164         ret = PTR_ERR(clk);
0165         goto err_phy_release;
0166     }
0167
0168     ret = clk_prepare_enable(clk);
0169     if (ret) {
0170         dev_err(&pdev->dev, "failed to enable clock\n");
0171         goto err_phy_release;
0172     }
0173
0174     musb_pdev->dev.parent = dev;
0175     musb_pdev->dev.coherent_dma_mask = DMA_BIT_MASK(39);
0176     musb_pdev->dev.dma_mask = &musb_pdev->dev.coherent_dma_mask;
0177     device_set_of_node_from_dev(&musb_pdev->dev, dev);
0178
0179     glue->dev = dev;
0180     glue->musb = musb_pdev;
0181     glue->clk = clk;
0182
0183     pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
0184     if (!pdata) {
0185         ret = -ENOMEM;
0186         goto err_clk_disable;
0187     }
0188
0189     pdata->config = &mpfs_musb_hdrc_config;
0190     pdata->platform_ops = &mpfs_ops;
0191
0192     pdata->mode = usb_get_dr_mode(dev);
0193     if (pdata->mode == USB_DR_MODE_UNKNOWN) {
0194         dev_info(dev, "No dr_mode property found, defaulting to otg\n");
0195         pdata->mode = USB_DR_MODE_OTG;
0196     }
0197
0198     glue->phy = usb_phy_generic_register();
0199     if (IS_ERR(glue->phy)) {
0200         dev_err(dev, "failed to register usb-phy %ld\n",
0201             PTR_ERR(glue->phy));
0202         ret = PTR_ERR(glue->phy);
0203         goto err_clk_disable;
0204     }
0205
0206     platform_set_drvdata(pdev, glue);
0207
0208     ret = platform_device_add_resources(musb_pdev, pdev->resource, pdev->num_resources);
0209     if (ret) {
0210         dev_err(dev, "failed to add resources\n");
0211         goto err_clk_disable;
0212     }
0213
0214     ret = platform_device_add_data(musb_pdev, pdata, sizeof(*pdata));
0215     if (ret) {
0216         dev_err(dev, "failed to add platform_data\n");
0217         goto err_clk_disable;
0218     }
0219
0220     ret = platform_device_add(musb_pdev);
0221     if (ret) {
0222         dev_err(dev, "failed to register musb device\n");
0223         goto err_clk_disable;
0224     }
0225
0226     dev_info(&pdev->dev, "Registered MPFS MUSB driver\n");
0227     return 0;
0228
0229 err_clk_disable:
0230     clk_disable_unprepare(clk);
0231
0232 err_phy_release:
0233     usb_phy_generic_unregister(glue->phy);
0234     platform_device_put(musb_pdev);
0235     return ret;
0236 }
0237
0238 static int mpfs_remove(struct platform_device *pdev)
0239 {
0240     struct mpfs_glue *glue = platform_get_drvdata(pdev);
0241
0242     clk_disable_unprepare(glue->clk);
0243     platform_device_unregister(glue->musb);
0244     usb_phy_generic_unregister(pdev);
0245
0246     return 0;
0247 }
0248
0249 #ifdef CONFIG_OF
0250 static const struct of_device_id mpfs_id_table[] = {
0251     { .compatible = "microchip,mpfs-musb" },
0252     { }
0253 };
0254 MODULE_DEVICE_TABLE(of, mpfs_id_table);
0255 #endif
0256
0257 static struct platform_driver mpfs_musb_driver = {
0258     .probe = mpfs_probe,
0259     .remove = mpfs_remove,
0260     .driver = {
0261         .name = "mpfs-musb",
0262         .of_match_table = of_match_ptr(mpfs_id_table)
0263     },
0264 };
0265
0266 module_platform_driver(mpfs_musb_driver);
0267
0268 MODULE_DESCRIPTION("PolarFire SoC MUSB Glue Layer");
0269 MODULE_LICENSE("GPL");