usb/musb/cppi_dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (C) 2005-2006 by Texas Instruments */
0003
0004 #ifndef _CPPI_DMA_H_
0005 #define _CPPI_DMA_H_
0006
0007 #include <linux/slab.h>
0008 #include <linux/list.h>
0009 #include <linux/errno.h>
0010 #include <linux/dmapool.h>
0011 #include <linux/dmaengine.h>
0012
0013 #include "musb_core.h"
0014 #include "musb_dma.h"
0015
0016 /* CPPI RX/TX state RAM */
0017
0018 struct cppi_tx_stateram {
0019     u32 tx_head;            /* "DMA packet" head descriptor */
0020     u32 tx_buf;
0021     u32 tx_current;         /* current descriptor */
0022     u32 tx_buf_current;
0023     u32 tx_info;            /* flags, remaining buflen */
0024     u32 tx_rem_len;
0025     u32 tx_dummy;           /* unused */
0026     u32 tx_complete;
0027 };
0028
0029 struct cppi_rx_stateram {
0030     u32 rx_skipbytes;
0031     u32 rx_head;
0032     u32 rx_sop;         /* "DMA packet" head descriptor */
0033     u32 rx_current;         /* current descriptor */
0034     u32 rx_buf_current;
0035     u32 rx_len_len;
0036     u32 rx_cnt_cnt;
0037     u32 rx_complete;
0038 };
0039
0040 /* hw_options bits in CPPI buffer descriptors */
0041 #define CPPI_SOP_SET    ((u32)(1 << 31))
0042 #define CPPI_EOP_SET    ((u32)(1 << 30))
0043 #define CPPI_OWN_SET    ((u32)(1 << 29))    /* owned by cppi */
0044 #define CPPI_EOQ_MASK   ((u32)(1 << 28))
0045 #define CPPI_ZERO_SET   ((u32)(1 << 23))    /* rx saw zlp; tx issues one */
0046 #define CPPI_RXABT_MASK ((u32)(1 << 19))    /* need more rx buffers */
0047
0048 #define CPPI_RECV_PKTLEN_MASK 0xFFFF
0049 #define CPPI_BUFFER_LEN_MASK 0xFFFF
0050
0051 #define CPPI_TEAR_READY ((u32)(1 << 31))
0052
0053 /* CPPI data structure definitions */
0054
0055 #define CPPI_DESCRIPTOR_ALIGN   16  /* bytes; 5-dec docs say 4-byte align */
0056
0057 struct cppi_descriptor {
0058     /* hardware overlay */
0059     u32     hw_next;    /* next buffer descriptor Pointer */
0060     u32     hw_bufp;    /* i/o buffer pointer */
0061     u32     hw_off_len; /* buffer_offset16, buffer_length16 */
0062     u32     hw_options; /* flags:  SOP, EOP etc*/
0063
0064     struct cppi_descriptor *next;
0065     dma_addr_t  dma;        /* address of this descriptor */
0066     u32     buflen;     /* for RX: original buffer length */
0067 } __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN)));
0068
0069
0070 struct cppi;
0071
0072 /* CPPI  Channel Control structure */
0073 struct cppi_channel {
0074     struct dma_channel  channel;
0075
0076     /* back pointer to the DMA controller structure */
0077     struct cppi     *controller;
0078
0079     /* which direction of which endpoint? */
0080     struct musb_hw_ep   *hw_ep;
0081     bool            transmit;
0082     u8          index;
0083
0084     /* DMA modes:  RNDIS or "transparent" */
0085     u8          is_rndis;
0086
0087     /* book keeping for current transfer request */
0088     dma_addr_t      buf_dma;
0089     u32         buf_len;
0090     u32         maxpacket;
0091     u32         offset;     /* dma requested */
0092
0093     void __iomem        *state_ram; /* CPPI state */
0094
0095     struct cppi_descriptor  *freelist;
0096
0097     /* BD management fields */
0098     struct cppi_descriptor  *head;
0099     struct cppi_descriptor  *tail;
0100     struct cppi_descriptor  *last_processed;
0101
0102     /* use tx_complete in host role to track endpoints waiting for
0103      * FIFONOTEMPTY to clear.
0104      */
0105     struct list_head    tx_complete;
0106 };
0107
0108 /* CPPI DMA controller object */
0109 struct cppi {
0110     struct dma_controller       controller;
0111     void __iomem            *mregs;     /* Mentor regs */
0112     void __iomem            *tibase;    /* TI/CPPI regs */
0113
0114     int             irq;
0115
0116     struct cppi_channel     tx[4];
0117     struct cppi_channel     rx[4];
0118
0119     struct dma_pool         *pool;
0120
0121     struct list_head        tx_complete;
0122 };
0123
0124 /* CPPI IRQ handler */
0125 extern irqreturn_t cppi_interrupt(int, void *);
0126
0127 struct cppi41_dma_channel {
0128     struct dma_channel channel;
0129     struct cppi41_dma_controller *controller;
0130     struct musb_hw_ep *hw_ep;
0131     struct dma_chan *dc;
0132     dma_cookie_t cookie;
0133     u8 port_num;
0134     u8 is_tx;
0135     u8 is_allocated;
0136     u8 usb_toggle;
0137
0138     dma_addr_t buf_addr;
0139     u32 total_len;
0140     u32 prog_len;
0141     u32 transferred;
0142     u32 packet_sz;
0143     struct list_head tx_check;
0144     int tx_zlp;
0145 };
0146
0147 #endif              /* end of ifndef _CPPI_DMA_H_ */