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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2016 MediaTek Inc.
0004  *
0005  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
0006  */
0007 
0008 #include <linux/dma-mapping.h>
0009 #include <linux/iopoll.h>
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_irq.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pm_wakeirq.h>
0016 #include <linux/reset.h>
0017 
0018 #include "mtu3.h"
0019 #include "mtu3_dr.h"
0020 #include "mtu3_debug.h"
0021 
0022 /* u2-port0 should be powered on and enabled; */
0023 int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
0024 {
0025     void __iomem *ibase = ssusb->ippc_base;
0026     u32 value, check_val;
0027     int ret;
0028 
0029     check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
0030             SSUSB_REF_RST_B_STS;
0031 
0032     ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
0033             (check_val == (value & check_val)), 100, 20000);
0034     if (ret) {
0035         dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
0036         return ret;
0037     }
0038 
0039     ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
0040             (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
0041     if (ret) {
0042         dev_err(ssusb->dev, "mac2 clock is not stable\n");
0043         return ret;
0044     }
0045 
0046     return 0;
0047 }
0048 
0049 static int wait_for_ip_sleep(struct ssusb_mtk *ssusb)
0050 {
0051     bool sleep_check = true;
0052     u32 value;
0053     int ret;
0054 
0055     if (!ssusb->is_host)
0056         sleep_check = ssusb_gadget_ip_sleep_check(ssusb);
0057 
0058     if (!sleep_check)
0059         return 0;
0060 
0061     /* wait for ip enter sleep mode */
0062     ret = readl_poll_timeout(ssusb->ippc_base + U3D_SSUSB_IP_PW_STS1, value,
0063                  (value & SSUSB_IP_SLEEP_STS), 100, 100000);
0064     if (ret) {
0065         dev_err(ssusb->dev, "ip sleep failed!!!\n");
0066         ret = -EBUSY;
0067     } else {
0068         /* workaround: avoid wrong wakeup signal latch for some soc */
0069         usleep_range(100, 200);
0070     }
0071 
0072     return ret;
0073 }
0074 
0075 static int ssusb_phy_init(struct ssusb_mtk *ssusb)
0076 {
0077     int i;
0078     int ret;
0079 
0080     for (i = 0; i < ssusb->num_phys; i++) {
0081         ret = phy_init(ssusb->phys[i]);
0082         if (ret)
0083             goto exit_phy;
0084     }
0085     return 0;
0086 
0087 exit_phy:
0088     for (; i > 0; i--)
0089         phy_exit(ssusb->phys[i - 1]);
0090 
0091     return ret;
0092 }
0093 
0094 static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
0095 {
0096     int i;
0097 
0098     for (i = 0; i < ssusb->num_phys; i++)
0099         phy_exit(ssusb->phys[i]);
0100 
0101     return 0;
0102 }
0103 
0104 static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
0105 {
0106     int i;
0107     int ret;
0108 
0109     for (i = 0; i < ssusb->num_phys; i++) {
0110         ret = phy_power_on(ssusb->phys[i]);
0111         if (ret)
0112             goto power_off_phy;
0113     }
0114     return 0;
0115 
0116 power_off_phy:
0117     for (; i > 0; i--)
0118         phy_power_off(ssusb->phys[i - 1]);
0119 
0120     return ret;
0121 }
0122 
0123 static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
0124 {
0125     unsigned int i;
0126 
0127     for (i = 0; i < ssusb->num_phys; i++)
0128         phy_power_off(ssusb->phys[i]);
0129 }
0130 
0131 static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
0132 {
0133     int ret = 0;
0134 
0135     ret = regulator_enable(ssusb->vusb33);
0136     if (ret) {
0137         dev_err(ssusb->dev, "failed to enable vusb33\n");
0138         goto vusb33_err;
0139     }
0140 
0141     ret = clk_bulk_prepare_enable(BULK_CLKS_CNT, ssusb->clks);
0142     if (ret)
0143         goto clks_err;
0144 
0145     ret = ssusb_phy_init(ssusb);
0146     if (ret) {
0147         dev_err(ssusb->dev, "failed to init phy\n");
0148         goto phy_init_err;
0149     }
0150 
0151     ret = ssusb_phy_power_on(ssusb);
0152     if (ret) {
0153         dev_err(ssusb->dev, "failed to power on phy\n");
0154         goto phy_err;
0155     }
0156 
0157     return 0;
0158 
0159 phy_err:
0160     ssusb_phy_exit(ssusb);
0161 phy_init_err:
0162     clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
0163 clks_err:
0164     regulator_disable(ssusb->vusb33);
0165 vusb33_err:
0166     return ret;
0167 }
0168 
0169 static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
0170 {
0171     clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
0172     regulator_disable(ssusb->vusb33);
0173     ssusb_phy_power_off(ssusb);
0174     ssusb_phy_exit(ssusb);
0175 }
0176 
0177 static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
0178 {
0179     /* reset whole ip (xhci & u3d) */
0180     mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
0181     udelay(1);
0182     mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
0183 
0184     /*
0185      * device ip may be powered on in firmware/BROM stage before entering
0186      * kernel stage;
0187      * power down device ip, otherwise ip-sleep will fail when working as
0188      * host only mode
0189      */
0190     mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
0191 }
0192 
0193 static void ssusb_u3_drd_check(struct ssusb_mtk *ssusb)
0194 {
0195     struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
0196     u32 dev_u3p_num;
0197     u32 host_u3p_num;
0198     u32 value;
0199 
0200     /* u3 port0 is disabled */
0201     if (ssusb->u3p_dis_msk & BIT(0)) {
0202         otg_sx->is_u3_drd = false;
0203         goto out;
0204     }
0205 
0206     value = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_DEV_CAP);
0207     dev_u3p_num = SSUSB_IP_DEV_U3_PORT_NUM(value);
0208 
0209     value = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_XHCI_CAP);
0210     host_u3p_num = SSUSB_IP_XHCI_U3_PORT_NUM(value);
0211 
0212     otg_sx->is_u3_drd = !!(dev_u3p_num && host_u3p_num);
0213 
0214 out:
0215     dev_info(ssusb->dev, "usb3-drd: %d\n", otg_sx->is_u3_drd);
0216 }
0217 
0218 static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
0219 {
0220     struct device_node *node = pdev->dev.of_node;
0221     struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
0222     struct clk_bulk_data *clks = ssusb->clks;
0223     struct device *dev = &pdev->dev;
0224     int i;
0225     int ret;
0226 
0227     ssusb->vusb33 = devm_regulator_get(dev, "vusb33");
0228     if (IS_ERR(ssusb->vusb33)) {
0229         dev_err(dev, "failed to get vusb33\n");
0230         return PTR_ERR(ssusb->vusb33);
0231     }
0232 
0233     clks[0].id = "sys_ck";
0234     clks[1].id = "ref_ck";
0235     clks[2].id = "mcu_ck";
0236     clks[3].id = "dma_ck";
0237     ret = devm_clk_bulk_get_optional(dev, BULK_CLKS_CNT, clks);
0238     if (ret)
0239         return ret;
0240 
0241     ssusb->num_phys = of_count_phandle_with_args(node,
0242             "phys", "#phy-cells");
0243     if (ssusb->num_phys > 0) {
0244         ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
0245                     sizeof(*ssusb->phys), GFP_KERNEL);
0246         if (!ssusb->phys)
0247             return -ENOMEM;
0248     } else {
0249         ssusb->num_phys = 0;
0250     }
0251 
0252     for (i = 0; i < ssusb->num_phys; i++) {
0253         ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
0254         if (IS_ERR(ssusb->phys[i])) {
0255             dev_err(dev, "failed to get phy-%d\n", i);
0256             return PTR_ERR(ssusb->phys[i]);
0257         }
0258     }
0259 
0260     ssusb->ippc_base = devm_platform_ioremap_resource_byname(pdev, "ippc");
0261     if (IS_ERR(ssusb->ippc_base))
0262         return PTR_ERR(ssusb->ippc_base);
0263 
0264     ssusb->wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
0265     if (ssusb->wakeup_irq == -EPROBE_DEFER)
0266         return ssusb->wakeup_irq;
0267 
0268     ssusb->dr_mode = usb_get_dr_mode(dev);
0269     if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN)
0270         ssusb->dr_mode = USB_DR_MODE_OTG;
0271 
0272     of_property_read_u32(node, "mediatek,u3p-dis-msk", &ssusb->u3p_dis_msk);
0273 
0274     if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
0275         goto out;
0276 
0277     /* if host role is supported */
0278     ret = ssusb_wakeup_of_property_parse(ssusb, node);
0279     if (ret) {
0280         dev_err(dev, "failed to parse uwk property\n");
0281         return ret;
0282     }
0283 
0284     /* optional property, ignore the error if it does not exist */
0285     of_property_read_u32(node, "mediatek,u2p-dis-msk",
0286                  &ssusb->u2p_dis_msk);
0287 
0288     otg_sx->vbus = devm_regulator_get(dev, "vbus");
0289     if (IS_ERR(otg_sx->vbus)) {
0290         dev_err(dev, "failed to get vbus\n");
0291         return PTR_ERR(otg_sx->vbus);
0292     }
0293 
0294     if (ssusb->dr_mode == USB_DR_MODE_HOST)
0295         goto out;
0296 
0297     /* if dual-role mode is supported */
0298     otg_sx->manual_drd_enabled =
0299         of_property_read_bool(node, "enable-manual-drd");
0300     otg_sx->role_sw_used = of_property_read_bool(node, "usb-role-switch");
0301 
0302     /* can't disable port0 when use dual-role mode */
0303     ssusb->u2p_dis_msk &= ~0x1;
0304 
0305     if (otg_sx->role_sw_used || otg_sx->manual_drd_enabled)
0306         goto out;
0307 
0308     if (of_property_read_bool(node, "extcon")) {
0309         otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
0310         if (IS_ERR(otg_sx->edev)) {
0311             return dev_err_probe(dev, PTR_ERR(otg_sx->edev),
0312                          "couldn't get extcon device\n");
0313         }
0314     }
0315 
0316 out:
0317     dev_info(dev, "dr_mode: %d, drd: %s\n", ssusb->dr_mode,
0318          otg_sx->manual_drd_enabled ? "manual" : "auto");
0319     dev_info(dev, "u2p_dis_msk: %x, u3p_dis_msk: %x\n",
0320          ssusb->u2p_dis_msk, ssusb->u3p_dis_msk);
0321 
0322     return 0;
0323 }
0324 
0325 static int mtu3_probe(struct platform_device *pdev)
0326 {
0327     struct device_node *node = pdev->dev.of_node;
0328     struct device *dev = &pdev->dev;
0329     struct ssusb_mtk *ssusb;
0330     int ret = -ENOMEM;
0331 
0332     /* all elements are set to ZERO as default value */
0333     ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
0334     if (!ssusb)
0335         return -ENOMEM;
0336 
0337     ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
0338     if (ret) {
0339         dev_err(dev, "No suitable DMA config available\n");
0340         return -ENOTSUPP;
0341     }
0342 
0343     platform_set_drvdata(pdev, ssusb);
0344     ssusb->dev = dev;
0345 
0346     ret = get_ssusb_rscs(pdev, ssusb);
0347     if (ret)
0348         return ret;
0349 
0350     ssusb_debugfs_create_root(ssusb);
0351 
0352     /* enable power domain */
0353     pm_runtime_set_active(dev);
0354     pm_runtime_use_autosuspend(dev);
0355     pm_runtime_set_autosuspend_delay(dev, 4000);
0356     pm_runtime_enable(dev);
0357     pm_runtime_get_sync(dev);
0358 
0359     ret = ssusb_rscs_init(ssusb);
0360     if (ret)
0361         goto comm_init_err;
0362 
0363     if (ssusb->wakeup_irq > 0) {
0364         ret = dev_pm_set_dedicated_wake_irq_reverse(dev, ssusb->wakeup_irq);
0365         if (ret) {
0366             dev_err(dev, "failed to set wakeup irq %d\n", ssusb->wakeup_irq);
0367             goto comm_exit;
0368         }
0369         dev_info(dev, "wakeup irq %d\n", ssusb->wakeup_irq);
0370     }
0371 
0372     ret = device_reset_optional(dev);
0373     if (ret) {
0374         dev_err_probe(dev, ret, "failed to reset controller\n");
0375         goto comm_exit;
0376     }
0377 
0378     ssusb_ip_sw_reset(ssusb);
0379     ssusb_u3_drd_check(ssusb);
0380 
0381     if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
0382         ssusb->dr_mode = USB_DR_MODE_HOST;
0383     else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
0384         ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
0385 
0386     /* default as host */
0387     ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
0388 
0389     switch (ssusb->dr_mode) {
0390     case USB_DR_MODE_PERIPHERAL:
0391         ret = ssusb_gadget_init(ssusb);
0392         if (ret) {
0393             dev_err(dev, "failed to initialize gadget\n");
0394             goto comm_exit;
0395         }
0396         break;
0397     case USB_DR_MODE_HOST:
0398         ret = ssusb_host_init(ssusb, node);
0399         if (ret) {
0400             dev_err(dev, "failed to initialize host\n");
0401             goto comm_exit;
0402         }
0403         break;
0404     case USB_DR_MODE_OTG:
0405         ret = ssusb_gadget_init(ssusb);
0406         if (ret) {
0407             dev_err(dev, "failed to initialize gadget\n");
0408             goto comm_exit;
0409         }
0410 
0411         ret = ssusb_host_init(ssusb, node);
0412         if (ret) {
0413             dev_err(dev, "failed to initialize host\n");
0414             goto gadget_exit;
0415         }
0416 
0417         ret = ssusb_otg_switch_init(ssusb);
0418         if (ret) {
0419             dev_err(dev, "failed to initialize switch\n");
0420             goto host_exit;
0421         }
0422         break;
0423     default:
0424         dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
0425         ret = -EINVAL;
0426         goto comm_exit;
0427     }
0428 
0429     device_enable_async_suspend(dev);
0430     pm_runtime_mark_last_busy(dev);
0431     pm_runtime_put_autosuspend(dev);
0432     pm_runtime_forbid(dev);
0433 
0434     return 0;
0435 
0436 host_exit:
0437     ssusb_host_exit(ssusb);
0438 gadget_exit:
0439     ssusb_gadget_exit(ssusb);
0440 comm_exit:
0441     ssusb_rscs_exit(ssusb);
0442 comm_init_err:
0443     pm_runtime_put_noidle(dev);
0444     pm_runtime_disable(dev);
0445     ssusb_debugfs_remove_root(ssusb);
0446 
0447     return ret;
0448 }
0449 
0450 static int mtu3_remove(struct platform_device *pdev)
0451 {
0452     struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
0453 
0454     pm_runtime_get_sync(&pdev->dev);
0455 
0456     switch (ssusb->dr_mode) {
0457     case USB_DR_MODE_PERIPHERAL:
0458         ssusb_gadget_exit(ssusb);
0459         break;
0460     case USB_DR_MODE_HOST:
0461         ssusb_host_exit(ssusb);
0462         break;
0463     case USB_DR_MODE_OTG:
0464         ssusb_otg_switch_exit(ssusb);
0465         ssusb_gadget_exit(ssusb);
0466         ssusb_host_exit(ssusb);
0467         break;
0468     default:
0469         return -EINVAL;
0470     }
0471 
0472     ssusb_rscs_exit(ssusb);
0473     ssusb_debugfs_remove_root(ssusb);
0474     pm_runtime_disable(&pdev->dev);
0475     pm_runtime_put_noidle(&pdev->dev);
0476     pm_runtime_set_suspended(&pdev->dev);
0477 
0478     return 0;
0479 }
0480 
0481 static int resume_ip_and_ports(struct ssusb_mtk *ssusb, pm_message_t msg)
0482 {
0483     switch (ssusb->dr_mode) {
0484     case USB_DR_MODE_PERIPHERAL:
0485         ssusb_gadget_resume(ssusb, msg);
0486         break;
0487     case USB_DR_MODE_HOST:
0488         ssusb_host_resume(ssusb, false);
0489         break;
0490     case USB_DR_MODE_OTG:
0491         ssusb_host_resume(ssusb, !ssusb->is_host);
0492         if (!ssusb->is_host)
0493             ssusb_gadget_resume(ssusb, msg);
0494 
0495         break;
0496     default:
0497         return -EINVAL;
0498     }
0499 
0500     return 0;
0501 }
0502 
0503 static int mtu3_suspend_common(struct device *dev, pm_message_t msg)
0504 {
0505     struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
0506     int ret = 0;
0507 
0508     dev_dbg(dev, "%s\n", __func__);
0509 
0510     switch (ssusb->dr_mode) {
0511     case USB_DR_MODE_PERIPHERAL:
0512         ret = ssusb_gadget_suspend(ssusb, msg);
0513         if (ret)
0514             goto err;
0515 
0516         break;
0517     case USB_DR_MODE_HOST:
0518         ssusb_host_suspend(ssusb);
0519         break;
0520     case USB_DR_MODE_OTG:
0521         if (!ssusb->is_host) {
0522             ret = ssusb_gadget_suspend(ssusb, msg);
0523             if (ret)
0524                 goto err;
0525         }
0526         ssusb_host_suspend(ssusb);
0527         break;
0528     default:
0529         return -EINVAL;
0530     }
0531 
0532     ret = wait_for_ip_sleep(ssusb);
0533     if (ret)
0534         goto sleep_err;
0535 
0536     ssusb_phy_power_off(ssusb);
0537     clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
0538     ssusb_wakeup_set(ssusb, true);
0539     return 0;
0540 
0541 sleep_err:
0542     resume_ip_and_ports(ssusb, msg);
0543 err:
0544     return ret;
0545 }
0546 
0547 static int mtu3_resume_common(struct device *dev, pm_message_t msg)
0548 {
0549     struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
0550     int ret;
0551 
0552     dev_dbg(dev, "%s\n", __func__);
0553 
0554     ssusb_wakeup_set(ssusb, false);
0555     ret = clk_bulk_prepare_enable(BULK_CLKS_CNT, ssusb->clks);
0556     if (ret)
0557         goto clks_err;
0558 
0559     ret = ssusb_phy_power_on(ssusb);
0560     if (ret)
0561         goto phy_err;
0562 
0563     return resume_ip_and_ports(ssusb, msg);
0564 
0565 phy_err:
0566     clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
0567 clks_err:
0568     return ret;
0569 }
0570 
0571 static int __maybe_unused mtu3_suspend(struct device *dev)
0572 {
0573     return mtu3_suspend_common(dev, PMSG_SUSPEND);
0574 }
0575 
0576 static int __maybe_unused mtu3_resume(struct device *dev)
0577 {
0578     return mtu3_resume_common(dev, PMSG_SUSPEND);
0579 }
0580 
0581 static int __maybe_unused mtu3_runtime_suspend(struct device *dev)
0582 {
0583     if (!device_may_wakeup(dev))
0584         return 0;
0585 
0586     return mtu3_suspend_common(dev, PMSG_AUTO_SUSPEND);
0587 }
0588 
0589 static int __maybe_unused mtu3_runtime_resume(struct device *dev)
0590 {
0591     if (!device_may_wakeup(dev))
0592         return 0;
0593 
0594     return mtu3_resume_common(dev, PMSG_AUTO_SUSPEND);
0595 }
0596 
0597 static const struct dev_pm_ops mtu3_pm_ops = {
0598     SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
0599     SET_RUNTIME_PM_OPS(mtu3_runtime_suspend,
0600                mtu3_runtime_resume, NULL)
0601 };
0602 
0603 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
0604 
0605 static const struct of_device_id mtu3_of_match[] = {
0606     {.compatible = "mediatek,mt8173-mtu3",},
0607     {.compatible = "mediatek,mtu3",},
0608     {},
0609 };
0610 MODULE_DEVICE_TABLE(of, mtu3_of_match);
0611 
0612 static struct platform_driver mtu3_driver = {
0613     .probe = mtu3_probe,
0614     .remove = mtu3_remove,
0615     .driver = {
0616         .name = MTU3_DRIVER_NAME,
0617         .pm = DEV_PM_OPS,
0618         .of_match_table = mtu3_of_match,
0619     },
0620 };
0621 module_platform_driver(mtu3_driver);
0622 
0623 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
0624 MODULE_LICENSE("GPL v2");
0625 MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");
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