usb/mtu3/mtu3_host.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * mtu3_dr.c - dual role switch and host glue layer
0004  *
0005  * Copyright (C) 2016 MediaTek Inc.
0006  *
0007  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/irq.h>
0012 #include <linux/kernel.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/of_device.h>
0015 #include <linux/regmap.h>
0016
0017 #include "mtu3.h"
0018 #include "mtu3_dr.h"
0019
0020 /* mt8173 etc */
0021 #define PERI_WK_CTRL1   0x4
0022 #define WC1_IS_C(x) (((x) & 0xf) << 26)  /* cycle debounce */
0023 #define WC1_IS_EN   BIT(25)
0024 #define WC1_IS_P    BIT(6)  /* polarity for ip sleep */
0025
0026 /* mt8183 */
0027 #define PERI_WK_CTRL0   0x0
0028 #define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28))  /* cycle debounce */
0029 #define WC0_IS_P    BIT(12) /* polarity */
0030 #define WC0_IS_EN   BIT(6)
0031
0032 /* mt8192 */
0033 #define WC0_SSUSB0_CDEN     BIT(6)
0034 #define WC0_IS_SPM_EN       BIT(1)
0035
0036 /* mt2712 etc */
0037 #define PERI_SSUSB_SPM_CTRL 0x0
0038 #define SSC_IP_SLEEP_EN BIT(4)
0039 #define SSC_SPM_INT_EN      BIT(1)
0040
0041 enum ssusb_uwk_vers {
0042     SSUSB_UWK_V1 = 1,
0043     SSUSB_UWK_V2,
0044     SSUSB_UWK_V1_1 = 101,   /* specific revision 1.01 */
0045     SSUSB_UWK_V1_2,     /* specific revision 1.02 */
0046 };
0047
0048 /*
0049  * ip-sleep wakeup mode:
0050  * all clocks can be turn off, but power domain should be kept on
0051  */
0052 static void ssusb_wakeup_ip_sleep_set(struct ssusb_mtk *ssusb, bool enable)
0053 {
0054     u32 reg, msk, val;
0055
0056     switch (ssusb->uwk_vers) {
0057     case SSUSB_UWK_V1:
0058         reg = ssusb->uwk_reg_base + PERI_WK_CTRL1;
0059         msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
0060         val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
0061         break;
0062     case SSUSB_UWK_V1_1:
0063         reg = ssusb->uwk_reg_base + PERI_WK_CTRL0;
0064         msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
0065         val = enable ? (WC0_IS_EN | WC0_IS_C(0x1)) : 0;
0066         break;
0067     case SSUSB_UWK_V1_2:
0068         reg = ssusb->uwk_reg_base + PERI_WK_CTRL0;
0069         msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
0070         val = enable ? msk : 0;
0071         break;
0072     case SSUSB_UWK_V2:
0073         reg = ssusb->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
0074         msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
0075         val = enable ? msk : 0;
0076         break;
0077     default:
0078         return;
0079     }
0080     regmap_update_bits(ssusb->uwk, reg, msk, val);
0081 }
0082
0083 int ssusb_wakeup_of_property_parse(struct ssusb_mtk *ssusb,
0084                 struct device_node *dn)
0085 {
0086     struct of_phandle_args args;
0087     int ret;
0088
0089     /* wakeup function is optional */
0090     ssusb->uwk_en = of_property_read_bool(dn, "wakeup-source");
0091     if (!ssusb->uwk_en)
0092         return 0;
0093
0094     ret = of_parse_phandle_with_fixed_args(dn,
0095                 "mediatek,syscon-wakeup", 2, 0, &args);
0096     if (ret)
0097         return ret;
0098
0099     ssusb->uwk_reg_base = args.args[0];
0100     ssusb->uwk_vers = args.args[1];
0101     ssusb->uwk = syscon_node_to_regmap(args.np);
0102     of_node_put(args.np);
0103     dev_info(ssusb->dev, "uwk - reg:0x%x, version:%d\n",
0104             ssusb->uwk_reg_base, ssusb->uwk_vers);
0105
0106     return PTR_ERR_OR_ZERO(ssusb->uwk);
0107 }
0108
0109 void ssusb_wakeup_set(struct ssusb_mtk *ssusb, bool enable)
0110 {
0111     if (ssusb->uwk_en)
0112         ssusb_wakeup_ip_sleep_set(ssusb, enable);
0113 }
0114
0115 static void host_ports_num_get(struct ssusb_mtk *ssusb)
0116 {
0117     u32 xhci_cap;
0118
0119     xhci_cap = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_XHCI_CAP);
0120     ssusb->u2_ports = SSUSB_IP_XHCI_U2_PORT_NUM(xhci_cap);
0121     ssusb->u3_ports = SSUSB_IP_XHCI_U3_PORT_NUM(xhci_cap);
0122
0123     dev_dbg(ssusb->dev, "host - u2_ports:%d, u3_ports:%d\n",
0124          ssusb->u2_ports, ssusb->u3_ports);
0125 }
0126
0127 /* only configure ports will be used later */
0128 static int ssusb_host_enable(struct ssusb_mtk *ssusb)
0129 {
0130     void __iomem *ibase = ssusb->ippc_base;
0131     int num_u3p = ssusb->u3_ports;
0132     int num_u2p = ssusb->u2_ports;
0133     int u3_ports_disabled;
0134     u32 check_clk;
0135     u32 value;
0136     int i;
0137
0138     /* power on host ip */
0139     mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
0140
0141     /* power on and enable u3 ports except skipped ones */
0142     u3_ports_disabled = 0;
0143     for (i = 0; i < num_u3p; i++) {
0144         if ((0x1 << i) & ssusb->u3p_dis_msk) {
0145             u3_ports_disabled++;
0146             continue;
0147         }
0148
0149         value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
0150         value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS);
0151         value |= SSUSB_U3_PORT_HOST_SEL;
0152         mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
0153     }
0154
0155     /* power on and enable all u2 ports */
0156     for (i = 0; i < num_u2p; i++) {
0157         if ((0x1 << i) & ssusb->u2p_dis_msk)
0158             continue;
0159
0160         value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
0161         value &= ~(SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS);
0162         value |= SSUSB_U2_PORT_HOST_SEL;
0163         mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
0164     }
0165
0166     check_clk = SSUSB_XHCI_RST_B_STS;
0167     if (num_u3p > u3_ports_disabled)
0168         check_clk = SSUSB_U3_MAC_RST_B_STS;
0169
0170     return ssusb_check_clocks(ssusb, check_clk);
0171 }
0172
0173 static int ssusb_host_disable(struct ssusb_mtk *ssusb)
0174 {
0175     void __iomem *ibase = ssusb->ippc_base;
0176     int num_u3p = ssusb->u3_ports;
0177     int num_u2p = ssusb->u2_ports;
0178     u32 value;
0179     int i;
0180
0181     /* power down and disable u3 ports except skipped ones */
0182     for (i = 0; i < num_u3p; i++) {
0183         if ((0x1 << i) & ssusb->u3p_dis_msk)
0184             continue;
0185
0186         value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
0187         value |= SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS;
0188         mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
0189     }
0190
0191     /* power down and disable u2 ports except skipped ones */
0192     for (i = 0; i < num_u2p; i++) {
0193         if ((0x1 << i) & ssusb->u2p_dis_msk)
0194             continue;
0195
0196         value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
0197         value |= SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS;
0198         mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
0199     }
0200
0201     /* power down host ip */
0202     mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
0203
0204     return 0;
0205 }
0206
0207 int ssusb_host_resume(struct ssusb_mtk *ssusb, bool p0_skipped)
0208 {
0209     void __iomem *ibase = ssusb->ippc_base;
0210     int u3p_skip_msk = ssusb->u3p_dis_msk;
0211     int u2p_skip_msk = ssusb->u2p_dis_msk;
0212     int num_u3p = ssusb->u3_ports;
0213     int num_u2p = ssusb->u2_ports;
0214     u32 value;
0215     int i;
0216
0217     if (p0_skipped) {
0218         u2p_skip_msk |= 0x1;
0219         if (ssusb->otg_switch.is_u3_drd)
0220             u3p_skip_msk |= 0x1;
0221     }
0222
0223     /* power on host ip */
0224     mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
0225
0226     /* power on u3 ports except skipped ones */
0227     for (i = 0; i < num_u3p; i++) {
0228         if ((0x1 << i) & u3p_skip_msk)
0229             continue;
0230
0231         value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
0232         value &= ~SSUSB_U3_PORT_PDN;
0233         mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
0234     }
0235
0236     /* power on all u2 ports except skipped ones */
0237     for (i = 0; i < num_u2p; i++) {
0238         if ((0x1 << i) & u2p_skip_msk)
0239             continue;
0240
0241         value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
0242         value &= ~SSUSB_U2_PORT_PDN;
0243         mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
0244     }
0245
0246     return 0;
0247 }
0248
0249 /* here not skip port0 due to PDN can be set repeatedly */
0250 int ssusb_host_suspend(struct ssusb_mtk *ssusb)
0251 {
0252     void __iomem *ibase = ssusb->ippc_base;
0253     int num_u3p = ssusb->u3_ports;
0254     int num_u2p = ssusb->u2_ports;
0255     u32 value;
0256     int i;
0257
0258     /* power down u3 ports except skipped ones */
0259     for (i = 0; i < num_u3p; i++) {
0260         if ((0x1 << i) & ssusb->u3p_dis_msk)
0261             continue;
0262
0263         value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
0264         value |= SSUSB_U3_PORT_PDN;
0265         mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
0266     }
0267
0268     /* power down u2 ports except skipped ones */
0269     for (i = 0; i < num_u2p; i++) {
0270         if ((0x1 << i) & ssusb->u2p_dis_msk)
0271             continue;
0272
0273         value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
0274         value |= SSUSB_U2_PORT_PDN;
0275         mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
0276     }
0277
0278     /* power down host ip */
0279     mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
0280
0281     return 0;
0282 }
0283
0284 static void ssusb_host_setup(struct ssusb_mtk *ssusb)
0285 {
0286     host_ports_num_get(ssusb);
0287
0288     /*
0289      * power on host and power on/enable all ports
0290      * if support OTG, gadget driver will switch port0 to device mode
0291      */
0292     ssusb_host_enable(ssusb);
0293     ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST);
0294
0295     /* if port0 supports dual-role, works as host mode by default */
0296     ssusb_set_vbus(&ssusb->otg_switch, 1);
0297 }
0298
0299 static void ssusb_host_cleanup(struct ssusb_mtk *ssusb)
0300 {
0301     if (ssusb->is_host)
0302         ssusb_set_vbus(&ssusb->otg_switch, 0);
0303
0304     ssusb_host_disable(ssusb);
0305 }
0306
0307 /*
0308  * If host supports multiple ports, the VBUSes(5V) of ports except port0
0309  * which supports OTG are better to be enabled by default in DTS.
0310  * Because the host driver will keep link with devices attached when system
0311  * enters suspend mode, so no need to control VBUSes after initialization.
0312  */
0313 int ssusb_host_init(struct ssusb_mtk *ssusb, struct device_node *parent_dn)
0314 {
0315     struct device *parent_dev = ssusb->dev;
0316     int ret;
0317
0318     ssusb_host_setup(ssusb);
0319
0320     ret = of_platform_populate(parent_dn, NULL, NULL, parent_dev);
0321     if (ret) {
0322         dev_dbg(parent_dev, "failed to create child devices at %pOF\n",
0323                 parent_dn);
0324         return ret;
0325     }
0326
0327     dev_info(parent_dev, "xHCI platform device register success...\n");
0328
0329     return 0;
0330 }
0331
0332 void ssusb_host_exit(struct ssusb_mtk *ssusb)
0333 {
0334     of_platform_depopulate(ssusb->dev);
0335     ssusb_host_cleanup(ssusb);
0336 }