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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * mtu3_core.c - hardware access layer and gadget init/exit of
0004  *                     MediaTek usb3 Dual-Role Controller Driver
0005  *
0006  * Copyright (C) 2016 MediaTek Inc.
0007  *
0008  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
0009  */
0010 
0011 #include <linux/dma-mapping.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/platform_device.h>
0017 
0018 #include "mtu3.h"
0019 #include "mtu3_dr.h"
0020 #include "mtu3_debug.h"
0021 #include "mtu3_trace.h"
0022 
0023 static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
0024 {
0025     struct mtu3_fifo_info *fifo = mep->fifo;
0026     u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
0027     u32 start_bit;
0028 
0029     /* ensure that @mep->fifo_seg_size is power of two */
0030     num_bits = roundup_pow_of_two(num_bits);
0031     if (num_bits > fifo->limit)
0032         return -EINVAL;
0033 
0034     mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
0035     num_bits = num_bits * (mep->slot + 1);
0036     start_bit = bitmap_find_next_zero_area(fifo->bitmap,
0037             fifo->limit, 0, num_bits, 0);
0038     if (start_bit >= fifo->limit)
0039         return -EOVERFLOW;
0040 
0041     bitmap_set(fifo->bitmap, start_bit, num_bits);
0042     mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
0043     mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
0044 
0045     dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
0046         __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
0047 
0048     return mep->fifo_addr;
0049 }
0050 
0051 static void ep_fifo_free(struct mtu3_ep *mep)
0052 {
0053     struct mtu3_fifo_info *fifo = mep->fifo;
0054     u32 addr = mep->fifo_addr;
0055     u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
0056     u32 start_bit;
0057 
0058     if (unlikely(addr < fifo->base || bits > fifo->limit))
0059         return;
0060 
0061     start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
0062     bitmap_clear(fifo->bitmap, start_bit, bits);
0063     mep->fifo_size = 0;
0064     mep->fifo_seg_size = 0;
0065 
0066     dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
0067         __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
0068 }
0069 
0070 /* enable/disable U3D SS function */
0071 static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
0072 {
0073     /* If usb3_en==0, LTSSM will go to SS.Disable state */
0074     if (enable)
0075         mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
0076     else
0077         mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
0078 
0079     dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
0080 }
0081 
0082 /* set/clear U3D HS device soft connect */
0083 static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
0084 {
0085     if (enable) {
0086         mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
0087             SOFT_CONN | SUSPENDM_ENABLE);
0088     } else {
0089         mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
0090             SOFT_CONN | SUSPENDM_ENABLE);
0091     }
0092     dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
0093 }
0094 
0095 /* only port0 of U2/U3 supports device mode */
0096 static int mtu3_device_enable(struct mtu3 *mtu)
0097 {
0098     void __iomem *ibase = mtu->ippc_base;
0099     u32 check_clk = 0;
0100 
0101     mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
0102 
0103     if (mtu->u3_capable) {
0104         check_clk = SSUSB_U3_MAC_RST_B_STS;
0105         mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
0106             (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
0107             SSUSB_U3_PORT_HOST_SEL));
0108     }
0109     mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
0110         (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
0111         SSUSB_U2_PORT_HOST_SEL));
0112 
0113     if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
0114         mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
0115         if (mtu->u3_capable)
0116             mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
0117                      SSUSB_U3_PORT_DUAL_MODE);
0118     }
0119 
0120     return ssusb_check_clocks(mtu->ssusb, check_clk);
0121 }
0122 
0123 static void mtu3_device_disable(struct mtu3 *mtu)
0124 {
0125     void __iomem *ibase = mtu->ippc_base;
0126 
0127     if (mtu->u3_capable)
0128         mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
0129             (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
0130 
0131     mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
0132         SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
0133 
0134     if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
0135         mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
0136         if (mtu->u3_capable)
0137             mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
0138                      SSUSB_U3_PORT_DUAL_MODE);
0139     }
0140 
0141     mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
0142 }
0143 
0144 static void mtu3_dev_power_on(struct mtu3 *mtu)
0145 {
0146     void __iomem *ibase = mtu->ippc_base;
0147 
0148     mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
0149     if (mtu->u3_capable)
0150         mtu3_clrbits(ibase, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN);
0151 
0152     mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN);
0153 }
0154 
0155 static void mtu3_dev_power_down(struct mtu3 *mtu)
0156 {
0157     void __iomem *ibase = mtu->ippc_base;
0158 
0159     if (mtu->u3_capable)
0160         mtu3_setbits(ibase, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN);
0161 
0162     mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN);
0163     mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
0164 }
0165 
0166 /* reset U3D's device module. */
0167 static void mtu3_device_reset(struct mtu3 *mtu)
0168 {
0169     void __iomem *ibase = mtu->ippc_base;
0170 
0171     mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
0172     udelay(1);
0173     mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
0174 }
0175 
0176 static void mtu3_intr_status_clear(struct mtu3 *mtu)
0177 {
0178     void __iomem *mbase = mtu->mac_base;
0179 
0180     /* Clear EP0 and Tx/Rx EPn interrupts status */
0181     mtu3_writel(mbase, U3D_EPISR, ~0x0);
0182     /* Clear U2 USB common interrupts status */
0183     mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
0184     /* Clear U3 LTSSM interrupts status */
0185     mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
0186     /* Clear speed change interrupt status */
0187     mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
0188     /* Clear QMU interrupt status */
0189     mtu3_writel(mbase, U3D_QISAR0, ~0x0);
0190 }
0191 
0192 /* disable all interrupts */
0193 static void mtu3_intr_disable(struct mtu3 *mtu)
0194 {
0195     /* Disable level 1 interrupts */
0196     mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0);
0197     /* Disable endpoint interrupts */
0198     mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0);
0199     mtu3_intr_status_clear(mtu);
0200 }
0201 
0202 /* enable system global interrupt */
0203 static void mtu3_intr_enable(struct mtu3 *mtu)
0204 {
0205     void __iomem *mbase = mtu->mac_base;
0206     u32 value;
0207 
0208     /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
0209     value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
0210     mtu3_writel(mbase, U3D_LV1IESR, value);
0211 
0212     /* Enable U2 common USB interrupts */
0213     value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
0214     mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
0215 
0216     if (mtu->u3_capable) {
0217         /* Enable U3 LTSSM interrupts */
0218         value = HOT_RST_INTR | WARM_RST_INTR |
0219             ENTER_U3_INTR | EXIT_U3_INTR;
0220         mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
0221     }
0222 
0223     /* Enable QMU interrupts. */
0224     value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
0225             RXQ_LENERR_INT | RXQ_ZLPERR_INT;
0226     mtu3_writel(mbase, U3D_QIESR1, value);
0227 
0228     /* Enable speed change interrupt */
0229     mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
0230 }
0231 
0232 static void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed)
0233 {
0234     void __iomem *mbase = mtu->mac_base;
0235 
0236     if (speed > mtu->max_speed)
0237         speed = mtu->max_speed;
0238 
0239     switch (speed) {
0240     case USB_SPEED_FULL:
0241         /* disable U3 SS function */
0242         mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
0243         /* disable HS function */
0244         mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
0245         break;
0246     case USB_SPEED_HIGH:
0247         mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
0248         /* HS/FS detected by HW */
0249         mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
0250         break;
0251     case USB_SPEED_SUPER:
0252         mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
0253         mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
0254                  SSUSB_U3_PORT_SSP_SPEED);
0255         break;
0256     case USB_SPEED_SUPER_PLUS:
0257         mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
0258         mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
0259                  SSUSB_U3_PORT_SSP_SPEED);
0260         break;
0261     default:
0262         dev_err(mtu->dev, "invalid speed: %s\n",
0263             usb_speed_string(speed));
0264         return;
0265     }
0266 
0267     mtu->speed = speed;
0268     dev_dbg(mtu->dev, "set speed: %s\n", usb_speed_string(speed));
0269 }
0270 
0271 /* CSR registers will be reset to default value if port is disabled */
0272 static void mtu3_csr_init(struct mtu3 *mtu)
0273 {
0274     void __iomem *mbase = mtu->mac_base;
0275 
0276     if (mtu->u3_capable) {
0277         /* disable LGO_U1/U2 by default */
0278         mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
0279                 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
0280         /* enable accept LGO_U1/U2 link command from host */
0281         mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
0282                 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
0283         /* device responses to u3_exit from host automatically */
0284         mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
0285         /* automatically build U2 link when U3 detect fail */
0286         mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
0287         /* auto clear SOFT_CONN when clear USB3_EN if work as HS */
0288         mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
0289     }
0290 
0291     /* delay about 0.1us from detecting reset to send chirp-K */
0292     mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
0293     /* enable automatical HWRW from L1 */
0294     mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
0295 }
0296 
0297 /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
0298 static void mtu3_ep_reset(struct mtu3_ep *mep)
0299 {
0300     struct mtu3 *mtu = mep->mtu;
0301     u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
0302 
0303     mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
0304     mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
0305 }
0306 
0307 /* set/clear the stall and toggle bits for non-ep0 */
0308 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
0309 {
0310     struct mtu3 *mtu = mep->mtu;
0311     void __iomem *mbase = mtu->mac_base;
0312     u8 epnum = mep->epnum;
0313     u32 csr;
0314 
0315     if (mep->is_in) {   /* TX */
0316         csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
0317         if (set)
0318             csr |= TX_SENDSTALL;
0319         else
0320             csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
0321         mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
0322     } else {    /* RX */
0323         csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
0324         if (set)
0325             csr |= RX_SENDSTALL;
0326         else
0327             csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
0328         mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
0329     }
0330 
0331     if (!set) {
0332         mtu3_ep_reset(mep);
0333         mep->flags &= ~MTU3_EP_STALL;
0334     } else {
0335         mep->flags |= MTU3_EP_STALL;
0336     }
0337 
0338     dev_dbg(mtu->dev, "%s: %s\n", mep->name,
0339         set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
0340 }
0341 
0342 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
0343 {
0344     if (mtu->u3_capable && mtu->speed >= USB_SPEED_SUPER)
0345         mtu3_ss_func_set(mtu, is_on);
0346     else
0347         mtu3_hs_softconn_set(mtu, is_on);
0348 
0349     dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
0350         usb_speed_string(mtu->speed), is_on ? "+" : "-");
0351 }
0352 
0353 void mtu3_start(struct mtu3 *mtu)
0354 {
0355     void __iomem *mbase = mtu->mac_base;
0356 
0357     dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
0358         mtu3_readl(mbase, U3D_DEVICE_CONTROL));
0359 
0360     mtu3_dev_power_on(mtu);
0361     mtu3_csr_init(mtu);
0362     mtu3_set_speed(mtu, mtu->speed);
0363 
0364     /* Initialize the default interrupts */
0365     mtu3_intr_enable(mtu);
0366     mtu->is_active = 1;
0367 
0368     if (mtu->softconnect)
0369         mtu3_dev_on_off(mtu, 1);
0370 }
0371 
0372 void mtu3_stop(struct mtu3 *mtu)
0373 {
0374     dev_dbg(mtu->dev, "%s\n", __func__);
0375 
0376     mtu3_intr_disable(mtu);
0377 
0378     if (mtu->softconnect)
0379         mtu3_dev_on_off(mtu, 0);
0380 
0381     mtu->is_active = 0;
0382     mtu3_dev_power_down(mtu);
0383 }
0384 
0385 static void mtu3_dev_suspend(struct mtu3 *mtu)
0386 {
0387     if (!mtu->is_active)
0388         return;
0389 
0390     mtu3_intr_disable(mtu);
0391     mtu3_dev_power_down(mtu);
0392 }
0393 
0394 static void mtu3_dev_resume(struct mtu3 *mtu)
0395 {
0396     if (!mtu->is_active)
0397         return;
0398 
0399     mtu3_dev_power_on(mtu);
0400     mtu3_intr_enable(mtu);
0401 }
0402 
0403 /* for non-ep0 */
0404 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
0405             int interval, int burst, int mult)
0406 {
0407     void __iomem *mbase = mtu->mac_base;
0408     bool gen2cp = mtu->gen2cp;
0409     int epnum = mep->epnum;
0410     u32 csr0, csr1, csr2;
0411     int fifo_sgsz, fifo_addr;
0412     int num_pkts;
0413 
0414     fifo_addr = ep_fifo_alloc(mep, mep->maxp);
0415     if (fifo_addr < 0) {
0416         dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
0417         return -ENOMEM;
0418     }
0419     fifo_sgsz = ilog2(mep->fifo_seg_size);
0420     dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
0421         mep->fifo_seg_size, mep->fifo_size);
0422 
0423     if (mep->is_in) {
0424         csr0 = TX_TXMAXPKTSZ(mep->maxp);
0425         csr0 |= TX_DMAREQEN;
0426 
0427         num_pkts = (burst + 1) * (mult + 1) - 1;
0428         csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
0429         csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
0430 
0431         csr2 = TX_FIFOADDR(fifo_addr >> 4);
0432         csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
0433 
0434         switch (mep->type) {
0435         case USB_ENDPOINT_XFER_BULK:
0436             csr1 |= TX_TYPE(TYPE_BULK);
0437             break;
0438         case USB_ENDPOINT_XFER_ISOC:
0439             csr1 |= TX_TYPE(TYPE_ISO);
0440             csr2 |= TX_BINTERVAL(interval);
0441             break;
0442         case USB_ENDPOINT_XFER_INT:
0443             csr1 |= TX_TYPE(TYPE_INT);
0444             csr2 |= TX_BINTERVAL(interval);
0445             break;
0446         }
0447 
0448         /* Enable QMU Done interrupt */
0449         mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
0450 
0451         mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
0452         mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
0453         mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
0454 
0455         dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
0456             epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
0457             mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
0458             mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
0459     } else {
0460         csr0 = RX_RXMAXPKTSZ(mep->maxp);
0461         csr0 |= RX_DMAREQEN;
0462 
0463         num_pkts = (burst + 1) * (mult + 1) - 1;
0464         csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
0465         csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
0466 
0467         csr2 = RX_FIFOADDR(fifo_addr >> 4);
0468         csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
0469 
0470         switch (mep->type) {
0471         case USB_ENDPOINT_XFER_BULK:
0472             csr1 |= RX_TYPE(TYPE_BULK);
0473             break;
0474         case USB_ENDPOINT_XFER_ISOC:
0475             csr1 |= RX_TYPE(TYPE_ISO);
0476             csr2 |= RX_BINTERVAL(interval);
0477             break;
0478         case USB_ENDPOINT_XFER_INT:
0479             csr1 |= RX_TYPE(TYPE_INT);
0480             csr2 |= RX_BINTERVAL(interval);
0481             break;
0482         }
0483 
0484         /*Enable QMU Done interrupt */
0485         mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
0486 
0487         mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
0488         mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
0489         mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
0490 
0491         dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
0492             epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
0493             mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
0494             mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
0495     }
0496 
0497     dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
0498     dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
0499         __func__, mep->name, mep->fifo_addr, mep->fifo_size,
0500         fifo_sgsz, mep->fifo_seg_size);
0501 
0502     return 0;
0503 }
0504 
0505 /* for non-ep0 */
0506 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
0507 {
0508     void __iomem *mbase = mtu->mac_base;
0509     int epnum = mep->epnum;
0510 
0511     if (mep->is_in) {
0512         mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
0513         mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
0514         mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
0515         mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
0516     } else {
0517         mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
0518         mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
0519         mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
0520         mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
0521     }
0522 
0523     mtu3_ep_reset(mep);
0524     ep_fifo_free(mep);
0525 
0526     dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
0527 }
0528 
0529 /*
0530  * Two scenarios:
0531  * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
0532  *  are separated;
0533  * 2. when supports only HS, the fifo is shared for all EPs, and
0534  *  the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
0535  *  the total fifo size of non-ep0, and ep0's is fixed to 64B,
0536  *  so the total fifo size is 64B + @EPNTXFFSZ;
0537  *  Due to the first 64B should be reserved for EP0, non-ep0's fifo
0538  *  starts from offset 64 and are divided into two equal parts for
0539  *  TX or RX EPs for simplification.
0540  */
0541 static void get_ep_fifo_config(struct mtu3 *mtu)
0542 {
0543     struct mtu3_fifo_info *tx_fifo;
0544     struct mtu3_fifo_info *rx_fifo;
0545     u32 fifosize;
0546 
0547     if (mtu->separate_fifo) {
0548         fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
0549         tx_fifo = &mtu->tx_fifo;
0550         tx_fifo->base = 0;
0551         tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
0552         bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
0553 
0554         fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
0555         rx_fifo = &mtu->rx_fifo;
0556         rx_fifo->base = 0;
0557         rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
0558         bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
0559         mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
0560     } else {
0561         fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
0562         tx_fifo = &mtu->tx_fifo;
0563         tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
0564         tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
0565         bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
0566 
0567         rx_fifo = &mtu->rx_fifo;
0568         rx_fifo->base =
0569             tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
0570         rx_fifo->limit = tx_fifo->limit;
0571         bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
0572         mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
0573     }
0574 
0575     dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
0576         __func__, tx_fifo->base, tx_fifo->limit,
0577         rx_fifo->base, rx_fifo->limit);
0578 }
0579 
0580 static void mtu3_ep0_setup(struct mtu3 *mtu)
0581 {
0582     u32 maxpacket = mtu->g.ep0->maxpacket;
0583     u32 csr;
0584 
0585     dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
0586 
0587     csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
0588     csr &= ~EP0_MAXPKTSZ_MSK;
0589     csr |= EP0_MAXPKTSZ(maxpacket);
0590     csr &= EP0_W1C_BITS;
0591     mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
0592 
0593     /* Enable EP0 interrupt */
0594     mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
0595 }
0596 
0597 static int mtu3_mem_alloc(struct mtu3 *mtu)
0598 {
0599     void __iomem *mbase = mtu->mac_base;
0600     struct mtu3_ep *ep_array;
0601     int in_ep_num, out_ep_num;
0602     u32 cap_epinfo;
0603     int ret;
0604     int i;
0605 
0606     cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
0607     in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
0608     out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
0609 
0610     dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
0611          mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
0612          mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
0613 
0614     /* one for ep0, another is reserved */
0615     mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
0616     ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
0617     if (ep_array == NULL)
0618         return -ENOMEM;
0619 
0620     mtu->ep_array = ep_array;
0621     mtu->in_eps = ep_array;
0622     mtu->out_eps = &ep_array[mtu->num_eps];
0623     /* ep0 uses in_eps[0], out_eps[0] is reserved */
0624     mtu->ep0 = mtu->in_eps;
0625     mtu->ep0->mtu = mtu;
0626     mtu->ep0->epnum = 0;
0627 
0628     for (i = 1; i < mtu->num_eps; i++) {
0629         struct mtu3_ep *mep = mtu->in_eps + i;
0630 
0631         mep->fifo = &mtu->tx_fifo;
0632         mep = mtu->out_eps + i;
0633         mep->fifo = &mtu->rx_fifo;
0634     }
0635 
0636     get_ep_fifo_config(mtu);
0637 
0638     ret = mtu3_qmu_init(mtu);
0639     if (ret)
0640         kfree(mtu->ep_array);
0641 
0642     return ret;
0643 }
0644 
0645 static void mtu3_mem_free(struct mtu3 *mtu)
0646 {
0647     mtu3_qmu_exit(mtu);
0648     kfree(mtu->ep_array);
0649 }
0650 
0651 static void mtu3_regs_init(struct mtu3 *mtu)
0652 {
0653     void __iomem *mbase = mtu->mac_base;
0654 
0655     /* be sure interrupts are disabled before registration of ISR */
0656     mtu3_intr_disable(mtu);
0657 
0658     mtu3_csr_init(mtu);
0659 
0660     /* U2/U3 detected by HW */
0661     mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
0662     /* vbus detected by HW */
0663     mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
0664     /* use new QMU format when HW version >= 0x1003 */
0665     if (mtu->gen2cp)
0666         mtu3_writel(mbase, U3D_QFCR, ~0x0);
0667 }
0668 
0669 static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
0670 {
0671     void __iomem *mbase = mtu->mac_base;
0672     enum usb_device_speed udev_speed;
0673     u32 maxpkt = 64;
0674     u32 link;
0675     u32 speed;
0676 
0677     link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
0678     link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
0679     mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
0680     dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
0681 
0682     if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
0683         return IRQ_NONE;
0684 
0685     speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
0686 
0687     switch (speed) {
0688     case MTU3_SPEED_FULL:
0689         udev_speed = USB_SPEED_FULL;
0690         /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
0691         mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
0692                 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
0693         mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
0694                 LPM_BESL_STALL | LPM_BESLD_STALL);
0695         break;
0696     case MTU3_SPEED_HIGH:
0697         udev_speed = USB_SPEED_HIGH;
0698         /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
0699         mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
0700                 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
0701         mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
0702                 LPM_BESL_STALL | LPM_BESLD_STALL);
0703         break;
0704     case MTU3_SPEED_SUPER:
0705         udev_speed = USB_SPEED_SUPER;
0706         maxpkt = 512;
0707         break;
0708     case MTU3_SPEED_SUPER_PLUS:
0709         udev_speed = USB_SPEED_SUPER_PLUS;
0710         maxpkt = 512;
0711         break;
0712     default:
0713         udev_speed = USB_SPEED_UNKNOWN;
0714         break;
0715     }
0716     dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
0717     mtu3_dbg_trace(mtu->dev, "link speed %s",
0718                usb_speed_string(udev_speed));
0719 
0720     mtu->g.speed = udev_speed;
0721     mtu->g.ep0->maxpacket = maxpkt;
0722     mtu->ep0_state = MU3D_EP0_STATE_SETUP;
0723     mtu->connected = !!(udev_speed != USB_SPEED_UNKNOWN);
0724 
0725     if (udev_speed == USB_SPEED_UNKNOWN) {
0726         mtu3_gadget_disconnect(mtu);
0727         pm_runtime_put(mtu->dev);
0728     } else {
0729         pm_runtime_get(mtu->dev);
0730         mtu3_ep0_setup(mtu);
0731     }
0732 
0733     return IRQ_HANDLED;
0734 }
0735 
0736 static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
0737 {
0738     void __iomem *mbase = mtu->mac_base;
0739     u32 ltssm;
0740 
0741     ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
0742     ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
0743     mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
0744     dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
0745     trace_mtu3_u3_ltssm_isr(ltssm);
0746 
0747     if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
0748         mtu3_gadget_reset(mtu);
0749 
0750     if (ltssm & VBUS_FALL_INTR) {
0751         mtu3_ss_func_set(mtu, false);
0752         mtu3_gadget_reset(mtu);
0753     }
0754 
0755     if (ltssm & VBUS_RISE_INTR)
0756         mtu3_ss_func_set(mtu, true);
0757 
0758     if (ltssm & EXIT_U3_INTR)
0759         mtu3_gadget_resume(mtu);
0760 
0761     if (ltssm & ENTER_U3_INTR)
0762         mtu3_gadget_suspend(mtu);
0763 
0764     return IRQ_HANDLED;
0765 }
0766 
0767 static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
0768 {
0769     void __iomem *mbase = mtu->mac_base;
0770     u32 u2comm;
0771 
0772     u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
0773     u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
0774     mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
0775     dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
0776     trace_mtu3_u2_common_isr(u2comm);
0777 
0778     if (u2comm & SUSPEND_INTR)
0779         mtu3_gadget_suspend(mtu);
0780 
0781     if (u2comm & RESUME_INTR)
0782         mtu3_gadget_resume(mtu);
0783 
0784     if (u2comm & RESET_INTR)
0785         mtu3_gadget_reset(mtu);
0786 
0787     return IRQ_HANDLED;
0788 }
0789 
0790 static irqreturn_t mtu3_irq(int irq, void *data)
0791 {
0792     struct mtu3 *mtu = (struct mtu3 *)data;
0793     unsigned long flags;
0794     u32 level1;
0795 
0796     spin_lock_irqsave(&mtu->lock, flags);
0797 
0798     /* U3D_LV1ISR is RU */
0799     level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
0800     level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
0801 
0802     if (level1 & EP_CTRL_INTR)
0803         mtu3_link_isr(mtu);
0804 
0805     if (level1 & MAC2_INTR)
0806         mtu3_u2_common_isr(mtu);
0807 
0808     if (level1 & MAC3_INTR)
0809         mtu3_u3_ltssm_isr(mtu);
0810 
0811     if (level1 & BMU_INTR)
0812         mtu3_ep0_isr(mtu);
0813 
0814     if (level1 & QMU_INTR)
0815         mtu3_qmu_isr(mtu);
0816 
0817     spin_unlock_irqrestore(&mtu->lock, flags);
0818 
0819     return IRQ_HANDLED;
0820 }
0821 
0822 static void mtu3_check_params(struct mtu3 *mtu)
0823 {
0824     /* device's u3 port (port0) is disabled */
0825     if (mtu->u3_capable && (mtu->ssusb->u3p_dis_msk & BIT(0)))
0826         mtu->u3_capable = 0;
0827 
0828     /* check the max_speed parameter */
0829     switch (mtu->max_speed) {
0830     case USB_SPEED_FULL:
0831     case USB_SPEED_HIGH:
0832     case USB_SPEED_SUPER:
0833     case USB_SPEED_SUPER_PLUS:
0834         break;
0835     default:
0836         dev_err(mtu->dev, "invalid max_speed: %s\n",
0837             usb_speed_string(mtu->max_speed));
0838         fallthrough;
0839     case USB_SPEED_UNKNOWN:
0840         /* default as SSP */
0841         mtu->max_speed = USB_SPEED_SUPER_PLUS;
0842         break;
0843     }
0844 
0845     if (!mtu->u3_capable && (mtu->max_speed > USB_SPEED_HIGH))
0846         mtu->max_speed = USB_SPEED_HIGH;
0847 
0848     mtu->speed = mtu->max_speed;
0849 
0850     dev_info(mtu->dev, "max_speed: %s\n",
0851          usb_speed_string(mtu->max_speed));
0852 }
0853 
0854 static int mtu3_hw_init(struct mtu3 *mtu)
0855 {
0856     u32 value;
0857     int ret;
0858 
0859     value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
0860     mtu->hw_version = IP_TRUNK_VERS(value);
0861     mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
0862 
0863     value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
0864     mtu->u3_capable = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
0865     /* usb3 ip uses separate fifo */
0866     mtu->separate_fifo = mtu->u3_capable;
0867 
0868     dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
0869         mtu->u3_capable ? "U3" : "U2");
0870 
0871     mtu3_check_params(mtu);
0872 
0873     mtu3_device_reset(mtu);
0874 
0875     ret = mtu3_device_enable(mtu);
0876     if (ret) {
0877         dev_err(mtu->dev, "device enable failed %d\n", ret);
0878         return ret;
0879     }
0880 
0881     ret = mtu3_mem_alloc(mtu);
0882     if (ret)
0883         return -ENOMEM;
0884 
0885     mtu3_regs_init(mtu);
0886 
0887     return 0;
0888 }
0889 
0890 static void mtu3_hw_exit(struct mtu3 *mtu)
0891 {
0892     mtu3_device_disable(mtu);
0893     mtu3_mem_free(mtu);
0894 }
0895 
0896 /*
0897  * we set 32-bit DMA mask by default, here check whether the controller
0898  * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
0899  */
0900 static int mtu3_set_dma_mask(struct mtu3 *mtu)
0901 {
0902     struct device *dev = mtu->dev;
0903     bool is_36bit = false;
0904     int ret = 0;
0905     u32 value;
0906 
0907     value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
0908     if (value & DMA_ADDR_36BIT) {
0909         is_36bit = true;
0910         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
0911         /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
0912         if (ret) {
0913             is_36bit = false;
0914             ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
0915         }
0916     }
0917     dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
0918 
0919     return ret;
0920 }
0921 
0922 int ssusb_gadget_init(struct ssusb_mtk *ssusb)
0923 {
0924     struct device *dev = ssusb->dev;
0925     struct platform_device *pdev = to_platform_device(dev);
0926     struct mtu3 *mtu = NULL;
0927     int ret = -ENOMEM;
0928 
0929     mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
0930     if (mtu == NULL)
0931         return -ENOMEM;
0932 
0933     mtu->irq = platform_get_irq_byname_optional(pdev, "device");
0934     if (mtu->irq < 0) {
0935         if (mtu->irq == -EPROBE_DEFER)
0936             return mtu->irq;
0937 
0938         /* for backward compatibility */
0939         mtu->irq = platform_get_irq(pdev, 0);
0940         if (mtu->irq < 0)
0941             return mtu->irq;
0942     }
0943     dev_info(dev, "irq %d\n", mtu->irq);
0944 
0945     mtu->mac_base = devm_platform_ioremap_resource_byname(pdev, "mac");
0946     if (IS_ERR(mtu->mac_base)) {
0947         dev_err(dev, "error mapping memory for dev mac\n");
0948         return PTR_ERR(mtu->mac_base);
0949     }
0950 
0951     spin_lock_init(&mtu->lock);
0952     mtu->dev = dev;
0953     mtu->ippc_base = ssusb->ippc_base;
0954     ssusb->mac_base = mtu->mac_base;
0955     ssusb->u3d = mtu;
0956     mtu->ssusb = ssusb;
0957     mtu->max_speed = usb_get_maximum_speed(dev);
0958 
0959     dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
0960         mtu->mac_base, mtu->ippc_base);
0961 
0962     ret = mtu3_hw_init(mtu);
0963     if (ret) {
0964         dev_err(dev, "mtu3 hw init failed:%d\n", ret);
0965         return ret;
0966     }
0967 
0968     ret = mtu3_set_dma_mask(mtu);
0969     if (ret) {
0970         dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
0971         goto dma_mask_err;
0972     }
0973 
0974     ret = devm_request_threaded_irq(dev, mtu->irq, NULL, mtu3_irq,
0975                     IRQF_ONESHOT, dev_name(dev), mtu);
0976     if (ret) {
0977         dev_err(dev, "request irq %d failed!\n", mtu->irq);
0978         goto irq_err;
0979     }
0980 
0981     device_init_wakeup(dev, true);
0982 
0983     /* power down device IP for power saving by default */
0984     mtu3_stop(mtu);
0985 
0986     ret = mtu3_gadget_setup(mtu);
0987     if (ret) {
0988         dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
0989         goto gadget_err;
0990     }
0991 
0992     ssusb_dev_debugfs_init(ssusb);
0993 
0994     dev_dbg(dev, " %s() done...\n", __func__);
0995 
0996     return 0;
0997 
0998 gadget_err:
0999     device_init_wakeup(dev, false);
1000 
1001 dma_mask_err:
1002 irq_err:
1003     mtu3_hw_exit(mtu);
1004     ssusb->u3d = NULL;
1005     dev_err(dev, " %s() fail...\n", __func__);
1006 
1007     return ret;
1008 }
1009 
1010 void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
1011 {
1012     struct mtu3 *mtu = ssusb->u3d;
1013 
1014     mtu3_gadget_cleanup(mtu);
1015     device_init_wakeup(ssusb->dev, false);
1016     mtu3_hw_exit(mtu);
1017 }
1018 
1019 bool ssusb_gadget_ip_sleep_check(struct ssusb_mtk *ssusb)
1020 {
1021     struct mtu3 *mtu = ssusb->u3d;
1022 
1023     /* host only, should wait for ip sleep */
1024     if (!mtu)
1025         return true;
1026 
1027     /* device is started and pullup D+, ip can sleep */
1028     if (mtu->is_active && mtu->softconnect)
1029         return true;
1030 
1031     /* ip can't sleep if not pullup D+ when support device mode */
1032     return false;
1033 }
1034 
1035 int ssusb_gadget_suspend(struct ssusb_mtk *ssusb, pm_message_t msg)
1036 {
1037     struct mtu3 *mtu = ssusb->u3d;
1038 
1039     if (!mtu->gadget_driver)
1040         return 0;
1041 
1042     if (mtu->connected)
1043         return -EBUSY;
1044 
1045     mtu3_dev_suspend(mtu);
1046     synchronize_irq(mtu->irq);
1047 
1048     return 0;
1049 }
1050 
1051 int ssusb_gadget_resume(struct ssusb_mtk *ssusb, pm_message_t msg)
1052 {
1053     struct mtu3 *mtu = ssusb->u3d;
1054 
1055     if (!mtu->gadget_driver)
1056         return 0;
1057 
1058     mtu3_dev_resume(mtu);
1059 
1060     return 0;
1061 }
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