usb/mtu3/mtu3.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mtu3.h - MediaTek USB3 DRD header
0004  *
0005  * Copyright (C) 2016 MediaTek Inc.
0006  *
0007  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
0008  */
0009
0010 #ifndef __MTU3_H__
0011 #define __MTU3_H__
0012
0013 #include <linux/clk.h>
0014 #include <linux/device.h>
0015 #include <linux/dmapool.h>
0016 #include <linux/extcon.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/list.h>
0019 #include <linux/phy/phy.h>
0020 #include <linux/regulator/consumer.h>
0021 #include <linux/usb.h>
0022 #include <linux/usb/ch9.h>
0023 #include <linux/usb/gadget.h>
0024 #include <linux/usb/otg.h>
0025 #include <linux/usb/role.h>
0026
0027 struct mtu3;
0028 struct mtu3_ep;
0029 struct mtu3_request;
0030
0031 #include "mtu3_hw_regs.h"
0032 #include "mtu3_qmu.h"
0033
0034 #define MU3D_EP_TXCR0(epnum)    (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
0035 #define MU3D_EP_TXCR1(epnum)    (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
0036 #define MU3D_EP_TXCR2(epnum)    (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
0037
0038 #define MU3D_EP_RXCR0(epnum)    (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
0039 #define MU3D_EP_RXCR1(epnum)    (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
0040 #define MU3D_EP_RXCR2(epnum)    (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
0041
0042 #define USB_QMU_TQHIAR(epnum)   (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
0043 #define USB_QMU_RQHIAR(epnum)   (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
0044
0045 #define USB_QMU_RQCSR(epnum)    (U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
0046 #define USB_QMU_RQSAR(epnum)    (U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
0047 #define USB_QMU_RQCPR(epnum)    (U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
0048
0049 #define USB_QMU_TQCSR(epnum)    (U3D_TXQCSR1 + (((epnum) - 1) * 0x10))
0050 #define USB_QMU_TQSAR(epnum)    (U3D_TXQSAR1 + (((epnum) - 1) * 0x10))
0051 #define USB_QMU_TQCPR(epnum)    (U3D_TXQCPR1 + (((epnum) - 1) * 0x10))
0052
0053 #define SSUSB_U3_CTRL(p)    (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08))
0054 #define SSUSB_U2_CTRL(p)    (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08))
0055
0056 #define MTU3_DRIVER_NAME    "mtu3"
0057 #define DMA_ADDR_INVALID    (~(dma_addr_t)0)
0058
0059 #define MTU3_EP_ENABLED     BIT(0)
0060 #define MTU3_EP_STALL       BIT(1)
0061 #define MTU3_EP_WEDGE       BIT(2)
0062 #define MTU3_EP_BUSY        BIT(3)
0063
0064 #define MTU3_U3_IP_SLOT_DEFAULT 2
0065 #define MTU3_U2_IP_SLOT_DEFAULT 1
0066
0067 /**
0068  * IP TRUNK version
0069  * from 0x1003 version, USB3 Gen2 is supported, two changes affect driver:
0070  * 1. MAXPKT and MULTI bits layout of TXCSR1 and RXCSR1 are adjusted,
0071  *    but not backward compatible
0072  * 2. QMU extend buffer length supported
0073  */
0074 #define MTU3_TRUNK_VERS_1003    0x1003
0075
0076 /**
0077  * Normally the device works on HS or SS, to simplify fifo management,
0078  * devide fifo into some 512B parts, use bitmap to manage it; And
0079  * 128 bits size of bitmap is large enough, that means it can manage
0080  * up to 64KB fifo size.
0081  * NOTE: MTU3_EP_FIFO_UNIT should be power of two
0082  */
0083 #define MTU3_EP_FIFO_UNIT       (1 << 9)
0084 #define MTU3_FIFO_BIT_SIZE      128
0085 #define MTU3_U2_IP_EP0_FIFO_SIZE    64
0086
0087 /**
0088  * Maximum size of ep0 response buffer for ch9 requests,
0089  * the SET_SEL request uses 6 so far, and GET_STATUS is 2
0090  */
0091 #define EP0_RESPONSE_BUF  6
0092
0093 #define BULK_CLKS_CNT   4
0094
0095 /* device operated link and speed got from DEVICE_CONF register */
0096 enum mtu3_speed {
0097     MTU3_SPEED_INACTIVE = 0,
0098     MTU3_SPEED_FULL = 1,
0099     MTU3_SPEED_HIGH = 3,
0100     MTU3_SPEED_SUPER = 4,
0101     MTU3_SPEED_SUPER_PLUS = 5,
0102 };
0103
0104 /**
0105  * @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP
0106  *      without data stage.
0107  * @MU3D_EP0_STATE_TX: IN data stage
0108  * @MU3D_EP0_STATE_RX: OUT data stage
0109  * @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and
0110  *      waits for its completion interrupt
0111  * @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared
0112  *      after receives a SETUP.
0113  */
0114 enum mtu3_g_ep0_state {
0115     MU3D_EP0_STATE_SETUP = 1,
0116     MU3D_EP0_STATE_TX,
0117     MU3D_EP0_STATE_RX,
0118     MU3D_EP0_STATE_TX_END,
0119     MU3D_EP0_STATE_STALL,
0120 };
0121
0122 /**
0123  * MTU3_DR_FORCE_NONE: automatically switch host and periperal mode
0124  *      by IDPIN signal.
0125  * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG
0126  *      IDPIN signal.
0127  * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode.
0128  */
0129 enum mtu3_dr_force_mode {
0130     MTU3_DR_FORCE_NONE = 0,
0131     MTU3_DR_FORCE_HOST,
0132     MTU3_DR_FORCE_DEVICE,
0133 };
0134
0135 /**
0136  * @base: the base address of fifo
0137  * @limit: the bitmap size in bits
0138  * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT
0139  */
0140 struct mtu3_fifo_info {
0141     u32 base;
0142     u32 limit;
0143     DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE);
0144 };
0145
0146 /**
0147  * General Purpose Descriptor (GPD):
0148  *  The format of TX GPD is a little different from RX one.
0149  *  And the size of GPD is 16 bytes.
0150  *
0151  * @dw0_info:
0152  *  bit0: Hardware Own (HWO)
0153  *  bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported
0154  *  bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1
0155  *  bit6: [EL] Zero Length Packet (ZLP), moved from @dw3_info[29]
0156  *  bit7: Interrupt On Completion (IOC)
0157  *  bit[31:16]: ([EL] bit[31:12]) allow data buffer length (RX ONLY),
0158  *      the buffer length of the data to receive
0159  *  bit[23:16]: ([EL] bit[31:24]) extension address (TX ONLY),
0160  *      lower 4 bits are extension bits of @buffer,
0161  *      upper 4 bits are extension bits of @next_gpd
0162  * @next_gpd: Physical address of the next GPD
0163  * @buffer: Physical address of the data buffer
0164  * @dw3_info:
0165  *  bit[15:0]: ([EL] bit[19:0]) data buffer length,
0166  *      (TX): the buffer length of the data to transmit
0167  *      (RX): The total length of data received
0168  *  bit[23:16]: ([EL] bit[31:24]) extension address (RX ONLY),
0169  *      lower 4 bits are extension bits of @buffer,
0170  *      upper 4 bits are extension bits of @next_gpd
0171  *  bit29: ([EL] abandoned) Zero Length Packet (ZLP) (TX ONLY)
0172  */
0173 struct qmu_gpd {
0174     __le32 dw0_info;
0175     __le32 next_gpd;
0176     __le32 buffer;
0177     __le32 dw3_info;
0178 } __packed;
0179
0180 /**
0181 * dma: physical base address of GPD segment
0182 * start: virtual base address of GPD segment
0183 * end: the last GPD element
0184 * enqueue: the first empty GPD to use
0185 * dequeue: the first completed GPD serviced by ISR
0186 * NOTE: the size of GPD ring should be >= 2
0187 */
0188 struct mtu3_gpd_ring {
0189     dma_addr_t dma;
0190     struct qmu_gpd *start;
0191     struct qmu_gpd *end;
0192     struct qmu_gpd *enqueue;
0193     struct qmu_gpd *dequeue;
0194 };
0195
0196 /**
0197 * @vbus: vbus 5V used by host mode
0198 * @edev: external connector used to detect vbus and iddig changes
0199 * @id_nb : notifier for iddig(idpin) detection
0200 * @dr_work : work for drd mode switch, used to avoid sleep in atomic context
0201 * @desired_role : role desired to switch
0202 * @default_role : default mode while usb role is USB_ROLE_NONE
0203 * @role_sw : use USB Role Switch to support dual-role switch, can't use
0204 *       extcon at the same time, and extcon is deprecated.
0205 * @role_sw_used : true when the USB Role Switch is used.
0206 * @is_u3_drd: whether port0 supports usb3.0 dual-role device or not
0207 * @manual_drd_enabled: it's true when supports dual-role device by debugfs
0208 *       to switch host/device modes depending on user input.
0209 */
0210 struct otg_switch_mtk {
0211     struct regulator *vbus;
0212     struct extcon_dev *edev;
0213     struct notifier_block id_nb;
0214     struct work_struct dr_work;
0215     enum usb_role desired_role;
0216     enum usb_role default_role;
0217     struct usb_role_switch *role_sw;
0218     bool role_sw_used;
0219     bool is_u3_drd;
0220     bool manual_drd_enabled;
0221 };
0222
0223 /**
0224  * @mac_base: register base address of device MAC, exclude xHCI's
0225  * @ippc_base: register base address of IP Power and Clock interface (IPPC)
0226  * @vusb33: usb3.3V shared by device/host IP
0227  * @dr_mode: works in which mode:
0228  *      host only, device only or dual-role mode
0229  * @u2_ports: number of usb2.0 host ports
0230  * @u3_ports: number of usb3.0 host ports
0231  * @u2p_dis_msk: mask of disabling usb2 ports, e.g. bit0==1 to
0232  *      disable u2port0, bit1==1 to disable u2port1,... etc,
0233  *      but when use dual-role mode, can't disable u2port0
0234  * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to
0235  *      disable u3port0, bit1==1 to disable u3port1,... etc
0236  * @dbgfs_root: only used when supports manual dual-role switch via debugfs
0237  * @uwk_en: it's true when supports remote wakeup in host mode
0238  * @uwk: syscon including usb wakeup glue layer between SSUSB IP and SPM
0239  * @uwk_reg_base: the base address of the wakeup glue layer in @uwk
0240  * @uwk_vers: the version of the wakeup glue layer
0241  */
0242 struct ssusb_mtk {
0243     struct device *dev;
0244     struct mtu3 *u3d;
0245     void __iomem *mac_base;
0246     void __iomem *ippc_base;
0247     struct phy **phys;
0248     int num_phys;
0249     int wakeup_irq;
0250     /* common power & clock */
0251     struct regulator *vusb33;
0252     struct clk_bulk_data clks[BULK_CLKS_CNT];
0253     /* otg */
0254     struct otg_switch_mtk otg_switch;
0255     enum usb_dr_mode dr_mode;
0256     bool is_host;
0257     int u2_ports;
0258     int u3_ports;
0259     int u2p_dis_msk;
0260     int u3p_dis_msk;
0261     struct dentry *dbgfs_root;
0262     /* usb wakeup for host mode */
0263     bool uwk_en;
0264     struct regmap *uwk;
0265     u32 uwk_reg_base;
0266     u32 uwk_vers;
0267 };
0268
0269 /**
0270  * @fifo_size: it is (@slot + 1) * @fifo_seg_size
0271  * @fifo_seg_size: it is roundup_pow_of_two(@maxp)
0272  */
0273 struct mtu3_ep {
0274     struct usb_ep ep;
0275     char name[12];
0276     struct mtu3 *mtu;
0277     u8 epnum;
0278     u8 type;
0279     u8 is_in;
0280     u16 maxp;
0281     int slot;
0282     u32 fifo_size;
0283     u32 fifo_addr;
0284     u32 fifo_seg_size;
0285     struct mtu3_fifo_info *fifo;
0286
0287     struct list_head req_list;
0288     struct mtu3_gpd_ring gpd_ring;
0289     const struct usb_ss_ep_comp_descriptor *comp_desc;
0290     const struct usb_endpoint_descriptor *desc;
0291
0292     int flags;
0293 };
0294
0295 struct mtu3_request {
0296     struct usb_request request;
0297     struct list_head list;
0298     struct mtu3_ep *mep;
0299     struct mtu3 *mtu;
0300     struct qmu_gpd *gpd;
0301     int epnum;
0302 };
0303
0304 static inline struct ssusb_mtk *dev_to_ssusb(struct device *dev)
0305 {
0306     return dev_get_drvdata(dev);
0307 }
0308
0309 /**
0310  * struct mtu3 - device driver instance data.
0311  * @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only,
0312  *      MTU3_U3_IP_SLOT_DEFAULT for U3 IP
0313  * @may_wakeup: means device's remote wakeup is enabled
0314  * @is_self_powered: is reported in device status and the config descriptor
0315  * @delayed_status: true when function drivers ask for delayed status
0316  * @gen2cp: compatible with USB3 Gen2 IP
0317  * @ep0_req: dummy request used while handling standard USB requests
0318  *      for GET_STATUS and SET_SEL
0319  * @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests
0320  * @u3_capable: is capable of supporting USB3
0321  */
0322 struct mtu3 {
0323     spinlock_t lock;
0324     struct ssusb_mtk *ssusb;
0325     struct device *dev;
0326     void __iomem *mac_base;
0327     void __iomem *ippc_base;
0328     int irq;
0329
0330     struct mtu3_fifo_info tx_fifo;
0331     struct mtu3_fifo_info rx_fifo;
0332
0333     struct mtu3_ep *ep_array;
0334     struct mtu3_ep *in_eps;
0335     struct mtu3_ep *out_eps;
0336     struct mtu3_ep *ep0;
0337     int num_eps;
0338     int slot;
0339     int active_ep;
0340
0341     struct dma_pool *qmu_gpd_pool;
0342     enum mtu3_g_ep0_state ep0_state;
0343     struct usb_gadget g;    /* the gadget */
0344     struct usb_gadget_driver *gadget_driver;
0345     struct mtu3_request ep0_req;
0346     u8 setup_buf[EP0_RESPONSE_BUF];
0347     enum usb_device_speed max_speed;
0348     enum usb_device_speed speed;
0349
0350     unsigned is_active:1;
0351     unsigned may_wakeup:1;
0352     unsigned is_self_powered:1;
0353     unsigned test_mode:1;
0354     unsigned softconnect:1;
0355     unsigned u1_enable:1;
0356     unsigned u2_enable:1;
0357     unsigned u3_capable:1;
0358     unsigned delayed_status:1;
0359     unsigned gen2cp:1;
0360     unsigned connected:1;
0361     unsigned async_callbacks:1;
0362     unsigned separate_fifo:1;
0363
0364     u8 address;
0365     u8 test_mode_nr;
0366     u32 hw_version;
0367 };
0368
0369 static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g)
0370 {
0371     return container_of(g, struct mtu3, g);
0372 }
0373
0374 static inline struct mtu3_request *to_mtu3_request(struct usb_request *req)
0375 {
0376     return req ? container_of(req, struct mtu3_request, request) : NULL;
0377 }
0378
0379 static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep)
0380 {
0381     return ep ? container_of(ep, struct mtu3_ep, ep) : NULL;
0382 }
0383
0384 static inline struct mtu3_request *next_request(struct mtu3_ep *mep)
0385 {
0386     return list_first_entry_or_null(&mep->req_list, struct mtu3_request,
0387                     list);
0388 }
0389
0390 static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data)
0391 {
0392     writel(data, base + offset);
0393 }
0394
0395 static inline u32 mtu3_readl(void __iomem *base, u32 offset)
0396 {
0397     return readl(base + offset);
0398 }
0399
0400 static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits)
0401 {
0402     void __iomem *addr = base + offset;
0403     u32 tmp = readl(addr);
0404
0405     writel((tmp | (bits)), addr);
0406 }
0407
0408 static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits)
0409 {
0410     void __iomem *addr = base + offset;
0411     u32 tmp = readl(addr);
0412
0413     writel((tmp & ~(bits)), addr);
0414 }
0415
0416 int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks);
0417 struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags);
0418 void mtu3_free_request(struct usb_ep *ep, struct usb_request *req);
0419 void mtu3_req_complete(struct mtu3_ep *mep,
0420         struct usb_request *req, int status);
0421
0422 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
0423         int interval, int burst, int mult);
0424 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep);
0425 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set);
0426 void mtu3_start(struct mtu3 *mtu);
0427 void mtu3_stop(struct mtu3 *mtu);
0428 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on);
0429
0430 int mtu3_gadget_setup(struct mtu3 *mtu);
0431 void mtu3_gadget_cleanup(struct mtu3 *mtu);
0432 void mtu3_gadget_reset(struct mtu3 *mtu);
0433 void mtu3_gadget_suspend(struct mtu3 *mtu);
0434 void mtu3_gadget_resume(struct mtu3 *mtu);
0435 void mtu3_gadget_disconnect(struct mtu3 *mtu);
0436
0437 irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu);
0438 extern const struct usb_ep_ops mtu3_ep0_ops;
0439
0440 #endif