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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for the NXP ISP1760 chip
0004  *
0005  * However, the code might contain some bugs. What doesn't work for sure is:
0006  * - ISO
0007  * - OTG
0008  e The interrupt line is configured as active low, level.
0009  *
0010  * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
0011  *
0012  * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
0013  *
0014  * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org>
0015  *
0016  */
0017 #include <linux/gpio/consumer.h>
0018 #include <linux/module.h>
0019 #include <linux/kernel.h>
0020 #include <linux/slab.h>
0021 #include <linux/list.h>
0022 #include <linux/usb.h>
0023 #include <linux/usb/hcd.h>
0024 #include <linux/debugfs.h>
0025 #include <linux/uaccess.h>
0026 #include <linux/io.h>
0027 #include <linux/iopoll.h>
0028 #include <linux/mm.h>
0029 #include <linux/timer.h>
0030 #include <asm/unaligned.h>
0031 #include <asm/cacheflush.h>
0032 
0033 #include "isp1760-core.h"
0034 #include "isp1760-hcd.h"
0035 #include "isp1760-regs.h"
0036 
0037 static struct kmem_cache *qtd_cachep;
0038 static struct kmem_cache *qh_cachep;
0039 static struct kmem_cache *urb_listitem_cachep;
0040 
0041 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
0042         struct isp1760_qtd *qtd);
0043 
0044 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
0045 {
0046     return *(struct isp1760_hcd **)hcd->hcd_priv;
0047 }
0048 
0049 #define dw_to_le32(x)   (cpu_to_le32((__force u32)x))
0050 #define le32_to_dw(x)   ((__force __dw)(le32_to_cpu(x)))
0051 
0052 /* urb state*/
0053 #define DELETE_URB      (0x0008)
0054 #define NO_TRANSFER_ACTIVE  (0xffffffff)
0055 
0056 /* Philips Proprietary Transfer Descriptor (PTD) */
0057 typedef __u32 __bitwise __dw;
0058 struct ptd {
0059     __dw dw0;
0060     __dw dw1;
0061     __dw dw2;
0062     __dw dw3;
0063     __dw dw4;
0064     __dw dw5;
0065     __dw dw6;
0066     __dw dw7;
0067 };
0068 
0069 struct ptd_le32 {
0070     __le32 dw0;
0071     __le32 dw1;
0072     __le32 dw2;
0073     __le32 dw3;
0074     __le32 dw4;
0075     __le32 dw5;
0076     __le32 dw6;
0077     __le32 dw7;
0078 };
0079 
0080 #define PTD_OFFSET      0x0400
0081 #define ISO_PTD_OFFSET      0x0400
0082 #define INT_PTD_OFFSET      0x0800
0083 #define ATL_PTD_OFFSET      0x0c00
0084 #define PAYLOAD_OFFSET      0x1000
0085 
0086 #define ISP_BANK_0      0x00
0087 #define ISP_BANK_1      0x01
0088 #define ISP_BANK_2      0x02
0089 #define ISP_BANK_3      0x03
0090 
0091 #define TO_DW(x)    ((__force __dw)x)
0092 #define TO_U32(x)   ((__force u32)x)
0093 
0094  /* ATL */
0095  /* DW0 */
0096 #define DW0_VALID_BIT           TO_DW(1)
0097 #define FROM_DW0_VALID(x)       (TO_U32(x) & 0x01)
0098 #define TO_DW0_LENGTH(x)        TO_DW((((u32)x) << 3))
0099 #define TO_DW0_MAXPACKET(x)     TO_DW((((u32)x) << 18))
0100 #define TO_DW0_MULTI(x)         TO_DW((((u32)x) << 29))
0101 #define TO_DW0_ENDPOINT(x)      TO_DW((((u32)x) << 31))
0102 /* DW1 */
0103 #define TO_DW1_DEVICE_ADDR(x)       TO_DW((((u32)x) << 3))
0104 #define TO_DW1_PID_TOKEN(x)     TO_DW((((u32)x) << 10))
0105 #define DW1_TRANS_BULK          TO_DW(((u32)2 << 12))
0106 #define DW1_TRANS_INT           TO_DW(((u32)3 << 12))
0107 #define DW1_TRANS_SPLIT         TO_DW(((u32)1 << 14))
0108 #define DW1_SE_USB_LOSPEED      TO_DW(((u32)2 << 16))
0109 #define TO_DW1_PORT_NUM(x)      TO_DW((((u32)x) << 18))
0110 #define TO_DW1_HUB_NUM(x)       TO_DW((((u32)x) << 25))
0111 /* DW2 */
0112 #define TO_DW2_DATA_START_ADDR(x)   TO_DW((((u32)x) << 8))
0113 #define TO_DW2_RL(x)            TO_DW(((x) << 25))
0114 #define FROM_DW2_RL(x)          ((TO_U32(x) >> 25) & 0xf)
0115 /* DW3 */
0116 #define FROM_DW3_NRBYTESTRANSFERRED(x)      TO_U32((x) & 0x3fff)
0117 #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x)  TO_U32((x) & 0x07ff)
0118 #define TO_DW3_NAKCOUNT(x)      TO_DW(((x) << 19))
0119 #define FROM_DW3_NAKCOUNT(x)        ((TO_U32(x) >> 19) & 0xf)
0120 #define TO_DW3_CERR(x)          TO_DW(((x) << 23))
0121 #define FROM_DW3_CERR(x)        ((TO_U32(x) >> 23) & 0x3)
0122 #define TO_DW3_DATA_TOGGLE(x)       TO_DW(((x) << 25))
0123 #define FROM_DW3_DATA_TOGGLE(x)     ((TO_U32(x) >> 25) & 0x1)
0124 #define TO_DW3_PING(x)          TO_DW(((x) << 26))
0125 #define FROM_DW3_PING(x)        ((TO_U32(x) >> 26) & 0x1)
0126 #define DW3_ERROR_BIT           TO_DW((1 << 28))
0127 #define DW3_BABBLE_BIT          TO_DW((1 << 29))
0128 #define DW3_HALT_BIT            TO_DW((1 << 30))
0129 #define DW3_ACTIVE_BIT          TO_DW((1 << 31))
0130 #define FROM_DW3_ACTIVE(x)      ((TO_U32(x) >> 31) & 0x01)
0131 
0132 #define INT_UNDERRUN            (1 << 2)
0133 #define INT_BABBLE          (1 << 1)
0134 #define INT_EXACT           (1 << 0)
0135 
0136 #define SETUP_PID   (2)
0137 #define IN_PID      (1)
0138 #define OUT_PID     (0)
0139 
0140 /* Errata 1 */
0141 #define RL_COUNTER  (0)
0142 #define NAK_COUNTER (0)
0143 #define ERR_COUNTER (3)
0144 
0145 struct isp1760_qtd {
0146     u8 packet_type;
0147     void *data_buffer;
0148     u32 payload_addr;
0149 
0150     /* the rest is HCD-private */
0151     struct list_head qtd_list;
0152     struct urb *urb;
0153     size_t length;
0154     size_t actual_length;
0155 
0156     /* QTD_ENQUEUED:    waiting for transfer (inactive) */
0157     /* QTD_PAYLOAD_ALLOC:   chip mem has been allocated for payload */
0158     /* QTD_XFER_STARTED:    valid ptd has been written to isp176x - only
0159                 interrupt handler may touch this qtd! */
0160     /* QTD_XFER_COMPLETE:   payload has been transferred successfully */
0161     /* QTD_RETIRE:      transfer error/abort qtd */
0162 #define QTD_ENQUEUED        0
0163 #define QTD_PAYLOAD_ALLOC   1
0164 #define QTD_XFER_STARTED    2
0165 #define QTD_XFER_COMPLETE   3
0166 #define QTD_RETIRE      4
0167     u32 status;
0168 };
0169 
0170 /* Queue head, one for each active endpoint */
0171 struct isp1760_qh {
0172     struct list_head qh_list;
0173     struct list_head qtd_list;
0174     u32 toggle;
0175     u32 ping;
0176     int slot;
0177     int tt_buffer_dirty;    /* See USB2.0 spec section 11.17.5 */
0178 };
0179 
0180 struct urb_listitem {
0181     struct list_head urb_list;
0182     struct urb *urb;
0183 };
0184 
0185 static const u32 isp176x_hc_portsc1_fields[] = {
0186     [PORT_OWNER]        = BIT(13),
0187     [PORT_POWER]        = BIT(12),
0188     [PORT_LSTATUS]      = BIT(10),
0189     [PORT_RESET]        = BIT(8),
0190     [PORT_SUSPEND]      = BIT(7),
0191     [PORT_RESUME]       = BIT(6),
0192     [PORT_PE]       = BIT(2),
0193     [PORT_CSC]      = BIT(1),
0194     [PORT_CONNECT]      = BIT(0),
0195 };
0196 
0197 /*
0198  * Access functions for isp176x registers regmap fields
0199  */
0200 static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field)
0201 {
0202     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0203 
0204     return isp1760_field_read(priv->fields, field);
0205 }
0206 
0207 /*
0208  * We need, in isp176x, to write directly the values to the portsc1
0209  * register so it will make the other values to trigger.
0210  */
0211 static void isp1760_hcd_portsc1_set_clear(struct isp1760_hcd *priv, u32 field,
0212                       u32 val)
0213 {
0214     u32 bit = isp176x_hc_portsc1_fields[field];
0215     u16 portsc1_reg = priv->is_isp1763 ? ISP1763_HC_PORTSC1 :
0216         ISP176x_HC_PORTSC1;
0217     u32 port_status = readl(priv->base + portsc1_reg);
0218 
0219     if (val)
0220         writel(port_status | bit, priv->base + portsc1_reg);
0221     else
0222         writel(port_status & ~bit, priv->base + portsc1_reg);
0223 }
0224 
0225 static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val)
0226 {
0227     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0228 
0229     if (unlikely((field >= PORT_OWNER && field <= PORT_CONNECT)))
0230         return isp1760_hcd_portsc1_set_clear(priv, field, val);
0231 
0232     isp1760_field_write(priv->fields, field, val);
0233 }
0234 
0235 static void isp1760_hcd_set(struct usb_hcd *hcd, u32 field)
0236 {
0237     isp1760_hcd_write(hcd, field, 0xFFFFFFFF);
0238 }
0239 
0240 static void isp1760_hcd_clear(struct usb_hcd *hcd, u32 field)
0241 {
0242     isp1760_hcd_write(hcd, field, 0);
0243 }
0244 
0245 static int isp1760_hcd_set_and_wait(struct usb_hcd *hcd, u32 field,
0246                     u32 timeout_us)
0247 {
0248     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0249     u32 val;
0250 
0251     isp1760_hcd_set(hcd, field);
0252 
0253     return regmap_field_read_poll_timeout(priv->fields[field], val,
0254                           val, 0, timeout_us);
0255 }
0256 
0257 static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field,
0258                      u32 timeout_us)
0259 {
0260     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0261     u32 val;
0262 
0263     isp1760_hcd_set(hcd, field);
0264 
0265     return regmap_field_read_poll_timeout(priv->fields[field], val,
0266                           !val, 0, timeout_us);
0267 }
0268 
0269 static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field,
0270                       u32 timeout_us)
0271 {
0272     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0273     u32 val;
0274 
0275     isp1760_hcd_clear(hcd, field);
0276 
0277     return regmap_field_read_poll_timeout(priv->fields[field], val,
0278                           !val, 0, timeout_us);
0279 }
0280 
0281 static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field)
0282 {
0283     return !!isp1760_hcd_read(hcd, field);
0284 }
0285 
0286 static bool isp1760_hcd_ppc_is_set(struct usb_hcd *hcd)
0287 {
0288     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0289 
0290     if (priv->is_isp1763)
0291         return true;
0292 
0293     return isp1760_hcd_is_set(hcd, HCS_PPC);
0294 }
0295 
0296 static u32 isp1760_hcd_n_ports(struct usb_hcd *hcd)
0297 {
0298     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0299 
0300     if (priv->is_isp1763)
0301         return 1;
0302 
0303     return isp1760_hcd_read(hcd, HCS_N_PORTS);
0304 }
0305 
0306 /*
0307  * Access functions for isp176x memory (offset >= 0x0400).
0308  *
0309  * bank_reads8() reads memory locations prefetched by an earlier write to
0310  * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
0311  * bank optimizations, you should use the more generic mem_read() below.
0312  *
0313  * For access to ptd memory, use the specialized ptd_read() and ptd_write()
0314  * below.
0315  *
0316  * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
0317  * doesn't quite work because some people have to enforce 32-bit access
0318  */
0319 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
0320                             __u32 *dst, u32 bytes)
0321 {
0322     __u32 __iomem *src;
0323     u32 val;
0324     __u8 *src_byteptr;
0325     __u8 *dst_byteptr;
0326 
0327     src = src_base + (bank_addr | src_offset);
0328 
0329     if (src_offset < PAYLOAD_OFFSET) {
0330         while (bytes >= 4) {
0331             *dst = readl_relaxed(src);
0332             bytes -= 4;
0333             src++;
0334             dst++;
0335         }
0336     } else {
0337         while (bytes >= 4) {
0338             *dst = __raw_readl(src);
0339             bytes -= 4;
0340             src++;
0341             dst++;
0342         }
0343     }
0344 
0345     if (!bytes)
0346         return;
0347 
0348     /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
0349      * allocated.
0350      */
0351     if (src_offset < PAYLOAD_OFFSET)
0352         val = readl_relaxed(src);
0353     else
0354         val = __raw_readl(src);
0355 
0356     dst_byteptr = (void *) dst;
0357     src_byteptr = (void *) &val;
0358     while (bytes > 0) {
0359         *dst_byteptr = *src_byteptr;
0360         dst_byteptr++;
0361         src_byteptr++;
0362         bytes--;
0363     }
0364 }
0365 
0366 static void isp1760_mem_read(struct usb_hcd *hcd, u32 src_offset, void *dst,
0367                  u32 bytes)
0368 {
0369     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0370 
0371     isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset);
0372     ndelay(100);
0373 
0374     bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes);
0375 }
0376 
0377 /*
0378  * ISP1763 does not have the banks direct host controller memory access,
0379  * needs to use the HC_DATA register. Add data read/write according to this,
0380  * and also adjust 16bit access.
0381  */
0382 static void isp1763_mem_read(struct usb_hcd *hcd, u16 srcaddr,
0383                  u16 *dstptr, u32 bytes)
0384 {
0385     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0386 
0387     /* Write the starting device address to the hcd memory register */
0388     isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, srcaddr);
0389     ndelay(100); /* Delay between consecutive access */
0390 
0391     /* As long there are at least 16-bit to read ... */
0392     while (bytes >= 2) {
0393         *dstptr = __raw_readw(priv->base + ISP1763_HC_DATA);
0394         bytes -= 2;
0395         dstptr++;
0396     }
0397 
0398     /* If there are no more bytes to read, return */
0399     if (bytes <= 0)
0400         return;
0401 
0402     *((u8 *)dstptr) = (u8)(readw(priv->base + ISP1763_HC_DATA) & 0xFF);
0403 }
0404 
0405 static void mem_read(struct usb_hcd *hcd, u32 src_offset, __u32 *dst,
0406              u32 bytes)
0407 {
0408     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0409 
0410     if (!priv->is_isp1763)
0411         return isp1760_mem_read(hcd, src_offset, (u16 *)dst, bytes);
0412 
0413     isp1763_mem_read(hcd, (u16)src_offset, (u16 *)dst, bytes);
0414 }
0415 
0416 static void isp1760_mem_write(void __iomem *dst_base, u32 dst_offset,
0417                   __u32 const *src, u32 bytes)
0418 {
0419     __u32 __iomem *dst;
0420 
0421     dst = dst_base + dst_offset;
0422 
0423     if (dst_offset < PAYLOAD_OFFSET) {
0424         while (bytes >= 4) {
0425             writel_relaxed(*src, dst);
0426             bytes -= 4;
0427             src++;
0428             dst++;
0429         }
0430     } else {
0431         while (bytes >= 4) {
0432             __raw_writel(*src, dst);
0433             bytes -= 4;
0434             src++;
0435             dst++;
0436         }
0437     }
0438 
0439     if (!bytes)
0440         return;
0441     /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
0442      * extra bytes should not be read by the HW.
0443      */
0444 
0445     if (dst_offset < PAYLOAD_OFFSET)
0446         writel_relaxed(*src, dst);
0447     else
0448         __raw_writel(*src, dst);
0449 }
0450 
0451 static void isp1763_mem_write(struct usb_hcd *hcd, u16 dstaddr, u16 *src,
0452                   u32 bytes)
0453 {
0454     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0455 
0456     /* Write the starting device address to the hcd memory register */
0457     isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, dstaddr);
0458     ndelay(100); /* Delay between consecutive access */
0459 
0460     while (bytes >= 2) {
0461         /* Get and write the data; then adjust the data ptr and len */
0462         __raw_writew(*src, priv->base + ISP1763_HC_DATA);
0463         bytes -= 2;
0464         src++;
0465     }
0466 
0467     /* If there are no more bytes to process, return */
0468     if (bytes <= 0)
0469         return;
0470 
0471     /*
0472      * The only way to get here is if there is a single byte left,
0473      * get it and write it to the data reg;
0474      */
0475     writew(*((u8 *)src), priv->base + ISP1763_HC_DATA);
0476 }
0477 
0478 static void mem_write(struct usb_hcd *hcd, u32 dst_offset, __u32 *src,
0479               u32 bytes)
0480 {
0481     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0482 
0483     if (!priv->is_isp1763)
0484         return isp1760_mem_write(priv->base, dst_offset, src, bytes);
0485 
0486     isp1763_mem_write(hcd, dst_offset, (u16 *)src, bytes);
0487 }
0488 
0489 /*
0490  * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
0491  * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
0492  */
0493 static void isp1760_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
0494                  struct ptd *ptd)
0495 {
0496     u16 src_offset = ptd_offset + slot * sizeof(*ptd);
0497     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0498 
0499     isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset);
0500     ndelay(90);
0501 
0502     bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd,
0503             sizeof(*ptd));
0504 }
0505 
0506 static void isp1763_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
0507                  struct ptd *ptd)
0508 {
0509     u16 src_offset = ptd_offset + slot * sizeof(*ptd);
0510     struct ptd_le32 le32_ptd;
0511 
0512     isp1763_mem_read(hcd, src_offset, (u16 *)&le32_ptd, sizeof(le32_ptd));
0513     /* Normalize the data obtained */
0514     ptd->dw0 = le32_to_dw(le32_ptd.dw0);
0515     ptd->dw1 = le32_to_dw(le32_ptd.dw1);
0516     ptd->dw2 = le32_to_dw(le32_ptd.dw2);
0517     ptd->dw3 = le32_to_dw(le32_ptd.dw3);
0518     ptd->dw4 = le32_to_dw(le32_ptd.dw4);
0519     ptd->dw5 = le32_to_dw(le32_ptd.dw5);
0520     ptd->dw6 = le32_to_dw(le32_ptd.dw6);
0521     ptd->dw7 = le32_to_dw(le32_ptd.dw7);
0522 }
0523 
0524 static void ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
0525              struct ptd *ptd)
0526 {
0527     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0528 
0529     if (!priv->is_isp1763)
0530         return isp1760_ptd_read(hcd, ptd_offset, slot, ptd);
0531 
0532     isp1763_ptd_read(hcd, ptd_offset, slot, ptd);
0533 }
0534 
0535 static void isp1763_ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
0536                   struct ptd *cpu_ptd)
0537 {
0538     u16 dst_offset = ptd_offset + slot * sizeof(*cpu_ptd);
0539     struct ptd_le32 ptd;
0540 
0541     ptd.dw0 = dw_to_le32(cpu_ptd->dw0);
0542     ptd.dw1 = dw_to_le32(cpu_ptd->dw1);
0543     ptd.dw2 = dw_to_le32(cpu_ptd->dw2);
0544     ptd.dw3 = dw_to_le32(cpu_ptd->dw3);
0545     ptd.dw4 = dw_to_le32(cpu_ptd->dw4);
0546     ptd.dw5 = dw_to_le32(cpu_ptd->dw5);
0547     ptd.dw6 = dw_to_le32(cpu_ptd->dw6);
0548     ptd.dw7 = dw_to_le32(cpu_ptd->dw7);
0549 
0550     isp1763_mem_write(hcd, dst_offset,  (u16 *)&ptd.dw0,
0551               8 * sizeof(ptd.dw0));
0552 }
0553 
0554 static void isp1760_ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
0555                   struct ptd *ptd)
0556 {
0557     u32 dst_offset = ptd_offset + slot * sizeof(*ptd);
0558 
0559     /*
0560      * Make sure dw0 gets written last (after other dw's and after payload)
0561      *  since it contains the enable bit
0562      */
0563     isp1760_mem_write(base, dst_offset + sizeof(ptd->dw0),
0564               (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1));
0565     wmb();
0566     isp1760_mem_write(base, dst_offset, (__force u32 *)&ptd->dw0,
0567               sizeof(ptd->dw0));
0568 }
0569 
0570 static void ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
0571               struct ptd *ptd)
0572 {
0573     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0574 
0575     if (!priv->is_isp1763)
0576         return isp1760_ptd_write(priv->base, ptd_offset, slot, ptd);
0577 
0578     isp1763_ptd_write(hcd, ptd_offset, slot, ptd);
0579 }
0580 
0581 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
0582 static void init_memory(struct isp1760_hcd *priv)
0583 {
0584     const struct isp1760_memory_layout *mem = priv->memory_layout;
0585     int i, j, curr;
0586     u32 payload_addr;
0587 
0588     payload_addr = PAYLOAD_OFFSET;
0589 
0590     for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++, curr += j) {
0591         for (j = 0; j < mem->blocks[i]; j++) {
0592             priv->memory_pool[curr + j].start = payload_addr;
0593             priv->memory_pool[curr + j].size = mem->blocks_size[i];
0594             priv->memory_pool[curr + j].free = 1;
0595             payload_addr += priv->memory_pool[curr + j].size;
0596         }
0597     }
0598 
0599     WARN_ON(payload_addr - priv->memory_pool[0].start >
0600         mem->payload_area_size);
0601 }
0602 
0603 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
0604 {
0605     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0606     const struct isp1760_memory_layout *mem = priv->memory_layout;
0607     int i;
0608 
0609     WARN_ON(qtd->payload_addr);
0610 
0611     if (!qtd->length)
0612         return;
0613 
0614     for (i = 0; i < mem->payload_blocks; i++) {
0615         if (priv->memory_pool[i].size >= qtd->length &&
0616                 priv->memory_pool[i].free) {
0617             priv->memory_pool[i].free = 0;
0618             qtd->payload_addr = priv->memory_pool[i].start;
0619             return;
0620         }
0621     }
0622 }
0623 
0624 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
0625 {
0626     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0627     const struct isp1760_memory_layout *mem = priv->memory_layout;
0628     int i;
0629 
0630     if (!qtd->payload_addr)
0631         return;
0632 
0633     for (i = 0; i < mem->payload_blocks; i++) {
0634         if (priv->memory_pool[i].start == qtd->payload_addr) {
0635             WARN_ON(priv->memory_pool[i].free);
0636             priv->memory_pool[i].free = 1;
0637             qtd->payload_addr = 0;
0638             return;
0639         }
0640     }
0641 
0642     dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
0643                         __func__, qtd->payload_addr);
0644     WARN_ON(1);
0645     qtd->payload_addr = 0;
0646 }
0647 
0648 /* reset a non-running (STS_HALT == 1) controller */
0649 static int ehci_reset(struct usb_hcd *hcd)
0650 {
0651     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0652 
0653     hcd->state = HC_STATE_HALT;
0654     priv->next_statechange = jiffies;
0655 
0656     return isp1760_hcd_set_and_wait_swap(hcd, CMD_RESET, 250 * 1000);
0657 }
0658 
0659 static struct isp1760_qh *qh_alloc(gfp_t flags)
0660 {
0661     struct isp1760_qh *qh;
0662 
0663     qh = kmem_cache_zalloc(qh_cachep, flags);
0664     if (!qh)
0665         return NULL;
0666 
0667     INIT_LIST_HEAD(&qh->qh_list);
0668     INIT_LIST_HEAD(&qh->qtd_list);
0669     qh->slot = -1;
0670 
0671     return qh;
0672 }
0673 
0674 static void qh_free(struct isp1760_qh *qh)
0675 {
0676     WARN_ON(!list_empty(&qh->qtd_list));
0677     WARN_ON(qh->slot > -1);
0678     kmem_cache_free(qh_cachep, qh);
0679 }
0680 
0681 /* one-time init, only for memory state */
0682 static int priv_init(struct usb_hcd *hcd)
0683 {
0684     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0685     u32 isoc_cache;
0686     u32 isoc_thres;
0687     int i;
0688 
0689     spin_lock_init(&priv->lock);
0690 
0691     for (i = 0; i < QH_END; i++)
0692         INIT_LIST_HEAD(&priv->qh_list[i]);
0693 
0694     /*
0695      * hw default: 1K periodic list heads, one per frame.
0696      * periodic_size can shrink by USBCMD update if hcc_params allows.
0697      */
0698     priv->periodic_size = DEFAULT_I_TDPS;
0699 
0700     if (priv->is_isp1763) {
0701         priv->i_thresh = 2;
0702         return 0;
0703     }
0704 
0705     /* controllers may cache some of the periodic schedule ... */
0706     isoc_cache = isp1760_hcd_read(hcd, HCC_ISOC_CACHE);
0707     isoc_thres = isp1760_hcd_read(hcd, HCC_ISOC_THRES);
0708 
0709     /* full frame cache */
0710     if (isoc_cache)
0711         priv->i_thresh = 8;
0712     else /* N microframes cached */
0713         priv->i_thresh = 2 + isoc_thres;
0714 
0715     return 0;
0716 }
0717 
0718 static int isp1760_hc_setup(struct usb_hcd *hcd)
0719 {
0720     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0721     u32 atx_reset;
0722     int result;
0723     u32 scratch;
0724     u32 pattern;
0725 
0726     if (priv->is_isp1763)
0727         pattern = 0xcafe;
0728     else
0729         pattern = 0xdeadcafe;
0730 
0731     isp1760_hcd_write(hcd, HC_SCRATCH, pattern);
0732 
0733     /*
0734      * we do not care about the read value here we just want to
0735      * change bus pattern.
0736      */
0737     isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH);
0738     scratch = isp1760_hcd_read(hcd, HC_SCRATCH);
0739     if (scratch != pattern) {
0740         dev_err(hcd->self.controller, "Scratch test failed. 0x%08x\n",
0741             scratch);
0742         return -ENODEV;
0743     }
0744 
0745     /*
0746      * The RESET_HC bit in the SW_RESET register is supposed to reset the
0747      * host controller without touching the CPU interface registers, but at
0748      * least on the ISP1761 it seems to behave as the RESET_ALL bit and
0749      * reset the whole device. We thus can't use it here, so let's reset
0750      * the host controller through the EHCI USB Command register. The device
0751      * has been reset in core code anyway, so this shouldn't matter.
0752      */
0753     isp1760_hcd_clear(hcd, ISO_BUF_FILL);
0754     isp1760_hcd_clear(hcd, INT_BUF_FILL);
0755     isp1760_hcd_clear(hcd, ATL_BUF_FILL);
0756 
0757     isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP);
0758     isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP);
0759     isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP);
0760 
0761     result = ehci_reset(hcd);
0762     if (result)
0763         return result;
0764 
0765     /* Step 11 passed */
0766 
0767     /* ATL reset */
0768     if (priv->is_isp1763)
0769         atx_reset = SW_RESET_RESET_ATX;
0770     else
0771         atx_reset = ALL_ATX_RESET;
0772 
0773     isp1760_hcd_set(hcd, atx_reset);
0774     mdelay(10);
0775     isp1760_hcd_clear(hcd, atx_reset);
0776 
0777     if (priv->is_isp1763) {
0778         isp1760_hcd_set(hcd, HW_OTG_DISABLE);
0779         isp1760_hcd_set(hcd, HW_SW_SEL_HC_DC_CLEAR);
0780         isp1760_hcd_set(hcd, HW_HC_2_DIS_CLEAR);
0781         mdelay(10);
0782 
0783         isp1760_hcd_set(hcd, HW_INTF_LOCK);
0784     }
0785 
0786     isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE);
0787     isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE);
0788 
0789     return priv_init(hcd);
0790 }
0791 
0792 static u32 base_to_chip(u32 base)
0793 {
0794     return ((base - 0x400) >> 3);
0795 }
0796 
0797 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
0798 {
0799     struct urb *urb;
0800 
0801     if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
0802         return 1;
0803 
0804     urb = qtd->urb;
0805     qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
0806     return (qtd->urb != urb);
0807 }
0808 
0809 /* magic numbers that can affect system performance */
0810 #define EHCI_TUNE_CERR      3   /* 0-3 qtd retries; 0 == don't stop */
0811 #define EHCI_TUNE_RL_HS     4   /* nak throttle; see 4.9 */
0812 #define EHCI_TUNE_RL_TT     0
0813 #define EHCI_TUNE_MULT_HS   1   /* 1-3 transactions/uframe; 4.10.3 */
0814 #define EHCI_TUNE_MULT_TT   1
0815 #define EHCI_TUNE_FLS       2   /* (small) 256 frame schedule */
0816 
0817 static void create_ptd_atl(struct isp1760_qh *qh,
0818             struct isp1760_qtd *qtd, struct ptd *ptd)
0819 {
0820     u32 maxpacket;
0821     u32 multi;
0822     u32 rl = RL_COUNTER;
0823     u32 nak = NAK_COUNTER;
0824 
0825     memset(ptd, 0, sizeof(*ptd));
0826 
0827     /* according to 3.6.2, max packet len can not be > 0x400 */
0828     maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe);
0829     multi =  1 + ((maxpacket >> 11) & 0x3);
0830     maxpacket &= 0x7ff;
0831 
0832     /* DW0 */
0833     ptd->dw0 = DW0_VALID_BIT;
0834     ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
0835     ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
0836     ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
0837 
0838     /* DW1 */
0839     ptd->dw1 = TO_DW((usb_pipeendpoint(qtd->urb->pipe) >> 1));
0840     ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
0841     ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
0842 
0843     if (usb_pipebulk(qtd->urb->pipe))
0844         ptd->dw1 |= DW1_TRANS_BULK;
0845     else if  (usb_pipeint(qtd->urb->pipe))
0846         ptd->dw1 |= DW1_TRANS_INT;
0847 
0848     if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
0849         /* split transaction */
0850 
0851         ptd->dw1 |= DW1_TRANS_SPLIT;
0852         if (qtd->urb->dev->speed == USB_SPEED_LOW)
0853             ptd->dw1 |= DW1_SE_USB_LOSPEED;
0854 
0855         ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
0856         ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
0857 
0858         /* SE bit for Split INT transfers */
0859         if (usb_pipeint(qtd->urb->pipe) &&
0860                 (qtd->urb->dev->speed == USB_SPEED_LOW))
0861             ptd->dw1 |= DW1_SE_USB_LOSPEED;
0862 
0863         rl = 0;
0864         nak = 0;
0865     } else {
0866         ptd->dw0 |= TO_DW0_MULTI(multi);
0867         if (usb_pipecontrol(qtd->urb->pipe) ||
0868                         usb_pipebulk(qtd->urb->pipe))
0869             ptd->dw3 |= TO_DW3_PING(qh->ping);
0870     }
0871     /* DW2 */
0872     ptd->dw2 = 0;
0873     ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
0874     ptd->dw2 |= TO_DW2_RL(rl);
0875 
0876     /* DW3 */
0877     ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
0878     ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
0879     if (usb_pipecontrol(qtd->urb->pipe)) {
0880         if (qtd->data_buffer == qtd->urb->setup_packet)
0881             ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
0882         else if (last_qtd_of_urb(qtd, qh))
0883             ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
0884     }
0885 
0886     ptd->dw3 |= DW3_ACTIVE_BIT;
0887     /* Cerr */
0888     ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
0889 }
0890 
0891 static void transform_add_int(struct isp1760_qh *qh,
0892             struct isp1760_qtd *qtd, struct ptd *ptd)
0893 {
0894     u32 usof;
0895     u32 period;
0896 
0897     /*
0898      * Most of this is guessing. ISP1761 datasheet is quite unclear, and
0899      * the algorithm from the original Philips driver code, which was
0900      * pretty much used in this driver before as well, is quite horrendous
0901      * and, i believe, incorrect. The code below follows the datasheet and
0902      * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
0903      * more reliable this way (fingers crossed...).
0904      */
0905 
0906     if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
0907         /* urb->interval is in units of microframes (1/8 ms) */
0908         period = qtd->urb->interval >> 3;
0909 
0910         if (qtd->urb->interval > 4)
0911             usof = 0x01; /* One bit set =>
0912                         interval 1 ms * uFrame-match */
0913         else if (qtd->urb->interval > 2)
0914             usof = 0x22; /* Two bits set => interval 1/2 ms */
0915         else if (qtd->urb->interval > 1)
0916             usof = 0x55; /* Four bits set => interval 1/4 ms */
0917         else
0918             usof = 0xff; /* All bits set => interval 1/8 ms */
0919     } else {
0920         /* urb->interval is in units of frames (1 ms) */
0921         period = qtd->urb->interval;
0922         usof = 0x0f;        /* Execute Start Split on any of the
0923                        four first uFrames */
0924 
0925         /*
0926          * First 8 bits in dw5 is uSCS and "specifies which uSOF the
0927          * complete split needs to be sent. Valid only for IN." Also,
0928          * "All bits can be set to one for every transfer." (p 82,
0929          * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
0930          * that number come from? 0xff seems to work fine...
0931          */
0932         /* ptd->dw5 = 0x1c; */
0933         ptd->dw5 = TO_DW(0xff); /* Execute Complete Split on any uFrame */
0934     }
0935 
0936     period = period >> 1;/* Ensure equal or shorter period than requested */
0937     period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
0938 
0939     ptd->dw2 |= TO_DW(period);
0940     ptd->dw4 = TO_DW(usof);
0941 }
0942 
0943 static void create_ptd_int(struct isp1760_qh *qh,
0944             struct isp1760_qtd *qtd, struct ptd *ptd)
0945 {
0946     create_ptd_atl(qh, qtd, ptd);
0947     transform_add_int(qh, qtd, ptd);
0948 }
0949 
0950 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
0951 __releases(priv->lock)
0952 __acquires(priv->lock)
0953 {
0954     struct isp1760_hcd *priv = hcd_to_priv(hcd);
0955 
0956     if (!urb->unlinked) {
0957         if (urb->status == -EINPROGRESS)
0958             urb->status = 0;
0959     }
0960 
0961     if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
0962         void *ptr;
0963         for (ptr = urb->transfer_buffer;
0964              ptr < urb->transfer_buffer + urb->transfer_buffer_length;
0965              ptr += PAGE_SIZE)
0966             flush_dcache_page(virt_to_page(ptr));
0967     }
0968 
0969     /* complete() can reenter this HCD */
0970     usb_hcd_unlink_urb_from_ep(hcd, urb);
0971     spin_unlock(&priv->lock);
0972     usb_hcd_giveback_urb(hcd, urb, urb->status);
0973     spin_lock(&priv->lock);
0974 }
0975 
0976 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
0977                                 u8 packet_type)
0978 {
0979     struct isp1760_qtd *qtd;
0980 
0981     qtd = kmem_cache_zalloc(qtd_cachep, flags);
0982     if (!qtd)
0983         return NULL;
0984 
0985     INIT_LIST_HEAD(&qtd->qtd_list);
0986     qtd->urb = urb;
0987     qtd->packet_type = packet_type;
0988     qtd->status = QTD_ENQUEUED;
0989     qtd->actual_length = 0;
0990 
0991     return qtd;
0992 }
0993 
0994 static void qtd_free(struct isp1760_qtd *qtd)
0995 {
0996     WARN_ON(qtd->payload_addr);
0997     kmem_cache_free(qtd_cachep, qtd);
0998 }
0999 
1000 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
1001                 struct isp1760_slotinfo *slots,
1002                 struct isp1760_qtd *qtd, struct isp1760_qh *qh,
1003                 struct ptd *ptd)
1004 {
1005     struct isp1760_hcd *priv = hcd_to_priv(hcd);
1006     const struct isp1760_memory_layout *mem = priv->memory_layout;
1007     int skip_map;
1008 
1009     WARN_ON((slot < 0) || (slot > mem->slot_num - 1));
1010     WARN_ON(qtd->length && !qtd->payload_addr);
1011     WARN_ON(slots[slot].qtd);
1012     WARN_ON(slots[slot].qh);
1013     WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
1014 
1015     if (priv->is_isp1763)
1016         ndelay(100);
1017 
1018     /* Make sure done map has not triggered from some unlinked transfer */
1019     if (ptd_offset == ATL_PTD_OFFSET) {
1020         skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP);
1021         isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP,
1022                   skip_map | (1 << slot));
1023         priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP);
1024         priv->atl_done_map &= ~(1 << slot);
1025     } else {
1026         skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP);
1027         isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP,
1028                   skip_map | (1 << slot));
1029         priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP);
1030         priv->int_done_map &= ~(1 << slot);
1031     }
1032 
1033     skip_map &= ~(1 << slot);
1034     qh->slot = slot;
1035     qtd->status = QTD_XFER_STARTED;
1036     slots[slot].timestamp = jiffies;
1037     slots[slot].qtd = qtd;
1038     slots[slot].qh = qh;
1039     ptd_write(hcd, ptd_offset, slot, ptd);
1040 
1041     if (ptd_offset == ATL_PTD_OFFSET)
1042         isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map);
1043     else
1044         isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map);
1045 }
1046 
1047 static int is_short_bulk(struct isp1760_qtd *qtd)
1048 {
1049     return (usb_pipebulk(qtd->urb->pipe) &&
1050                     (qtd->actual_length < qtd->length));
1051 }
1052 
1053 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
1054                         struct list_head *urb_list)
1055 {
1056     struct isp1760_qtd *qtd, *qtd_next;
1057     struct urb_listitem *urb_listitem;
1058     int last_qtd;
1059 
1060     list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
1061         if (qtd->status < QTD_XFER_COMPLETE)
1062             break;
1063 
1064         last_qtd = last_qtd_of_urb(qtd, qh);
1065 
1066         if ((!last_qtd) && (qtd->status == QTD_RETIRE))
1067             qtd_next->status = QTD_RETIRE;
1068 
1069         if (qtd->status == QTD_XFER_COMPLETE) {
1070             if (qtd->actual_length) {
1071                 switch (qtd->packet_type) {
1072                 case IN_PID:
1073                     mem_read(hcd, qtd->payload_addr,
1074                          qtd->data_buffer,
1075                          qtd->actual_length);
1076                     fallthrough;
1077                 case OUT_PID:
1078                     qtd->urb->actual_length +=
1079                             qtd->actual_length;
1080                     fallthrough;
1081                 case SETUP_PID:
1082                     break;
1083                 }
1084             }
1085 
1086             if (is_short_bulk(qtd)) {
1087                 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
1088                     qtd->urb->status = -EREMOTEIO;
1089                 if (!last_qtd)
1090                     qtd_next->status = QTD_RETIRE;
1091             }
1092         }
1093 
1094         if (qtd->payload_addr)
1095             free_mem(hcd, qtd);
1096 
1097         if (last_qtd) {
1098             if ((qtd->status == QTD_RETIRE) &&
1099                     (qtd->urb->status == -EINPROGRESS))
1100                 qtd->urb->status = -EPIPE;
1101             /* Defer calling of urb_done() since it releases lock */
1102             urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
1103                                 GFP_ATOMIC);
1104             if (unlikely(!urb_listitem))
1105                 break; /* Try again on next call */
1106             urb_listitem->urb = qtd->urb;
1107             list_add_tail(&urb_listitem->urb_list, urb_list);
1108         }
1109 
1110         list_del(&qtd->qtd_list);
1111         qtd_free(qtd);
1112     }
1113 }
1114 
1115 #define ENQUEUE_DEPTH   2
1116 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
1117 {
1118     struct isp1760_hcd *priv = hcd_to_priv(hcd);
1119     const struct isp1760_memory_layout *mem = priv->memory_layout;
1120     int slot_num = mem->slot_num;
1121     int ptd_offset;
1122     struct isp1760_slotinfo *slots;
1123     int curr_slot, free_slot;
1124     int n;
1125     struct ptd ptd;
1126     struct isp1760_qtd *qtd;
1127 
1128     if (unlikely(list_empty(&qh->qtd_list))) {
1129         WARN_ON(1);
1130         return;
1131     }
1132 
1133     /* Make sure this endpoint's TT buffer is clean before queueing ptds */
1134     if (qh->tt_buffer_dirty)
1135         return;
1136 
1137     if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
1138                             qtd_list)->urb->pipe)) {
1139         ptd_offset = INT_PTD_OFFSET;
1140         slots = priv->int_slots;
1141     } else {
1142         ptd_offset = ATL_PTD_OFFSET;
1143         slots = priv->atl_slots;
1144     }
1145 
1146     free_slot = -1;
1147     for (curr_slot = 0; curr_slot < slot_num; curr_slot++) {
1148         if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
1149             free_slot = curr_slot;
1150         if (slots[curr_slot].qh == qh)
1151             break;
1152     }
1153 
1154     n = 0;
1155     list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
1156         if (qtd->status == QTD_ENQUEUED) {
1157             WARN_ON(qtd->payload_addr);
1158             alloc_mem(hcd, qtd);
1159             if ((qtd->length) && (!qtd->payload_addr))
1160                 break;
1161 
1162             if (qtd->length && (qtd->packet_type == SETUP_PID ||
1163                         qtd->packet_type == OUT_PID)) {
1164                 mem_write(hcd, qtd->payload_addr,
1165                       qtd->data_buffer, qtd->length);
1166             }
1167 
1168             qtd->status = QTD_PAYLOAD_ALLOC;
1169         }
1170 
1171         if (qtd->status == QTD_PAYLOAD_ALLOC) {
1172 /*
1173             if ((curr_slot > 31) && (free_slot == -1))
1174                 dev_dbg(hcd->self.controller, "%s: No slot "
1175                     "available for transfer\n", __func__);
1176 */
1177             /* Start xfer for this endpoint if not already done */
1178             if ((curr_slot > slot_num - 1) && (free_slot > -1)) {
1179                 if (usb_pipeint(qtd->urb->pipe))
1180                     create_ptd_int(qh, qtd, &ptd);
1181                 else
1182                     create_ptd_atl(qh, qtd, &ptd);
1183 
1184                 start_bus_transfer(hcd, ptd_offset, free_slot,
1185                             slots, qtd, qh, &ptd);
1186                 curr_slot = free_slot;
1187             }
1188 
1189             n++;
1190             if (n >= ENQUEUE_DEPTH)
1191                 break;
1192         }
1193     }
1194 }
1195 
1196 static void schedule_ptds(struct usb_hcd *hcd)
1197 {
1198     struct isp1760_hcd *priv;
1199     struct isp1760_qh *qh, *qh_next;
1200     struct list_head *ep_queue;
1201     LIST_HEAD(urb_list);
1202     struct urb_listitem *urb_listitem, *urb_listitem_next;
1203     int i;
1204 
1205     if (!hcd) {
1206         WARN_ON(1);
1207         return;
1208     }
1209 
1210     priv = hcd_to_priv(hcd);
1211 
1212     /*
1213      * check finished/retired xfers, transfer payloads, call urb_done()
1214      */
1215     for (i = 0; i < QH_END; i++) {
1216         ep_queue = &priv->qh_list[i];
1217         list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
1218             collect_qtds(hcd, qh, &urb_list);
1219             if (list_empty(&qh->qtd_list))
1220                 list_del(&qh->qh_list);
1221         }
1222     }
1223 
1224     list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
1225                                 urb_list) {
1226         isp1760_urb_done(hcd, urb_listitem->urb);
1227         kmem_cache_free(urb_listitem_cachep, urb_listitem);
1228     }
1229 
1230     /*
1231      * Schedule packets for transfer.
1232      *
1233      * According to USB2.0 specification:
1234      *
1235      * 1st prio: interrupt xfers, up to 80 % of bandwidth
1236      * 2nd prio: control xfers
1237      * 3rd prio: bulk xfers
1238      *
1239      * ... but let's use a simpler scheme here (mostly because ISP1761 doc
1240      * is very unclear on how to prioritize traffic):
1241      *
1242      * 1) Enqueue any queued control transfers, as long as payload chip mem
1243      *    and PTD ATL slots are available.
1244      * 2) Enqueue any queued INT transfers, as long as payload chip mem
1245      *    and PTD INT slots are available.
1246      * 3) Enqueue any queued bulk transfers, as long as payload chip mem
1247      *    and PTD ATL slots are available.
1248      *
1249      * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
1250      * conservation of chip mem and performance.
1251      *
1252      * I'm sure this scheme could be improved upon!
1253      */
1254     for (i = 0; i < QH_END; i++) {
1255         ep_queue = &priv->qh_list[i];
1256         list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
1257             enqueue_qtds(hcd, qh);
1258     }
1259 }
1260 
1261 #define PTD_STATE_QTD_DONE  1
1262 #define PTD_STATE_QTD_RELOAD    2
1263 #define PTD_STATE_URB_RETIRE    3
1264 
1265 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1266                                 struct urb *urb)
1267 {
1268     u32 dw4;
1269     int i;
1270 
1271     dw4 = TO_U32(ptd->dw4);
1272     dw4 >>= 8;
1273 
1274     /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1275        need to handle these errors? Is it done in hardware? */
1276 
1277     if (ptd->dw3 & DW3_HALT_BIT) {
1278 
1279         urb->status = -EPROTO; /* Default unknown error */
1280 
1281         for (i = 0; i < 8; i++) {
1282             switch (dw4 & 0x7) {
1283             case INT_UNDERRUN:
1284                 dev_dbg(hcd->self.controller, "%s: underrun "
1285                         "during uFrame %d\n",
1286                         __func__, i);
1287                 urb->status = -ECOMM; /* Could not write data */
1288                 break;
1289             case INT_EXACT:
1290                 dev_dbg(hcd->self.controller, "%s: transaction "
1291                         "error during uFrame %d\n",
1292                         __func__, i);
1293                 urb->status = -EPROTO; /* timeout, bad CRC, PID
1294                               error etc. */
1295                 break;
1296             case INT_BABBLE:
1297                 dev_dbg(hcd->self.controller, "%s: babble "
1298                         "error during uFrame %d\n",
1299                         __func__, i);
1300                 urb->status = -EOVERFLOW;
1301                 break;
1302             }
1303             dw4 >>= 3;
1304         }
1305 
1306         return PTD_STATE_URB_RETIRE;
1307     }
1308 
1309     return PTD_STATE_QTD_DONE;
1310 }
1311 
1312 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1313                                 struct urb *urb)
1314 {
1315     WARN_ON(!ptd);
1316     if (ptd->dw3 & DW3_HALT_BIT) {
1317         if (ptd->dw3 & DW3_BABBLE_BIT)
1318             urb->status = -EOVERFLOW;
1319         else if (FROM_DW3_CERR(ptd->dw3))
1320             urb->status = -EPIPE;  /* Stall */
1321         else
1322             urb->status = -EPROTO; /* Unknown */
1323 /*
1324         dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1325             "        dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1326             "        dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1327             __func__,
1328             ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1329             ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1330 */
1331         return PTD_STATE_URB_RETIRE;
1332     }
1333 
1334     if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1335         /* Transfer Error, *but* active and no HALT -> reload */
1336         dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1337         return PTD_STATE_QTD_RELOAD;
1338     }
1339 
1340     if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1341         /*
1342          * NAKs are handled in HW by the chip. Usually if the
1343          * device is not able to send data fast enough.
1344          * This happens mostly on slower hardware.
1345          */
1346         return PTD_STATE_QTD_RELOAD;
1347     }
1348 
1349     return PTD_STATE_QTD_DONE;
1350 }
1351 
1352 static void handle_done_ptds(struct usb_hcd *hcd)
1353 {
1354     struct isp1760_hcd *priv = hcd_to_priv(hcd);
1355     struct ptd ptd;
1356     struct isp1760_qh *qh;
1357     int slot;
1358     int state;
1359     struct isp1760_slotinfo *slots;
1360     u32 ptd_offset;
1361     struct isp1760_qtd *qtd;
1362     int modified;
1363     int skip_map;
1364 
1365     skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP);
1366     priv->int_done_map &= ~skip_map;
1367     skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP);
1368     priv->atl_done_map &= ~skip_map;
1369 
1370     modified = priv->int_done_map || priv->atl_done_map;
1371 
1372     while (priv->int_done_map || priv->atl_done_map) {
1373         if (priv->int_done_map) {
1374             /* INT ptd */
1375             slot = __ffs(priv->int_done_map);
1376             priv->int_done_map &= ~(1 << slot);
1377             slots = priv->int_slots;
1378             /* This should not trigger, and could be removed if
1379                noone have any problems with it triggering: */
1380             if (!slots[slot].qh) {
1381                 WARN_ON(1);
1382                 continue;
1383             }
1384             ptd_offset = INT_PTD_OFFSET;
1385             ptd_read(hcd, INT_PTD_OFFSET, slot, &ptd);
1386             state = check_int_transfer(hcd, &ptd,
1387                             slots[slot].qtd->urb);
1388         } else {
1389             /* ATL ptd */
1390             slot = __ffs(priv->atl_done_map);
1391             priv->atl_done_map &= ~(1 << slot);
1392             slots = priv->atl_slots;
1393             /* This should not trigger, and could be removed if
1394                noone have any problems with it triggering: */
1395             if (!slots[slot].qh) {
1396                 WARN_ON(1);
1397                 continue;
1398             }
1399             ptd_offset = ATL_PTD_OFFSET;
1400             ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd);
1401             state = check_atl_transfer(hcd, &ptd,
1402                             slots[slot].qtd->urb);
1403         }
1404 
1405         qtd = slots[slot].qtd;
1406         slots[slot].qtd = NULL;
1407         qh = slots[slot].qh;
1408         slots[slot].qh = NULL;
1409         qh->slot = -1;
1410 
1411         WARN_ON(qtd->status != QTD_XFER_STARTED);
1412 
1413         switch (state) {
1414         case PTD_STATE_QTD_DONE:
1415             if ((usb_pipeint(qtd->urb->pipe)) &&
1416                        (qtd->urb->dev->speed != USB_SPEED_HIGH))
1417                 qtd->actual_length =
1418                        FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1419             else
1420                 qtd->actual_length =
1421                     FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1422 
1423             qtd->status = QTD_XFER_COMPLETE;
1424             if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1425                 is_short_bulk(qtd))
1426                 qtd = NULL;
1427             else
1428                 qtd = list_entry(qtd->qtd_list.next,
1429                             typeof(*qtd), qtd_list);
1430 
1431             qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1432             qh->ping = FROM_DW3_PING(ptd.dw3);
1433             break;
1434 
1435         case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1436             qtd->status = QTD_PAYLOAD_ALLOC;
1437             ptd.dw0 |= DW0_VALID_BIT;
1438             /* RL counter = ERR counter */
1439             ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1440             ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1441             ptd.dw3 &= ~TO_DW3_CERR(3);
1442             ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1443             qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1444             qh->ping = FROM_DW3_PING(ptd.dw3);
1445             break;
1446 
1447         case PTD_STATE_URB_RETIRE:
1448             qtd->status = QTD_RETIRE;
1449             if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1450                     (qtd->urb->status != -EPIPE) &&
1451                     (qtd->urb->status != -EREMOTEIO)) {
1452                 qh->tt_buffer_dirty = 1;
1453                 if (usb_hub_clear_tt_buffer(qtd->urb))
1454                     /* Clear failed; let's hope things work
1455                        anyway */
1456                     qh->tt_buffer_dirty = 0;
1457             }
1458             qtd = NULL;
1459             qh->toggle = 0;
1460             qh->ping = 0;
1461             break;
1462 
1463         default:
1464             WARN_ON(1);
1465             continue;
1466         }
1467 
1468         if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1469             if (slots == priv->int_slots) {
1470                 if (state == PTD_STATE_QTD_RELOAD)
1471                     dev_err(hcd->self.controller,
1472                         "%s: PTD_STATE_QTD_RELOAD on "
1473                         "interrupt packet\n", __func__);
1474                 if (state != PTD_STATE_QTD_RELOAD)
1475                     create_ptd_int(qh, qtd, &ptd);
1476             } else {
1477                 if (state != PTD_STATE_QTD_RELOAD)
1478                     create_ptd_atl(qh, qtd, &ptd);
1479             }
1480 
1481             start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1482                 qh, &ptd);
1483         }
1484     }
1485 
1486     if (modified)
1487         schedule_ptds(hcd);
1488 }
1489 
1490 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1491 {
1492     struct isp1760_hcd *priv = hcd_to_priv(hcd);
1493     irqreturn_t irqret = IRQ_NONE;
1494     u32 int_reg;
1495     u32 imask;
1496 
1497     spin_lock(&priv->lock);
1498 
1499     if (!(hcd->state & HC_STATE_RUNNING))
1500         goto leave;
1501 
1502     imask = isp1760_hcd_read(hcd, HC_INTERRUPT);
1503     if (unlikely(!imask))
1504         goto leave;
1505 
1506     int_reg = priv->is_isp1763 ? ISP1763_HC_INTERRUPT :
1507         ISP176x_HC_INTERRUPT;
1508     isp1760_reg_write(priv->regs, int_reg, imask);
1509 
1510     priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP);
1511     priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP);
1512 
1513     handle_done_ptds(hcd);
1514 
1515     irqret = IRQ_HANDLED;
1516 
1517 leave:
1518     spin_unlock(&priv->lock);
1519 
1520     return irqret;
1521 }
1522 
1523 /*
1524  * Workaround for problem described in chip errata 2:
1525  *
1526  * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1527  * One solution suggested in the errata is to use SOF interrupts _instead_of_
1528  * ATL done interrupts (the "instead of" might be important since it seems
1529  * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1530  * to set the PTD's done bit in addition to not generating an interrupt!).
1531  *
1532  * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1533  * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1534  *
1535  * If we use SOF interrupts only, we get latency between ptd completion and the
1536  * actual handling. This is very noticeable in testusb runs which takes several
1537  * minutes longer without ATL interrupts.
1538  *
1539  * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1540  * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1541  * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1542  * completed and its done map bit is set.
1543  *
1544  * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1545  * not to cause too much lag when this HW bug occurs, while still hopefully
1546  * ensuring that the check does not falsely trigger.
1547  */
1548 #define SLOT_TIMEOUT 300
1549 #define SLOT_CHECK_PERIOD 200
1550 static struct timer_list errata2_timer;
1551 static struct usb_hcd *errata2_timer_hcd;
1552 
1553 static void errata2_function(struct timer_list *unused)
1554 {
1555     struct usb_hcd *hcd = errata2_timer_hcd;
1556     struct isp1760_hcd *priv = hcd_to_priv(hcd);
1557     const struct isp1760_memory_layout *mem = priv->memory_layout;
1558     int slot;
1559     struct ptd ptd;
1560     unsigned long spinflags;
1561 
1562     spin_lock_irqsave(&priv->lock, spinflags);
1563 
1564     for (slot = 0; slot < mem->slot_num; slot++)
1565         if (priv->atl_slots[slot].qh && time_after(jiffies,
1566                     priv->atl_slots[slot].timestamp +
1567                     msecs_to_jiffies(SLOT_TIMEOUT))) {
1568             ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd);
1569             if (!FROM_DW0_VALID(ptd.dw0) &&
1570                     !FROM_DW3_ACTIVE(ptd.dw3))
1571                 priv->atl_done_map |= 1 << slot;
1572         }
1573 
1574     if (priv->atl_done_map)
1575         handle_done_ptds(hcd);
1576 
1577     spin_unlock_irqrestore(&priv->lock, spinflags);
1578 
1579     errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD);
1580     add_timer(&errata2_timer);
1581 }
1582 
1583 static int isp1763_run(struct usb_hcd *hcd)
1584 {
1585     struct isp1760_hcd *priv = hcd_to_priv(hcd);
1586     int retval;
1587     u32 chipid_h;
1588     u32 chipid_l;
1589     u32 chip_rev;
1590     u32 ptd_atl_int;
1591     u32 ptd_iso;
1592 
1593     hcd->uses_new_polling = 1;
1594     hcd->state = HC_STATE_RUNNING;
1595 
1596     chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH);
1597     chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW);
1598     chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV);
1599     dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n",
1600          chipid_h, chipid_l, chip_rev);
1601 
1602     isp1760_hcd_clear(hcd, ISO_BUF_FILL);
1603     isp1760_hcd_clear(hcd, INT_BUF_FILL);
1604     isp1760_hcd_clear(hcd, ATL_BUF_FILL);
1605 
1606     isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP);
1607     isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP);
1608     isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP);
1609     ndelay(100);
1610     isp1760_hcd_clear(hcd, HC_ATL_PTD_DONEMAP);
1611     isp1760_hcd_clear(hcd, HC_INT_PTD_DONEMAP);
1612     isp1760_hcd_clear(hcd, HC_ISO_PTD_DONEMAP);
1613 
1614     isp1760_hcd_set(hcd, HW_OTG_DISABLE);
1615     isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(7));
1616     isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(15));
1617     mdelay(10);
1618 
1619     isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE);
1620     isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE);
1621 
1622     isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN);
1623 
1624     isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND);
1625     isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND);
1626     isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND);
1627 
1628     isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR);
1629     isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR);
1630     isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR);
1631 
1632     ptd_atl_int = 0x8000;
1633     ptd_iso = 0x0001;
1634 
1635     isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int);
1636     isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int);
1637     isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso);
1638 
1639     isp1760_hcd_set(hcd, ATL_BUF_FILL);
1640     isp1760_hcd_set(hcd, INT_BUF_FILL);
1641 
1642     isp1760_hcd_clear(hcd, CMD_LRESET);
1643     isp1760_hcd_clear(hcd, CMD_RESET);
1644 
1645     retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000);
1646     if (retval)
1647         return retval;
1648 
1649     down_write(&ehci_cf_port_reset_rwsem);
1650     retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000);
1651     up_write(&ehci_cf_port_reset_rwsem);
1652     if (retval)
1653         return retval;
1654 
1655     return 0;
1656 }
1657 
1658 static int isp1760_run(struct usb_hcd *hcd)
1659 {
1660     struct isp1760_hcd *priv = hcd_to_priv(hcd);
1661     int retval;
1662     u32 chipid_h;
1663     u32 chipid_l;
1664     u32 chip_rev;
1665     u32 ptd_atl_int;
1666     u32 ptd_iso;
1667 
1668     /*
1669      * ISP1763 have some differences in the setup and order to enable
1670      * the ports, disable otg, setup buffers, and ATL, INT, ISO status.
1671      * So, just handle it a separate sequence.
1672      */
1673     if (priv->is_isp1763)
1674         return isp1763_run(hcd);
1675 
1676     hcd->uses_new_polling = 1;
1677 
1678     hcd->state = HC_STATE_RUNNING;
1679 
1680     /* Set PTD interrupt AND & OR maps */
1681     isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND);
1682     isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND);
1683     isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND);
1684 
1685     isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR);
1686     isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR);
1687     isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR);
1688 
1689     /* step 23 passed */
1690 
1691     isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN);
1692 
1693     isp1760_hcd_clear(hcd, CMD_LRESET);
1694     isp1760_hcd_clear(hcd, CMD_RESET);
1695 
1696     retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000);
1697     if (retval)
1698         return retval;
1699 
1700     /*
1701      * XXX
1702      * Spec says to write FLAG_CF as last config action, priv code grabs
1703      * the semaphore while doing so.
1704      */
1705     down_write(&ehci_cf_port_reset_rwsem);
1706 
1707     retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000);
1708     up_write(&ehci_cf_port_reset_rwsem);
1709     if (retval)
1710         return retval;
1711 
1712     errata2_timer_hcd = hcd;
1713     timer_setup(&errata2_timer, errata2_function, 0);
1714     errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD);
1715     add_timer(&errata2_timer);
1716 
1717     chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH);
1718     chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW);
1719     chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV);
1720     dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n",
1721          chipid_h, chipid_l, chip_rev);
1722 
1723     /* PTD Register Init Part 2, Step 28 */
1724 
1725     /* Setup registers controlling PTD checking */
1726     ptd_atl_int = 0x80000000;
1727     ptd_iso = 0x00000001;
1728 
1729     isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int);
1730     isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int);
1731     isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso);
1732 
1733     isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP);
1734     isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP);
1735     isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP);
1736 
1737     isp1760_hcd_set(hcd, ATL_BUF_FILL);
1738     isp1760_hcd_set(hcd, INT_BUF_FILL);
1739 
1740     /* GRR this is run-once init(), being done every time the HC starts.
1741      * So long as they're part of class devices, we can't do it init()
1742      * since the class device isn't created that early.
1743      */
1744     return 0;
1745 }
1746 
1747 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1748 {
1749     qtd->data_buffer = databuffer;
1750 
1751     qtd->length = len;
1752 
1753     return qtd->length;
1754 }
1755 
1756 static void qtd_list_free(struct list_head *qtd_list)
1757 {
1758     struct isp1760_qtd *qtd, *qtd_next;
1759 
1760     list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1761         list_del(&qtd->qtd_list);
1762         qtd_free(qtd);
1763     }
1764 }
1765 
1766 /*
1767  * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1768  * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1769  */
1770 static void packetize_urb(struct usb_hcd *hcd,
1771         struct urb *urb, struct list_head *head, gfp_t flags)
1772 {
1773     struct isp1760_hcd *priv = hcd_to_priv(hcd);
1774     const struct isp1760_memory_layout *mem = priv->memory_layout;
1775     struct isp1760_qtd *qtd;
1776     void *buf;
1777     int len, maxpacketsize;
1778     u8 packet_type;
1779 
1780     /*
1781      * URBs map to sequences of QTDs:  one logical transaction
1782      */
1783 
1784     if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1785         /* XXX This looks like usb storage / SCSI bug */
1786         dev_err(hcd->self.controller,
1787                 "buf is null, dma is %08lx len is %d\n",
1788                 (long unsigned)urb->transfer_dma,
1789                 urb->transfer_buffer_length);
1790         WARN_ON(1);
1791     }
1792 
1793     if (usb_pipein(urb->pipe))
1794         packet_type = IN_PID;
1795     else
1796         packet_type = OUT_PID;
1797 
1798     if (usb_pipecontrol(urb->pipe)) {
1799         qtd = qtd_alloc(flags, urb, SETUP_PID);
1800         if (!qtd)
1801             goto cleanup;
1802         qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1803         list_add_tail(&qtd->qtd_list, head);
1804 
1805         /* for zero length DATA stages, STATUS is always IN */
1806         if (urb->transfer_buffer_length == 0)
1807             packet_type = IN_PID;
1808     }
1809 
1810     maxpacketsize = usb_maxpacket(urb->dev, urb->pipe);
1811 
1812     /*
1813      * buffer gets wrapped in one or more qtds;
1814      * last one may be "short" (including zero len)
1815      * and may serve as a control status ack
1816      */
1817     buf = urb->transfer_buffer;
1818     len = urb->transfer_buffer_length;
1819 
1820     for (;;) {
1821         int this_qtd_len;
1822 
1823         qtd = qtd_alloc(flags, urb, packet_type);
1824         if (!qtd)
1825             goto cleanup;
1826 
1827         if (len > mem->blocks_size[ISP176x_BLOCK_NUM - 1])
1828             this_qtd_len = mem->blocks_size[ISP176x_BLOCK_NUM - 1];
1829         else
1830             this_qtd_len = len;
1831 
1832         this_qtd_len = qtd_fill(qtd, buf, this_qtd_len);
1833         list_add_tail(&qtd->qtd_list, head);
1834 
1835         len -= this_qtd_len;
1836         buf += this_qtd_len;
1837 
1838         if (len <= 0)
1839             break;
1840     }
1841 
1842     /*
1843      * control requests may need a terminating data "status" ack;
1844      * bulk ones may need a terminating short packet (zero length).
1845      */
1846     if (urb->transfer_buffer_length != 0) {
1847         int one_more = 0;
1848 
1849         if (usb_pipecontrol(urb->pipe)) {
1850             one_more = 1;
1851             if (packet_type == IN_PID)
1852                 packet_type = OUT_PID;
1853             else
1854                 packet_type = IN_PID;
1855         } else if (usb_pipebulk(urb->pipe) && maxpacketsize
1856                 && (urb->transfer_flags & URB_ZERO_PACKET)
1857                 && !(urb->transfer_buffer_length %
1858                             maxpacketsize)) {
1859             one_more = 1;
1860         }
1861         if (one_more) {
1862             qtd = qtd_alloc(flags, urb, packet_type);
1863             if (!qtd)
1864                 goto cleanup;
1865 
1866             /* never any data in such packets */
1867             qtd_fill(qtd, NULL, 0);
1868             list_add_tail(&qtd->qtd_list, head);
1869         }
1870     }
1871 
1872     return;
1873 
1874 cleanup:
1875     qtd_list_free(head);
1876 }
1877 
1878 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1879         gfp_t mem_flags)
1880 {
1881     struct isp1760_hcd *priv = hcd_to_priv(hcd);
1882     struct list_head *ep_queue;
1883     struct isp1760_qh *qh, *qhit;
1884     unsigned long spinflags;
1885     LIST_HEAD(new_qtds);
1886     int retval;
1887     int qh_in_queue;
1888 
1889     switch (usb_pipetype(urb->pipe)) {
1890     case PIPE_CONTROL:
1891         ep_queue = &priv->qh_list[QH_CONTROL];
1892         break;
1893     case PIPE_BULK:
1894         ep_queue = &priv->qh_list[QH_BULK];
1895         break;
1896     case PIPE_INTERRUPT:
1897         if (urb->interval < 0)
1898             return -EINVAL;
1899         /* FIXME: Check bandwidth  */
1900         ep_queue = &priv->qh_list[QH_INTERRUPT];
1901         break;
1902     case PIPE_ISOCHRONOUS:
1903         dev_err(hcd->self.controller, "%s: isochronous USB packets "
1904                             "not yet supported\n",
1905                             __func__);
1906         return -EPIPE;
1907     default:
1908         dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1909                             __func__);
1910         return -EPIPE;
1911     }
1912 
1913     if (usb_pipein(urb->pipe))
1914         urb->actual_length = 0;
1915 
1916     packetize_urb(hcd, urb, &new_qtds, mem_flags);
1917     if (list_empty(&new_qtds))
1918         return -ENOMEM;
1919 
1920     spin_lock_irqsave(&priv->lock, spinflags);
1921 
1922     if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1923         retval = -ESHUTDOWN;
1924         qtd_list_free(&new_qtds);
1925         goto out;
1926     }
1927     retval = usb_hcd_link_urb_to_ep(hcd, urb);
1928     if (retval) {
1929         qtd_list_free(&new_qtds);
1930         goto out;
1931     }
1932 
1933     qh = urb->ep->hcpriv;
1934     if (qh) {
1935         qh_in_queue = 0;
1936         list_for_each_entry(qhit, ep_queue, qh_list) {
1937             if (qhit == qh) {
1938                 qh_in_queue = 1;
1939                 break;
1940             }
1941         }
1942         if (!qh_in_queue)
1943             list_add_tail(&qh->qh_list, ep_queue);
1944     } else {
1945         qh = qh_alloc(GFP_ATOMIC);
1946         if (!qh) {
1947             retval = -ENOMEM;
1948             usb_hcd_unlink_urb_from_ep(hcd, urb);
1949             qtd_list_free(&new_qtds);
1950             goto out;
1951         }
1952         list_add_tail(&qh->qh_list, ep_queue);
1953         urb->ep->hcpriv = qh;
1954     }
1955 
1956     list_splice_tail(&new_qtds, &qh->qtd_list);
1957     schedule_ptds(hcd);
1958 
1959 out:
1960     spin_unlock_irqrestore(&priv->lock, spinflags);
1961     return retval;
1962 }
1963 
1964 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1965         struct isp1760_qh *qh)
1966 {
1967     struct isp1760_hcd *priv = hcd_to_priv(hcd);
1968     int skip_map;
1969 
1970     WARN_ON(qh->slot == -1);
1971 
1972     /* We need to forcefully reclaim the slot since some transfers never
1973        return, e.g. interrupt transfers and NAKed bulk transfers. */
1974     if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1975         if (qh->slot != -1) {
1976             skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP);
1977             skip_map |= (1 << qh->slot);
1978             isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map);
1979             ndelay(100);
1980         }
1981         priv->atl_slots[qh->slot].qh = NULL;
1982         priv->atl_slots[qh->slot].qtd = NULL;
1983     } else {
1984         if (qh->slot != -1) {
1985             skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP);
1986             skip_map |= (1 << qh->slot);
1987             isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map);
1988         }
1989         priv->int_slots[qh->slot].qh = NULL;
1990         priv->int_slots[qh->slot].qtd = NULL;
1991     }
1992 
1993     qh->slot = -1;
1994 }
1995 
1996 /*
1997  * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1998  * any active transfer belonging to the urb in the process.
1999  */
2000 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
2001                         struct isp1760_qtd *qtd)
2002 {
2003     struct urb *urb;
2004     int urb_was_running;
2005 
2006     urb = qtd->urb;
2007     urb_was_running = 0;
2008     list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
2009         if (qtd->urb != urb)
2010             break;
2011 
2012         if (qtd->status >= QTD_XFER_STARTED)
2013             urb_was_running = 1;
2014         if (last_qtd_of_urb(qtd, qh) &&
2015                     (qtd->status >= QTD_XFER_COMPLETE))
2016             urb_was_running = 0;
2017 
2018         if (qtd->status == QTD_XFER_STARTED)
2019             kill_transfer(hcd, urb, qh);
2020         qtd->status = QTD_RETIRE;
2021     }
2022 
2023     if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
2024         qh->tt_buffer_dirty = 1;
2025         if (usb_hub_clear_tt_buffer(urb))
2026             /* Clear failed; let's hope things work anyway */
2027             qh->tt_buffer_dirty = 0;
2028     }
2029 }
2030 
2031 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2032         int status)
2033 {
2034     struct isp1760_hcd *priv = hcd_to_priv(hcd);
2035     unsigned long spinflags;
2036     struct isp1760_qh *qh;
2037     struct isp1760_qtd *qtd;
2038     int retval = 0;
2039 
2040     spin_lock_irqsave(&priv->lock, spinflags);
2041     retval = usb_hcd_check_unlink_urb(hcd, urb, status);
2042     if (retval)
2043         goto out;
2044 
2045     qh = urb->ep->hcpriv;
2046     if (!qh) {
2047         retval = -EINVAL;
2048         goto out;
2049     }
2050 
2051     list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
2052         if (qtd->urb == urb) {
2053             dequeue_urb_from_qtd(hcd, qh, qtd);
2054             list_move(&qtd->qtd_list, &qh->qtd_list);
2055             break;
2056         }
2057 
2058     urb->status = status;
2059     schedule_ptds(hcd);
2060 
2061 out:
2062     spin_unlock_irqrestore(&priv->lock, spinflags);
2063     return retval;
2064 }
2065 
2066 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
2067         struct usb_host_endpoint *ep)
2068 {
2069     struct isp1760_hcd *priv = hcd_to_priv(hcd);
2070     unsigned long spinflags;
2071     struct isp1760_qh *qh, *qh_iter;
2072     int i;
2073 
2074     spin_lock_irqsave(&priv->lock, spinflags);
2075 
2076     qh = ep->hcpriv;
2077     if (!qh)
2078         goto out;
2079 
2080     WARN_ON(!list_empty(&qh->qtd_list));
2081 
2082     for (i = 0; i < QH_END; i++)
2083         list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
2084             if (qh_iter == qh) {
2085                 list_del(&qh_iter->qh_list);
2086                 i = QH_END;
2087                 break;
2088             }
2089     qh_free(qh);
2090     ep->hcpriv = NULL;
2091 
2092     schedule_ptds(hcd);
2093 
2094 out:
2095     spin_unlock_irqrestore(&priv->lock, spinflags);
2096 }
2097 
2098 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
2099 {
2100     struct isp1760_hcd *priv = hcd_to_priv(hcd);
2101     u32 status = 0;
2102     int retval = 1;
2103     unsigned long flags;
2104 
2105     /* if !PM, root hub timers won't get shut down ... */
2106     if (!HC_IS_RUNNING(hcd->state))
2107         return 0;
2108 
2109     /* init status to no-changes */
2110     buf[0] = 0;
2111 
2112     spin_lock_irqsave(&priv->lock, flags);
2113 
2114     if (isp1760_hcd_is_set(hcd, PORT_OWNER) &&
2115         isp1760_hcd_is_set(hcd, PORT_CSC)) {
2116         isp1760_hcd_clear(hcd, PORT_CSC);
2117         goto done;
2118     }
2119 
2120     /*
2121      * Return status information even for ports with OWNER set.
2122      * Otherwise hub_wq wouldn't see the disconnect event when a
2123      * high-speed device is switched over to the companion
2124      * controller by the user.
2125      */
2126     if (isp1760_hcd_is_set(hcd, PORT_CSC) ||
2127         (isp1760_hcd_is_set(hcd, PORT_RESUME) &&
2128          time_after_eq(jiffies, priv->reset_done))) {
2129         buf [0] |= 1 << (0 + 1);
2130         status = STS_PCD;
2131     }
2132     /* FIXME autosuspend idle root hubs */
2133 done:
2134     spin_unlock_irqrestore(&priv->lock, flags);
2135     return status ? retval : 0;
2136 }
2137 
2138 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
2139         struct usb_hub_descriptor *desc)
2140 {
2141     int ports;
2142     u16 temp;
2143 
2144     ports = isp1760_hcd_n_ports(priv->hcd);
2145 
2146     desc->bDescriptorType = USB_DT_HUB;
2147     /* priv 1.0, 2.3.9 says 20ms max */
2148     desc->bPwrOn2PwrGood = 10;
2149     desc->bHubContrCurrent = 0;
2150 
2151     desc->bNbrPorts = ports;
2152     temp = 1 + (ports / 8);
2153     desc->bDescLength = 7 + 2 * temp;
2154 
2155     /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
2156     memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
2157     memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
2158 
2159     /* per-port overcurrent reporting */
2160     temp = HUB_CHAR_INDV_PORT_OCPM;
2161     if (isp1760_hcd_ppc_is_set(priv->hcd))
2162         /* per-port power control */
2163         temp |= HUB_CHAR_INDV_PORT_LPSM;
2164     else
2165         /* no power switching */
2166         temp |= HUB_CHAR_NO_LPSM;
2167     desc->wHubCharacteristics = cpu_to_le16(temp);
2168 }
2169 
2170 #define PORT_WAKE_BITS  (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
2171 
2172 static void check_reset_complete(struct usb_hcd *hcd, int index)
2173 {
2174     if (!(isp1760_hcd_is_set(hcd, PORT_CONNECT)))
2175         return;
2176 
2177     /* if reset finished and it's still not enabled -- handoff */
2178     if (!isp1760_hcd_is_set(hcd, PORT_PE)) {
2179         dev_info(hcd->self.controller,
2180              "port %d full speed --> companion\n", index + 1);
2181 
2182         isp1760_hcd_set(hcd, PORT_OWNER);
2183 
2184         isp1760_hcd_clear(hcd, PORT_CSC);
2185     } else {
2186         dev_info(hcd->self.controller, "port %d high speed\n",
2187              index + 1);
2188     }
2189 
2190     return;
2191 }
2192 
2193 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
2194         u16 wValue, u16 wIndex, char *buf, u16 wLength)
2195 {
2196     struct isp1760_hcd *priv = hcd_to_priv(hcd);
2197     u32 status;
2198     unsigned long flags;
2199     int retval = 0;
2200     int ports;
2201 
2202     ports = isp1760_hcd_n_ports(hcd);
2203 
2204     /*
2205      * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
2206      * HCS_INDICATOR may say we can change LEDs to off/amber/green.
2207      * (track current state ourselves) ... blink for diagnostics,
2208      * power, "this is the one", etc.  EHCI spec supports this.
2209      */
2210 
2211     spin_lock_irqsave(&priv->lock, flags);
2212     switch (typeReq) {
2213     case ClearHubFeature:
2214         switch (wValue) {
2215         case C_HUB_LOCAL_POWER:
2216         case C_HUB_OVER_CURRENT:
2217             /* no hub-wide feature/status flags */
2218             break;
2219         default:
2220             goto error;
2221         }
2222         break;
2223     case ClearPortFeature:
2224         if (!wIndex || wIndex > ports)
2225             goto error;
2226         wIndex--;
2227 
2228         /*
2229          * Even if OWNER is set, so the port is owned by the
2230          * companion controller, hub_wq needs to be able to clear
2231          * the port-change status bits (especially
2232          * USB_PORT_STAT_C_CONNECTION).
2233          */
2234 
2235         switch (wValue) {
2236         case USB_PORT_FEAT_ENABLE:
2237             isp1760_hcd_clear(hcd, PORT_PE);
2238             break;
2239         case USB_PORT_FEAT_C_ENABLE:
2240             /* XXX error? */
2241             break;
2242         case USB_PORT_FEAT_SUSPEND:
2243             if (isp1760_hcd_is_set(hcd, PORT_RESET))
2244                 goto error;
2245 
2246             if (isp1760_hcd_is_set(hcd, PORT_SUSPEND)) {
2247                 if (!isp1760_hcd_is_set(hcd, PORT_PE))
2248                     goto error;
2249                 /* resume signaling for 20 msec */
2250                 isp1760_hcd_clear(hcd, PORT_CSC);
2251                 isp1760_hcd_set(hcd, PORT_RESUME);
2252 
2253                 priv->reset_done = jiffies +
2254                     msecs_to_jiffies(USB_RESUME_TIMEOUT);
2255             }
2256             break;
2257         case USB_PORT_FEAT_C_SUSPEND:
2258             /* we auto-clear this feature */
2259             break;
2260         case USB_PORT_FEAT_POWER:
2261             if (isp1760_hcd_ppc_is_set(hcd))
2262                 isp1760_hcd_clear(hcd, PORT_POWER);
2263             break;
2264         case USB_PORT_FEAT_C_CONNECTION:
2265             isp1760_hcd_set(hcd, PORT_CSC);
2266             break;
2267         case USB_PORT_FEAT_C_OVER_CURRENT:
2268             /* XXX error ?*/
2269             break;
2270         case USB_PORT_FEAT_C_RESET:
2271             /* GetPortStatus clears reset */
2272             break;
2273         default:
2274             goto error;
2275         }
2276         isp1760_hcd_read(hcd, CMD_RUN);
2277         break;
2278     case GetHubDescriptor:
2279         isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
2280             buf);
2281         break;
2282     case GetHubStatus:
2283         /* no hub-wide feature/status flags */
2284         memset(buf, 0, 4);
2285         break;
2286     case GetPortStatus:
2287         if (!wIndex || wIndex > ports)
2288             goto error;
2289         wIndex--;
2290         status = 0;
2291 
2292         /* wPortChange bits */
2293         if (isp1760_hcd_is_set(hcd, PORT_CSC))
2294             status |= USB_PORT_STAT_C_CONNECTION << 16;
2295 
2296         /* whoever resumes must GetPortStatus to complete it!! */
2297         if (isp1760_hcd_is_set(hcd, PORT_RESUME)) {
2298             dev_err(hcd->self.controller, "Port resume should be skipped.\n");
2299 
2300             /* Remote Wakeup received? */
2301             if (!priv->reset_done) {
2302                 /* resume signaling for 20 msec */
2303                 priv->reset_done = jiffies
2304                         + msecs_to_jiffies(20);
2305                 /* check the port again */
2306                 mod_timer(&hcd->rh_timer, priv->reset_done);
2307             }
2308 
2309             /* resume completed? */
2310             else if (time_after_eq(jiffies,
2311                     priv->reset_done)) {
2312                 status |= USB_PORT_STAT_C_SUSPEND << 16;
2313                 priv->reset_done = 0;
2314 
2315                 /* stop resume signaling */
2316                 isp1760_hcd_clear(hcd, PORT_CSC);
2317 
2318                 retval = isp1760_hcd_clear_and_wait(hcd,
2319                               PORT_RESUME, 2000);
2320                 if (retval != 0) {
2321                     dev_err(hcd->self.controller,
2322                         "port %d resume error %d\n",
2323                         wIndex + 1, retval);
2324                     goto error;
2325                 }
2326             }
2327         }
2328 
2329         /* whoever resets must GetPortStatus to complete it!! */
2330         if (isp1760_hcd_is_set(hcd, PORT_RESET) &&
2331             time_after_eq(jiffies, priv->reset_done)) {
2332             status |= USB_PORT_STAT_C_RESET << 16;
2333             priv->reset_done = 0;
2334 
2335             /* force reset to complete */
2336             /* REVISIT:  some hardware needs 550+ usec to clear
2337              * this bit; seems too long to spin routinely...
2338              */
2339             retval = isp1760_hcd_clear_and_wait(hcd, PORT_RESET,
2340                                 750);
2341             if (retval != 0) {
2342                 dev_err(hcd->self.controller, "port %d reset error %d\n",
2343                     wIndex + 1, retval);
2344                 goto error;
2345             }
2346 
2347             /* see what we found out */
2348             check_reset_complete(hcd, wIndex);
2349         }
2350         /*
2351          * Even if OWNER is set, there's no harm letting hub_wq
2352          * see the wPortStatus values (they should all be 0 except
2353          * for PORT_POWER anyway).
2354          */
2355 
2356         if (isp1760_hcd_is_set(hcd, PORT_OWNER))
2357             dev_err(hcd->self.controller, "PORT_OWNER is set\n");
2358 
2359         if (isp1760_hcd_is_set(hcd, PORT_CONNECT)) {
2360             status |= USB_PORT_STAT_CONNECTION;
2361             /* status may be from integrated TT */
2362             status |= USB_PORT_STAT_HIGH_SPEED;
2363         }
2364         if (isp1760_hcd_is_set(hcd, PORT_PE))
2365             status |= USB_PORT_STAT_ENABLE;
2366         if (isp1760_hcd_is_set(hcd, PORT_SUSPEND) &&
2367             isp1760_hcd_is_set(hcd, PORT_RESUME))
2368             status |= USB_PORT_STAT_SUSPEND;
2369         if (isp1760_hcd_is_set(hcd, PORT_RESET))
2370             status |= USB_PORT_STAT_RESET;
2371         if (isp1760_hcd_is_set(hcd, PORT_POWER))
2372             status |= USB_PORT_STAT_POWER;
2373 
2374         put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2375         break;
2376     case SetHubFeature:
2377         switch (wValue) {
2378         case C_HUB_LOCAL_POWER:
2379         case C_HUB_OVER_CURRENT:
2380             /* no hub-wide feature/status flags */
2381             break;
2382         default:
2383             goto error;
2384         }
2385         break;
2386     case SetPortFeature:
2387         wIndex &= 0xff;
2388         if (!wIndex || wIndex > ports)
2389             goto error;
2390         wIndex--;
2391 
2392         if (isp1760_hcd_is_set(hcd, PORT_OWNER))
2393             break;
2394 
2395         switch (wValue) {
2396         case USB_PORT_FEAT_ENABLE:
2397             isp1760_hcd_set(hcd, PORT_PE);
2398             break;
2399 
2400         case USB_PORT_FEAT_SUSPEND:
2401             if (!isp1760_hcd_is_set(hcd, PORT_PE) ||
2402                 isp1760_hcd_is_set(hcd, PORT_RESET))
2403                 goto error;
2404 
2405             isp1760_hcd_set(hcd, PORT_SUSPEND);
2406             break;
2407         case USB_PORT_FEAT_POWER:
2408             if (isp1760_hcd_ppc_is_set(hcd))
2409                 isp1760_hcd_set(hcd, PORT_POWER);
2410             break;
2411         case USB_PORT_FEAT_RESET:
2412             if (isp1760_hcd_is_set(hcd, PORT_RESUME))
2413                 goto error;
2414             /* line status bits may report this as low speed,
2415              * which can be fine if this root hub has a
2416              * transaction translator built in.
2417              */
2418             if ((isp1760_hcd_is_set(hcd, PORT_CONNECT) &&
2419                  !isp1760_hcd_is_set(hcd, PORT_PE)) &&
2420                 (isp1760_hcd_read(hcd, PORT_LSTATUS) == 1)) {
2421                 isp1760_hcd_set(hcd, PORT_OWNER);
2422             } else {
2423                 isp1760_hcd_set(hcd, PORT_RESET);
2424                 isp1760_hcd_clear(hcd, PORT_PE);
2425 
2426                 /*
2427                  * caller must wait, then call GetPortStatus
2428                  * usb 2.0 spec says 50 ms resets on root
2429                  */
2430                 priv->reset_done = jiffies +
2431                     msecs_to_jiffies(50);
2432             }
2433             break;
2434         default:
2435             goto error;
2436         }
2437         break;
2438 
2439     default:
2440 error:
2441         /* "stall" on error */
2442         retval = -EPIPE;
2443     }
2444     spin_unlock_irqrestore(&priv->lock, flags);
2445     return retval;
2446 }
2447 
2448 static int isp1760_get_frame(struct usb_hcd *hcd)
2449 {
2450     struct isp1760_hcd *priv = hcd_to_priv(hcd);
2451     u32 fr;
2452 
2453     fr = isp1760_hcd_read(hcd, HC_FRINDEX);
2454     return (fr >> 3) % priv->periodic_size;
2455 }
2456 
2457 static void isp1760_stop(struct usb_hcd *hcd)
2458 {
2459     struct isp1760_hcd *priv = hcd_to_priv(hcd);
2460 
2461     del_timer(&errata2_timer);
2462 
2463     isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2464             NULL, 0);
2465     msleep(20);
2466 
2467     spin_lock_irq(&priv->lock);
2468     ehci_reset(hcd);
2469     /* Disable IRQ */
2470     isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN);
2471     spin_unlock_irq(&priv->lock);
2472 
2473     isp1760_hcd_clear(hcd, FLAG_CF);
2474 }
2475 
2476 static void isp1760_shutdown(struct usb_hcd *hcd)
2477 {
2478     isp1760_stop(hcd);
2479 
2480     isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN);
2481 
2482     isp1760_hcd_clear(hcd, CMD_RUN);
2483 }
2484 
2485 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2486                         struct usb_host_endpoint *ep)
2487 {
2488     struct isp1760_hcd *priv = hcd_to_priv(hcd);
2489     struct isp1760_qh *qh = ep->hcpriv;
2490     unsigned long spinflags;
2491 
2492     if (!qh)
2493         return;
2494 
2495     spin_lock_irqsave(&priv->lock, spinflags);
2496     qh->tt_buffer_dirty = 0;
2497     schedule_ptds(hcd);
2498     spin_unlock_irqrestore(&priv->lock, spinflags);
2499 }
2500 
2501 
2502 static const struct hc_driver isp1760_hc_driver = {
2503     .description        = "isp1760-hcd",
2504     .product_desc       = "NXP ISP1760 USB Host Controller",
2505     .hcd_priv_size      = sizeof(struct isp1760_hcd *),
2506     .irq            = isp1760_irq,
2507     .flags          = HCD_MEMORY | HCD_USB2,
2508     .reset          = isp1760_hc_setup,
2509     .start          = isp1760_run,
2510     .stop           = isp1760_stop,
2511     .shutdown       = isp1760_shutdown,
2512     .urb_enqueue        = isp1760_urb_enqueue,
2513     .urb_dequeue        = isp1760_urb_dequeue,
2514     .endpoint_disable   = isp1760_endpoint_disable,
2515     .get_frame_number   = isp1760_get_frame,
2516     .hub_status_data    = isp1760_hub_status_data,
2517     .hub_control        = isp1760_hub_control,
2518     .clear_tt_buffer_complete   = isp1760_clear_tt_buffer_complete,
2519 };
2520 
2521 int __init isp1760_init_kmem_once(void)
2522 {
2523     urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
2524             sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2525             SLAB_MEM_SPREAD, NULL);
2526 
2527     if (!urb_listitem_cachep)
2528         return -ENOMEM;
2529 
2530     qtd_cachep = kmem_cache_create("isp1760_qtd",
2531             sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2532             SLAB_MEM_SPREAD, NULL);
2533 
2534     if (!qtd_cachep)
2535         goto destroy_urb_listitem;
2536 
2537     qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2538             0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2539 
2540     if (!qh_cachep)
2541         goto destroy_qtd;
2542 
2543     return 0;
2544 
2545 destroy_qtd:
2546     kmem_cache_destroy(qtd_cachep);
2547 
2548 destroy_urb_listitem:
2549     kmem_cache_destroy(urb_listitem_cachep);
2550 
2551     return -ENOMEM;
2552 }
2553 
2554 void isp1760_deinit_kmem_cache(void)
2555 {
2556     kmem_cache_destroy(qtd_cachep);
2557     kmem_cache_destroy(qh_cachep);
2558     kmem_cache_destroy(urb_listitem_cachep);
2559 }
2560 
2561 int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem,
2562              int irq, unsigned long irqflags,
2563              struct device *dev)
2564 {
2565     const struct isp1760_memory_layout *mem_layout = priv->memory_layout;
2566     struct usb_hcd *hcd;
2567     int ret;
2568 
2569     hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2570     if (!hcd)
2571         return -ENOMEM;
2572 
2573     *(struct isp1760_hcd **)hcd->hcd_priv = priv;
2574 
2575     priv->hcd = hcd;
2576 
2577     priv->atl_slots = kcalloc(mem_layout->slot_num,
2578                   sizeof(struct isp1760_slotinfo), GFP_KERNEL);
2579     if (!priv->atl_slots) {
2580         ret = -ENOMEM;
2581         goto put_hcd;
2582     }
2583 
2584     priv->int_slots = kcalloc(mem_layout->slot_num,
2585                   sizeof(struct isp1760_slotinfo), GFP_KERNEL);
2586     if (!priv->int_slots) {
2587         ret = -ENOMEM;
2588         goto free_atl_slots;
2589     }
2590 
2591     init_memory(priv);
2592 
2593     hcd->irq = irq;
2594     hcd->rsrc_start = mem->start;
2595     hcd->rsrc_len = resource_size(mem);
2596 
2597     /* This driver doesn't support wakeup requests */
2598     hcd->cant_recv_wakeups = 1;
2599 
2600     ret = usb_add_hcd(hcd, irq, irqflags);
2601     if (ret)
2602         goto free_int_slots;
2603 
2604     device_wakeup_enable(hcd->self.controller);
2605 
2606     return 0;
2607 
2608 free_int_slots:
2609     kfree(priv->int_slots);
2610 free_atl_slots:
2611     kfree(priv->atl_slots);
2612 put_hcd:
2613     usb_put_hcd(hcd);
2614     return ret;
2615 }
2616 
2617 void isp1760_hcd_unregister(struct isp1760_hcd *priv)
2618 {
2619     if (!priv->hcd)
2620         return;
2621 
2622     usb_remove_hcd(priv->hcd);
2623     usb_put_hcd(priv->hcd);
2624     kfree(priv->atl_slots);
2625     kfree(priv->int_slots);
2626 }