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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for the NXP ISP1760 chip
0004  *
0005  * Copyright 2021 Linaro, Rui Miguel Silva
0006  * Copyright 2014 Laurent Pinchart
0007  * Copyright 2007 Sebastian Siewior
0008  *
0009  * Contacts:
0010  *  Sebastian Siewior <bigeasy@linutronix.de>
0011  *  Laurent Pinchart <laurent.pinchart@ideasonboard.com>
0012  *  Rui Miguel Silva <rui.silva@linaro.org>
0013  */
0014 
0015 #include <linux/delay.h>
0016 #include <linux/gpio/consumer.h>
0017 #include <linux/io.h>
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 #include <linux/regmap.h>
0021 #include <linux/slab.h>
0022 #include <linux/usb.h>
0023 
0024 #include "isp1760-core.h"
0025 #include "isp1760-hcd.h"
0026 #include "isp1760-regs.h"
0027 #include "isp1760-udc.h"
0028 
0029 static int isp1760_init_core(struct isp1760_device *isp)
0030 {
0031     struct isp1760_hcd *hcd = &isp->hcd;
0032     struct isp1760_udc *udc = &isp->udc;
0033     u32 otg_ctrl;
0034 
0035     /* Low-level chip reset */
0036     if (isp->rst_gpio) {
0037         gpiod_set_value_cansleep(isp->rst_gpio, 1);
0038         msleep(50);
0039         gpiod_set_value_cansleep(isp->rst_gpio, 0);
0040     }
0041 
0042     /*
0043      * Reset the host controller, including the CPU interface
0044      * configuration.
0045      */
0046     isp1760_field_set(hcd->fields, SW_RESET_RESET_ALL);
0047     msleep(100);
0048 
0049     /* Setup HW Mode Control: This assumes a level active-low interrupt */
0050     if ((isp->devflags & ISP1760_FLAG_ANALOG_OC) && hcd->is_isp1763) {
0051         dev_err(isp->dev, "isp1763 analog overcurrent not available\n");
0052         return -EINVAL;
0053     }
0054 
0055     if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_16)
0056         isp1760_field_clear(hcd->fields, HW_DATA_BUS_WIDTH);
0057     if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_8)
0058         isp1760_field_set(hcd->fields, HW_DATA_BUS_WIDTH);
0059     if (isp->devflags & ISP1760_FLAG_ANALOG_OC)
0060         isp1760_field_set(hcd->fields, HW_ANA_DIGI_OC);
0061     if (isp->devflags & ISP1760_FLAG_DACK_POL_HIGH)
0062         isp1760_field_set(hcd->fields, HW_DACK_POL_HIGH);
0063     if (isp->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
0064         isp1760_field_set(hcd->fields, HW_DREQ_POL_HIGH);
0065     if (isp->devflags & ISP1760_FLAG_INTR_POL_HIGH)
0066         isp1760_field_set(hcd->fields, HW_INTR_HIGH_ACT);
0067     if (isp->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
0068         isp1760_field_set(hcd->fields, HW_INTR_EDGE_TRIG);
0069 
0070     /*
0071      * The ISP1761 has a dedicated DC IRQ line but supports sharing the HC
0072      * IRQ line for both the host and device controllers. Hardcode IRQ
0073      * sharing for now and disable the DC interrupts globally to avoid
0074      * spurious interrupts during HCD registration.
0075      */
0076     if (isp->devflags & ISP1760_FLAG_ISP1761) {
0077         isp1760_reg_write(udc->regs, ISP176x_DC_MODE, 0);
0078         isp1760_field_set(hcd->fields, HW_COMN_IRQ);
0079     }
0080 
0081     /*
0082      * PORT 1 Control register of the ISP1760 is the OTG control register
0083      * on ISP1761.
0084      *
0085      * TODO: Really support OTG. For now we configure port 1 in device mode
0086      */
0087     if (isp->devflags & ISP1760_FLAG_ISP1761) {
0088         if (isp->devflags & ISP1760_FLAG_PERIPHERAL_EN) {
0089             otg_ctrl = (ISP176x_HW_DM_PULLDOWN_CLEAR |
0090                     ISP176x_HW_DP_PULLDOWN_CLEAR |
0091                     ISP176x_HW_OTG_DISABLE);
0092         } else {
0093             otg_ctrl = (ISP176x_HW_SW_SEL_HC_DC_CLEAR |
0094                     ISP176x_HW_VBUS_DRV |
0095                     ISP176x_HW_SEL_CP_EXT);
0096         }
0097         isp1760_reg_write(hcd->regs, ISP176x_HC_OTG_CTRL, otg_ctrl);
0098     }
0099 
0100     dev_info(isp->dev, "%s bus width: %u, oc: %s\n",
0101          hcd->is_isp1763 ? "isp1763" : "isp1760",
0102          isp->devflags & ISP1760_FLAG_BUS_WIDTH_8 ? 8 :
0103          isp->devflags & ISP1760_FLAG_BUS_WIDTH_16 ? 16 : 32,
0104          hcd->is_isp1763 ? "not available" :
0105          isp->devflags & ISP1760_FLAG_ANALOG_OC ? "analog" : "digital");
0106 
0107     return 0;
0108 }
0109 
0110 void isp1760_set_pullup(struct isp1760_device *isp, bool enable)
0111 {
0112     struct isp1760_udc *udc = &isp->udc;
0113 
0114     if (enable)
0115         isp1760_field_set(udc->fields, HW_DP_PULLUP);
0116     else
0117         isp1760_field_set(udc->fields, HW_DP_PULLUP_CLEAR);
0118 }
0119 
0120 /*
0121  * ISP1760/61:
0122  *
0123  * 60kb divided in:
0124  * - 32 blocks @ 256  bytes
0125  * - 20 blocks @ 1024 bytes
0126  * -  4 blocks @ 8192 bytes
0127  */
0128 static const struct isp1760_memory_layout isp176x_memory_conf = {
0129     .blocks[0]      = 32,
0130     .blocks_size[0]     = 256,
0131     .blocks[1]      = 20,
0132     .blocks_size[1]     = 1024,
0133     .blocks[2]      = 4,
0134     .blocks_size[2]     = 8192,
0135 
0136     .slot_num       = 32,
0137     .payload_blocks     = 32 + 20 + 4,
0138     .payload_area_size  = 0xf000,
0139 };
0140 
0141 /*
0142  * ISP1763:
0143  *
0144  * 20kb divided in:
0145  * - 8 blocks @ 256  bytes
0146  * - 2 blocks @ 1024 bytes
0147  * - 4 blocks @ 4096 bytes
0148  */
0149 static const struct isp1760_memory_layout isp1763_memory_conf = {
0150     .blocks[0]      = 8,
0151     .blocks_size[0]     = 256,
0152     .blocks[1]      = 2,
0153     .blocks_size[1]     = 1024,
0154     .blocks[2]      = 4,
0155     .blocks_size[2]     = 4096,
0156 
0157     .slot_num       = 16,
0158     .payload_blocks     = 8 + 2 + 4,
0159     .payload_area_size  = 0x5000,
0160 };
0161 
0162 static const struct regmap_range isp176x_hc_volatile_ranges[] = {
0163     regmap_reg_range(ISP176x_HC_USBCMD, ISP176x_HC_ATL_PTD_LASTPTD),
0164     regmap_reg_range(ISP176x_HC_BUFFER_STATUS, ISP176x_HC_MEMORY),
0165     regmap_reg_range(ISP176x_HC_INTERRUPT, ISP176x_HC_OTG_CTRL_CLEAR),
0166 };
0167 
0168 static const struct regmap_access_table isp176x_hc_volatile_table = {
0169     .yes_ranges = isp176x_hc_volatile_ranges,
0170     .n_yes_ranges   = ARRAY_SIZE(isp176x_hc_volatile_ranges),
0171 };
0172 
0173 static const struct regmap_config isp1760_hc_regmap_conf = {
0174     .name = "isp1760-hc",
0175     .reg_bits = 16,
0176     .reg_stride = 4,
0177     .val_bits = 32,
0178     .fast_io = true,
0179     .max_register = ISP176x_HC_OTG_CTRL_CLEAR,
0180     .volatile_table = &isp176x_hc_volatile_table,
0181 };
0182 
0183 static const struct reg_field isp1760_hc_reg_fields[] = {
0184     [HCS_PPC]       = REG_FIELD(ISP176x_HC_HCSPARAMS, 4, 4),
0185     [HCS_N_PORTS]       = REG_FIELD(ISP176x_HC_HCSPARAMS, 0, 3),
0186     [HCC_ISOC_CACHE]    = REG_FIELD(ISP176x_HC_HCCPARAMS, 7, 7),
0187     [HCC_ISOC_THRES]    = REG_FIELD(ISP176x_HC_HCCPARAMS, 4, 6),
0188     [CMD_LRESET]        = REG_FIELD(ISP176x_HC_USBCMD, 7, 7),
0189     [CMD_RESET]     = REG_FIELD(ISP176x_HC_USBCMD, 1, 1),
0190     [CMD_RUN]       = REG_FIELD(ISP176x_HC_USBCMD, 0, 0),
0191     [STS_PCD]       = REG_FIELD(ISP176x_HC_USBSTS, 2, 2),
0192     [HC_FRINDEX]        = REG_FIELD(ISP176x_HC_FRINDEX, 0, 13),
0193     [FLAG_CF]       = REG_FIELD(ISP176x_HC_CONFIGFLAG, 0, 0),
0194     [HC_ISO_PTD_DONEMAP]    = REG_FIELD(ISP176x_HC_ISO_PTD_DONEMAP, 0, 31),
0195     [HC_ISO_PTD_SKIPMAP]    = REG_FIELD(ISP176x_HC_ISO_PTD_SKIPMAP, 0, 31),
0196     [HC_ISO_PTD_LASTPTD]    = REG_FIELD(ISP176x_HC_ISO_PTD_LASTPTD, 0, 31),
0197     [HC_INT_PTD_DONEMAP]    = REG_FIELD(ISP176x_HC_INT_PTD_DONEMAP, 0, 31),
0198     [HC_INT_PTD_SKIPMAP]    = REG_FIELD(ISP176x_HC_INT_PTD_SKIPMAP, 0, 31),
0199     [HC_INT_PTD_LASTPTD]    = REG_FIELD(ISP176x_HC_INT_PTD_LASTPTD, 0, 31),
0200     [HC_ATL_PTD_DONEMAP]    = REG_FIELD(ISP176x_HC_ATL_PTD_DONEMAP, 0, 31),
0201     [HC_ATL_PTD_SKIPMAP]    = REG_FIELD(ISP176x_HC_ATL_PTD_SKIPMAP, 0, 31),
0202     [HC_ATL_PTD_LASTPTD]    = REG_FIELD(ISP176x_HC_ATL_PTD_LASTPTD, 0, 31),
0203     [PORT_OWNER]        = REG_FIELD(ISP176x_HC_PORTSC1, 13, 13),
0204     [PORT_POWER]        = REG_FIELD(ISP176x_HC_PORTSC1, 12, 12),
0205     [PORT_LSTATUS]      = REG_FIELD(ISP176x_HC_PORTSC1, 10, 11),
0206     [PORT_RESET]        = REG_FIELD(ISP176x_HC_PORTSC1, 8, 8),
0207     [PORT_SUSPEND]      = REG_FIELD(ISP176x_HC_PORTSC1, 7, 7),
0208     [PORT_RESUME]       = REG_FIELD(ISP176x_HC_PORTSC1, 6, 6),
0209     [PORT_PE]       = REG_FIELD(ISP176x_HC_PORTSC1, 2, 2),
0210     [PORT_CSC]      = REG_FIELD(ISP176x_HC_PORTSC1, 1, 1),
0211     [PORT_CONNECT]      = REG_FIELD(ISP176x_HC_PORTSC1, 0, 0),
0212     [ALL_ATX_RESET]     = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 31, 31),
0213     [HW_ANA_DIGI_OC]    = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 15, 15),
0214     [HW_COMN_IRQ]       = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 10, 10),
0215     [HW_DATA_BUS_WIDTH] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 8, 8),
0216     [HW_DACK_POL_HIGH]  = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 6, 6),
0217     [HW_DREQ_POL_HIGH]  = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 5, 5),
0218     [HW_INTR_HIGH_ACT]  = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 2, 2),
0219     [HW_INTR_EDGE_TRIG] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 1, 1),
0220     [HW_GLOBAL_INTR_EN] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 0, 0),
0221     [HC_CHIP_REV]       = REG_FIELD(ISP176x_HC_CHIP_ID, 16, 31),
0222     [HC_CHIP_ID_HIGH]   = REG_FIELD(ISP176x_HC_CHIP_ID, 8, 15),
0223     [HC_CHIP_ID_LOW]    = REG_FIELD(ISP176x_HC_CHIP_ID, 0, 7),
0224     [HC_SCRATCH]        = REG_FIELD(ISP176x_HC_SCRATCH, 0, 31),
0225     [SW_RESET_RESET_ALL]    = REG_FIELD(ISP176x_HC_RESET, 0, 0),
0226     [ISO_BUF_FILL]      = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 2, 2),
0227     [INT_BUF_FILL]      = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 1, 1),
0228     [ATL_BUF_FILL]      = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 0, 0),
0229     [MEM_BANK_SEL]      = REG_FIELD(ISP176x_HC_MEMORY, 16, 17),
0230     [MEM_START_ADDR]    = REG_FIELD(ISP176x_HC_MEMORY, 0, 15),
0231     [HC_INTERRUPT]      = REG_FIELD(ISP176x_HC_INTERRUPT, 0, 9),
0232     [HC_ATL_IRQ_ENABLE] = REG_FIELD(ISP176x_HC_INTERRUPT_ENABLE, 8, 8),
0233     [HC_INT_IRQ_ENABLE] = REG_FIELD(ISP176x_HC_INTERRUPT_ENABLE, 7, 7),
0234     [HC_ISO_IRQ_MASK_OR]    = REG_FIELD(ISP176x_HC_ISO_IRQ_MASK_OR, 0, 31),
0235     [HC_INT_IRQ_MASK_OR]    = REG_FIELD(ISP176x_HC_INT_IRQ_MASK_OR, 0, 31),
0236     [HC_ATL_IRQ_MASK_OR]    = REG_FIELD(ISP176x_HC_ATL_IRQ_MASK_OR, 0, 31),
0237     [HC_ISO_IRQ_MASK_AND]   = REG_FIELD(ISP176x_HC_ISO_IRQ_MASK_AND, 0, 31),
0238     [HC_INT_IRQ_MASK_AND]   = REG_FIELD(ISP176x_HC_INT_IRQ_MASK_AND, 0, 31),
0239     [HC_ATL_IRQ_MASK_AND]   = REG_FIELD(ISP176x_HC_ATL_IRQ_MASK_AND, 0, 31),
0240     [HW_OTG_DISABLE_CLEAR]  = REG_FIELD(ISP176x_HC_OTG_CTRL, 26, 26),
0241     [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL, 23, 23),
0242     [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL, 20, 20),
0243     [HW_SEL_CP_EXT_CLEAR]   = REG_FIELD(ISP176x_HC_OTG_CTRL, 19, 19),
0244     [HW_DM_PULLDOWN_CLEAR]  = REG_FIELD(ISP176x_HC_OTG_CTRL, 18, 18),
0245     [HW_DP_PULLDOWN_CLEAR]  = REG_FIELD(ISP176x_HC_OTG_CTRL, 17, 17),
0246     [HW_DP_PULLUP_CLEAR]    = REG_FIELD(ISP176x_HC_OTG_CTRL, 16, 16),
0247     [HW_OTG_DISABLE]    = REG_FIELD(ISP176x_HC_OTG_CTRL, 10, 10),
0248     [HW_SW_SEL_HC_DC]   = REG_FIELD(ISP176x_HC_OTG_CTRL, 7, 7),
0249     [HW_VBUS_DRV]       = REG_FIELD(ISP176x_HC_OTG_CTRL, 4, 4),
0250     [HW_SEL_CP_EXT]     = REG_FIELD(ISP176x_HC_OTG_CTRL, 3, 3),
0251     [HW_DM_PULLDOWN]    = REG_FIELD(ISP176x_HC_OTG_CTRL, 2, 2),
0252     [HW_DP_PULLDOWN]    = REG_FIELD(ISP176x_HC_OTG_CTRL, 1, 1),
0253     [HW_DP_PULLUP]      = REG_FIELD(ISP176x_HC_OTG_CTRL, 0, 0),
0254     /* Make sure the array is sized properly during compilation */
0255     [HC_FIELD_MAX]      = {},
0256 };
0257 
0258 static const struct reg_field isp1763_hc_reg_fields[] = {
0259     [CMD_LRESET]        = REG_FIELD(ISP1763_HC_USBCMD, 7, 7),
0260     [CMD_RESET]     = REG_FIELD(ISP1763_HC_USBCMD, 1, 1),
0261     [CMD_RUN]       = REG_FIELD(ISP1763_HC_USBCMD, 0, 0),
0262     [STS_PCD]       = REG_FIELD(ISP1763_HC_USBSTS, 2, 2),
0263     [HC_FRINDEX]        = REG_FIELD(ISP1763_HC_FRINDEX, 0, 13),
0264     [FLAG_CF]       = REG_FIELD(ISP1763_HC_CONFIGFLAG, 0, 0),
0265     [HC_ISO_PTD_DONEMAP]    = REG_FIELD(ISP1763_HC_ISO_PTD_DONEMAP, 0, 15),
0266     [HC_ISO_PTD_SKIPMAP]    = REG_FIELD(ISP1763_HC_ISO_PTD_SKIPMAP, 0, 15),
0267     [HC_ISO_PTD_LASTPTD]    = REG_FIELD(ISP1763_HC_ISO_PTD_LASTPTD, 0, 15),
0268     [HC_INT_PTD_DONEMAP]    = REG_FIELD(ISP1763_HC_INT_PTD_DONEMAP, 0, 15),
0269     [HC_INT_PTD_SKIPMAP]    = REG_FIELD(ISP1763_HC_INT_PTD_SKIPMAP, 0, 15),
0270     [HC_INT_PTD_LASTPTD]    = REG_FIELD(ISP1763_HC_INT_PTD_LASTPTD, 0, 15),
0271     [HC_ATL_PTD_DONEMAP]    = REG_FIELD(ISP1763_HC_ATL_PTD_DONEMAP, 0, 15),
0272     [HC_ATL_PTD_SKIPMAP]    = REG_FIELD(ISP1763_HC_ATL_PTD_SKIPMAP, 0, 15),
0273     [HC_ATL_PTD_LASTPTD]    = REG_FIELD(ISP1763_HC_ATL_PTD_LASTPTD, 0, 15),
0274     [PORT_OWNER]        = REG_FIELD(ISP1763_HC_PORTSC1, 13, 13),
0275     [PORT_POWER]        = REG_FIELD(ISP1763_HC_PORTSC1, 12, 12),
0276     [PORT_LSTATUS]      = REG_FIELD(ISP1763_HC_PORTSC1, 10, 11),
0277     [PORT_RESET]        = REG_FIELD(ISP1763_HC_PORTSC1, 8, 8),
0278     [PORT_SUSPEND]      = REG_FIELD(ISP1763_HC_PORTSC1, 7, 7),
0279     [PORT_RESUME]       = REG_FIELD(ISP1763_HC_PORTSC1, 6, 6),
0280     [PORT_PE]       = REG_FIELD(ISP1763_HC_PORTSC1, 2, 2),
0281     [PORT_CSC]      = REG_FIELD(ISP1763_HC_PORTSC1, 1, 1),
0282     [PORT_CONNECT]      = REG_FIELD(ISP1763_HC_PORTSC1, 0, 0),
0283     [HW_DATA_BUS_WIDTH] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 4, 4),
0284     [HW_DACK_POL_HIGH]  = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 6, 6),
0285     [HW_DREQ_POL_HIGH]  = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 5, 5),
0286     [HW_INTF_LOCK]      = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 3, 3),
0287     [HW_INTR_HIGH_ACT]  = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 2, 2),
0288     [HW_INTR_EDGE_TRIG] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 1, 1),
0289     [HW_GLOBAL_INTR_EN] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 0, 0),
0290     [SW_RESET_RESET_ATX]    = REG_FIELD(ISP1763_HC_RESET, 3, 3),
0291     [SW_RESET_RESET_ALL]    = REG_FIELD(ISP1763_HC_RESET, 0, 0),
0292     [HC_CHIP_ID_HIGH]   = REG_FIELD(ISP1763_HC_CHIP_ID, 0, 15),
0293     [HC_CHIP_ID_LOW]    = REG_FIELD(ISP1763_HC_CHIP_REV, 8, 15),
0294     [HC_CHIP_REV]       = REG_FIELD(ISP1763_HC_CHIP_REV, 0, 7),
0295     [HC_SCRATCH]        = REG_FIELD(ISP1763_HC_SCRATCH, 0, 15),
0296     [ISO_BUF_FILL]      = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 2, 2),
0297     [INT_BUF_FILL]      = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 1, 1),
0298     [ATL_BUF_FILL]      = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 0, 0),
0299     [MEM_START_ADDR]    = REG_FIELD(ISP1763_HC_MEMORY, 0, 15),
0300     [HC_DATA]       = REG_FIELD(ISP1763_HC_DATA, 0, 15),
0301     [HC_INTERRUPT]      = REG_FIELD(ISP1763_HC_INTERRUPT, 0, 10),
0302     [HC_ATL_IRQ_ENABLE] = REG_FIELD(ISP1763_HC_INTERRUPT_ENABLE, 8, 8),
0303     [HC_INT_IRQ_ENABLE] = REG_FIELD(ISP1763_HC_INTERRUPT_ENABLE, 7, 7),
0304     [HC_ISO_IRQ_MASK_OR]    = REG_FIELD(ISP1763_HC_ISO_IRQ_MASK_OR, 0, 15),
0305     [HC_INT_IRQ_MASK_OR]    = REG_FIELD(ISP1763_HC_INT_IRQ_MASK_OR, 0, 15),
0306     [HC_ATL_IRQ_MASK_OR]    = REG_FIELD(ISP1763_HC_ATL_IRQ_MASK_OR, 0, 15),
0307     [HC_ISO_IRQ_MASK_AND]   = REG_FIELD(ISP1763_HC_ISO_IRQ_MASK_AND, 0, 15),
0308     [HC_INT_IRQ_MASK_AND]   = REG_FIELD(ISP1763_HC_INT_IRQ_MASK_AND, 0, 15),
0309     [HC_ATL_IRQ_MASK_AND]   = REG_FIELD(ISP1763_HC_ATL_IRQ_MASK_AND, 0, 15),
0310     [HW_HC_2_DIS]       = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 15, 15),
0311     [HW_OTG_DISABLE]    = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 10, 10),
0312     [HW_SW_SEL_HC_DC]   = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 7, 7),
0313     [HW_VBUS_DRV]       = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 4, 4),
0314     [HW_SEL_CP_EXT]     = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 3, 3),
0315     [HW_DM_PULLDOWN]    = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 2, 2),
0316     [HW_DP_PULLDOWN]    = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 1, 1),
0317     [HW_DP_PULLUP]      = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 0, 0),
0318     [HW_HC_2_DIS_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 15, 15),
0319     [HW_OTG_DISABLE_CLEAR]  = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 10, 10),
0320     [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 7, 7),
0321     [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 4, 4),
0322     [HW_SEL_CP_EXT_CLEAR]   = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 3, 3),
0323     [HW_DM_PULLDOWN_CLEAR]  = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 2, 2),
0324     [HW_DP_PULLDOWN_CLEAR]  = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 1, 1),
0325     [HW_DP_PULLUP_CLEAR]    = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 0, 0),
0326     /* Make sure the array is sized properly during compilation */
0327     [HC_FIELD_MAX]      = {},
0328 };
0329 
0330 static const struct regmap_range isp1763_hc_volatile_ranges[] = {
0331     regmap_reg_range(ISP1763_HC_USBCMD, ISP1763_HC_ATL_PTD_LASTPTD),
0332     regmap_reg_range(ISP1763_HC_BUFFER_STATUS, ISP1763_HC_DATA),
0333     regmap_reg_range(ISP1763_HC_INTERRUPT, ISP1763_HC_OTG_CTRL_CLEAR),
0334 };
0335 
0336 static const struct regmap_access_table isp1763_hc_volatile_table = {
0337     .yes_ranges = isp1763_hc_volatile_ranges,
0338     .n_yes_ranges   = ARRAY_SIZE(isp1763_hc_volatile_ranges),
0339 };
0340 
0341 static const struct regmap_config isp1763_hc_regmap_conf = {
0342     .name = "isp1763-hc",
0343     .reg_bits = 8,
0344     .reg_stride = 2,
0345     .val_bits = 16,
0346     .fast_io = true,
0347     .max_register = ISP1763_HC_OTG_CTRL_CLEAR,
0348     .volatile_table = &isp1763_hc_volatile_table,
0349 };
0350 
0351 static const struct regmap_range isp176x_dc_volatile_ranges[] = {
0352     regmap_reg_range(ISP176x_DC_EPMAXPKTSZ, ISP176x_DC_EPTYPE),
0353     regmap_reg_range(ISP176x_DC_BUFLEN, ISP176x_DC_EPINDEX),
0354 };
0355 
0356 static const struct regmap_access_table isp176x_dc_volatile_table = {
0357     .yes_ranges = isp176x_dc_volatile_ranges,
0358     .n_yes_ranges   = ARRAY_SIZE(isp176x_dc_volatile_ranges),
0359 };
0360 
0361 static const struct regmap_config isp1761_dc_regmap_conf = {
0362     .name = "isp1761-dc",
0363     .reg_bits = 16,
0364     .reg_stride = 4,
0365     .val_bits = 32,
0366     .fast_io = true,
0367     .max_register = ISP176x_DC_TESTMODE,
0368     .volatile_table = &isp176x_dc_volatile_table,
0369 };
0370 
0371 static const struct reg_field isp1761_dc_reg_fields[] = {
0372     [DC_DEVEN]      = REG_FIELD(ISP176x_DC_ADDRESS, 7, 7),
0373     [DC_DEVADDR]        = REG_FIELD(ISP176x_DC_ADDRESS, 0, 6),
0374     [DC_VBUSSTAT]       = REG_FIELD(ISP176x_DC_MODE, 8, 8),
0375     [DC_SFRESET]        = REG_FIELD(ISP176x_DC_MODE, 4, 4),
0376     [DC_GLINTENA]       = REG_FIELD(ISP176x_DC_MODE, 3, 3),
0377     [DC_CDBGMOD_ACK]    = REG_FIELD(ISP176x_DC_INTCONF, 6, 6),
0378     [DC_DDBGMODIN_ACK]  = REG_FIELD(ISP176x_DC_INTCONF, 4, 4),
0379     [DC_DDBGMODOUT_ACK] = REG_FIELD(ISP176x_DC_INTCONF, 2, 2),
0380     [DC_INTPOL]     = REG_FIELD(ISP176x_DC_INTCONF, 0, 0),
0381     [DC_IEPRXTX_7]      = REG_FIELD(ISP176x_DC_INTENABLE, 25, 25),
0382     [DC_IEPRXTX_6]      = REG_FIELD(ISP176x_DC_INTENABLE, 23, 23),
0383     [DC_IEPRXTX_5]      = REG_FIELD(ISP176x_DC_INTENABLE, 21, 21),
0384     [DC_IEPRXTX_4]      = REG_FIELD(ISP176x_DC_INTENABLE, 19, 19),
0385     [DC_IEPRXTX_3]      = REG_FIELD(ISP176x_DC_INTENABLE, 17, 17),
0386     [DC_IEPRXTX_2]      = REG_FIELD(ISP176x_DC_INTENABLE, 15, 15),
0387     [DC_IEPRXTX_1]      = REG_FIELD(ISP176x_DC_INTENABLE, 13, 13),
0388     [DC_IEPRXTX_0]      = REG_FIELD(ISP176x_DC_INTENABLE, 11, 11),
0389     [DC_IEP0SETUP]      = REG_FIELD(ISP176x_DC_INTENABLE, 8, 8),
0390     [DC_IEVBUS]     = REG_FIELD(ISP176x_DC_INTENABLE, 7, 7),
0391     [DC_IEHS_STA]       = REG_FIELD(ISP176x_DC_INTENABLE, 5, 5),
0392     [DC_IERESM]     = REG_FIELD(ISP176x_DC_INTENABLE, 4, 4),
0393     [DC_IESUSP]     = REG_FIELD(ISP176x_DC_INTENABLE, 3, 3),
0394     [DC_IEBRST]     = REG_FIELD(ISP176x_DC_INTENABLE, 0, 0),
0395     [DC_EP0SETUP]       = REG_FIELD(ISP176x_DC_EPINDEX, 5, 5),
0396     [DC_ENDPIDX]        = REG_FIELD(ISP176x_DC_EPINDEX, 1, 4),
0397     [DC_EPDIR]      = REG_FIELD(ISP176x_DC_EPINDEX, 0, 0),
0398     [DC_CLBUF]      = REG_FIELD(ISP176x_DC_CTRLFUNC, 4, 4),
0399     [DC_VENDP]      = REG_FIELD(ISP176x_DC_CTRLFUNC, 3, 3),
0400     [DC_DSEN]       = REG_FIELD(ISP176x_DC_CTRLFUNC, 2, 2),
0401     [DC_STATUS]     = REG_FIELD(ISP176x_DC_CTRLFUNC, 1, 1),
0402     [DC_STALL]      = REG_FIELD(ISP176x_DC_CTRLFUNC, 0, 0),
0403     [DC_BUFLEN]     = REG_FIELD(ISP176x_DC_BUFLEN, 0, 15),
0404     [DC_FFOSZ]      = REG_FIELD(ISP176x_DC_EPMAXPKTSZ, 0, 10),
0405     [DC_EPENABLE]       = REG_FIELD(ISP176x_DC_EPTYPE, 3, 3),
0406     [DC_ENDPTYP]        = REG_FIELD(ISP176x_DC_EPTYPE, 0, 1),
0407     [DC_UFRAMENUM]      = REG_FIELD(ISP176x_DC_FRAMENUM, 11, 13),
0408     [DC_FRAMENUM]       = REG_FIELD(ISP176x_DC_FRAMENUM, 0, 10),
0409     [DC_CHIP_ID_HIGH]   = REG_FIELD(ISP176x_DC_CHIPID, 16, 31),
0410     [DC_CHIP_ID_LOW]    = REG_FIELD(ISP176x_DC_CHIPID, 0, 15),
0411     [DC_SCRATCH]        = REG_FIELD(ISP176x_DC_SCRATCH, 0, 15),
0412     /* Make sure the array is sized properly during compilation */
0413     [DC_FIELD_MAX]      = {},
0414 };
0415 
0416 static const struct regmap_range isp1763_dc_volatile_ranges[] = {
0417     regmap_reg_range(ISP1763_DC_EPMAXPKTSZ, ISP1763_DC_EPTYPE),
0418     regmap_reg_range(ISP1763_DC_BUFLEN, ISP1763_DC_EPINDEX),
0419 };
0420 
0421 static const struct regmap_access_table isp1763_dc_volatile_table = {
0422     .yes_ranges = isp1763_dc_volatile_ranges,
0423     .n_yes_ranges   = ARRAY_SIZE(isp1763_dc_volatile_ranges),
0424 };
0425 
0426 static const struct reg_field isp1763_dc_reg_fields[] = {
0427     [DC_DEVEN]      = REG_FIELD(ISP1763_DC_ADDRESS, 7, 7),
0428     [DC_DEVADDR]        = REG_FIELD(ISP1763_DC_ADDRESS, 0, 6),
0429     [DC_VBUSSTAT]       = REG_FIELD(ISP1763_DC_MODE, 8, 8),
0430     [DC_SFRESET]        = REG_FIELD(ISP1763_DC_MODE, 4, 4),
0431     [DC_GLINTENA]       = REG_FIELD(ISP1763_DC_MODE, 3, 3),
0432     [DC_CDBGMOD_ACK]    = REG_FIELD(ISP1763_DC_INTCONF, 6, 6),
0433     [DC_DDBGMODIN_ACK]  = REG_FIELD(ISP1763_DC_INTCONF, 4, 4),
0434     [DC_DDBGMODOUT_ACK] = REG_FIELD(ISP1763_DC_INTCONF, 2, 2),
0435     [DC_INTPOL]     = REG_FIELD(ISP1763_DC_INTCONF, 0, 0),
0436     [DC_IEPRXTX_7]      = REG_FIELD(ISP1763_DC_INTENABLE, 25, 25),
0437     [DC_IEPRXTX_6]      = REG_FIELD(ISP1763_DC_INTENABLE, 23, 23),
0438     [DC_IEPRXTX_5]      = REG_FIELD(ISP1763_DC_INTENABLE, 21, 21),
0439     [DC_IEPRXTX_4]      = REG_FIELD(ISP1763_DC_INTENABLE, 19, 19),
0440     [DC_IEPRXTX_3]      = REG_FIELD(ISP1763_DC_INTENABLE, 17, 17),
0441     [DC_IEPRXTX_2]      = REG_FIELD(ISP1763_DC_INTENABLE, 15, 15),
0442     [DC_IEPRXTX_1]      = REG_FIELD(ISP1763_DC_INTENABLE, 13, 13),
0443     [DC_IEPRXTX_0]      = REG_FIELD(ISP1763_DC_INTENABLE, 11, 11),
0444     [DC_IEP0SETUP]      = REG_FIELD(ISP1763_DC_INTENABLE, 8, 8),
0445     [DC_IEVBUS]     = REG_FIELD(ISP1763_DC_INTENABLE, 7, 7),
0446     [DC_IEHS_STA]       = REG_FIELD(ISP1763_DC_INTENABLE, 5, 5),
0447     [DC_IERESM]     = REG_FIELD(ISP1763_DC_INTENABLE, 4, 4),
0448     [DC_IESUSP]     = REG_FIELD(ISP1763_DC_INTENABLE, 3, 3),
0449     [DC_IEBRST]     = REG_FIELD(ISP1763_DC_INTENABLE, 0, 0),
0450     [DC_EP0SETUP]       = REG_FIELD(ISP1763_DC_EPINDEX, 5, 5),
0451     [DC_ENDPIDX]        = REG_FIELD(ISP1763_DC_EPINDEX, 1, 4),
0452     [DC_EPDIR]      = REG_FIELD(ISP1763_DC_EPINDEX, 0, 0),
0453     [DC_CLBUF]      = REG_FIELD(ISP1763_DC_CTRLFUNC, 4, 4),
0454     [DC_VENDP]      = REG_FIELD(ISP1763_DC_CTRLFUNC, 3, 3),
0455     [DC_DSEN]       = REG_FIELD(ISP1763_DC_CTRLFUNC, 2, 2),
0456     [DC_STATUS]     = REG_FIELD(ISP1763_DC_CTRLFUNC, 1, 1),
0457     [DC_STALL]      = REG_FIELD(ISP1763_DC_CTRLFUNC, 0, 0),
0458     [DC_BUFLEN]     = REG_FIELD(ISP1763_DC_BUFLEN, 0, 15),
0459     [DC_FFOSZ]      = REG_FIELD(ISP1763_DC_EPMAXPKTSZ, 0, 10),
0460     [DC_EPENABLE]       = REG_FIELD(ISP1763_DC_EPTYPE, 3, 3),
0461     [DC_ENDPTYP]        = REG_FIELD(ISP1763_DC_EPTYPE, 0, 1),
0462     [DC_UFRAMENUM]      = REG_FIELD(ISP1763_DC_FRAMENUM, 11, 13),
0463     [DC_FRAMENUM]       = REG_FIELD(ISP1763_DC_FRAMENUM, 0, 10),
0464     [DC_CHIP_ID_HIGH]   = REG_FIELD(ISP1763_DC_CHIPID_HIGH, 0, 15),
0465     [DC_CHIP_ID_LOW]    = REG_FIELD(ISP1763_DC_CHIPID_LOW, 0, 15),
0466     [DC_SCRATCH]        = REG_FIELD(ISP1763_DC_SCRATCH, 0, 15),
0467     /* Make sure the array is sized properly during compilation */
0468     [DC_FIELD_MAX]      = {},
0469 };
0470 
0471 static const struct regmap_config isp1763_dc_regmap_conf = {
0472     .name = "isp1763-dc",
0473     .reg_bits = 8,
0474     .reg_stride = 2,
0475     .val_bits = 16,
0476     .fast_io = true,
0477     .max_register = ISP1763_DC_TESTMODE,
0478     .volatile_table = &isp1763_dc_volatile_table,
0479 };
0480 
0481 int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
0482              struct device *dev, unsigned int devflags)
0483 {
0484     const struct regmap_config *hc_regmap;
0485     const struct reg_field *hc_reg_fields;
0486     const struct regmap_config *dc_regmap;
0487     const struct reg_field *dc_reg_fields;
0488     struct isp1760_device *isp;
0489     struct isp1760_hcd *hcd;
0490     struct isp1760_udc *udc;
0491     struct regmap_field *f;
0492     bool udc_enabled;
0493     int ret;
0494     int i;
0495 
0496     /*
0497      * If neither the HCD not the UDC is enabled return an error, as no
0498      * device would be registered.
0499      */
0500     udc_enabled = ((devflags & ISP1760_FLAG_ISP1763) ||
0501                (devflags & ISP1760_FLAG_ISP1761));
0502 
0503     if ((!IS_ENABLED(CONFIG_USB_ISP1760_HCD) || usb_disabled()) &&
0504         (!udc_enabled || !IS_ENABLED(CONFIG_USB_ISP1761_UDC)))
0505         return -ENODEV;
0506 
0507     isp = devm_kzalloc(dev, sizeof(*isp), GFP_KERNEL);
0508     if (!isp)
0509         return -ENOMEM;
0510 
0511     isp->dev = dev;
0512     isp->devflags = devflags;
0513     hcd = &isp->hcd;
0514     udc = &isp->udc;
0515 
0516     hcd->is_isp1763 = !!(devflags & ISP1760_FLAG_ISP1763);
0517     udc->is_isp1763 = !!(devflags & ISP1760_FLAG_ISP1763);
0518 
0519     if (!hcd->is_isp1763 && (devflags & ISP1760_FLAG_BUS_WIDTH_8)) {
0520         dev_err(dev, "isp1760/61 do not support data width 8\n");
0521         return -EINVAL;
0522     }
0523 
0524     if (hcd->is_isp1763) {
0525         hc_regmap = &isp1763_hc_regmap_conf;
0526         hc_reg_fields = &isp1763_hc_reg_fields[0];
0527         dc_regmap = &isp1763_dc_regmap_conf;
0528         dc_reg_fields = &isp1763_dc_reg_fields[0];
0529     } else {
0530         hc_regmap = &isp1760_hc_regmap_conf;
0531         hc_reg_fields = &isp1760_hc_reg_fields[0];
0532         dc_regmap = &isp1761_dc_regmap_conf;
0533         dc_reg_fields = &isp1761_dc_reg_fields[0];
0534     }
0535 
0536     isp->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
0537     if (IS_ERR(isp->rst_gpio))
0538         return PTR_ERR(isp->rst_gpio);
0539 
0540     hcd->base = devm_ioremap_resource(dev, mem);
0541     if (IS_ERR(hcd->base))
0542         return PTR_ERR(hcd->base);
0543 
0544     hcd->regs = devm_regmap_init_mmio(dev, hcd->base, hc_regmap);
0545     if (IS_ERR(hcd->regs))
0546         return PTR_ERR(hcd->regs);
0547 
0548     for (i = 0; i < HC_FIELD_MAX; i++) {
0549         f = devm_regmap_field_alloc(dev, hcd->regs, hc_reg_fields[i]);
0550         if (IS_ERR(f))
0551             return PTR_ERR(f);
0552 
0553         hcd->fields[i] = f;
0554     }
0555 
0556     udc->regs = devm_regmap_init_mmio(dev, hcd->base, dc_regmap);
0557     if (IS_ERR(udc->regs))
0558         return PTR_ERR(udc->regs);
0559 
0560     for (i = 0; i < DC_FIELD_MAX; i++) {
0561         f = devm_regmap_field_alloc(dev, udc->regs, dc_reg_fields[i]);
0562         if (IS_ERR(f))
0563             return PTR_ERR(f);
0564 
0565         udc->fields[i] = f;
0566     }
0567 
0568     if (hcd->is_isp1763)
0569         hcd->memory_layout = &isp1763_memory_conf;
0570     else
0571         hcd->memory_layout = &isp176x_memory_conf;
0572 
0573     ret = isp1760_init_core(isp);
0574     if (ret < 0)
0575         return ret;
0576 
0577     if (IS_ENABLED(CONFIG_USB_ISP1760_HCD) && !usb_disabled()) {
0578         ret = isp1760_hcd_register(hcd, mem, irq,
0579                        irqflags | IRQF_SHARED, dev);
0580         if (ret < 0)
0581             return ret;
0582     }
0583 
0584     if (udc_enabled && IS_ENABLED(CONFIG_USB_ISP1761_UDC)) {
0585         ret = isp1760_udc_register(isp, irq, irqflags);
0586         if (ret < 0) {
0587             isp1760_hcd_unregister(hcd);
0588             return ret;
0589         }
0590     }
0591 
0592     dev_set_drvdata(dev, isp);
0593 
0594     return 0;
0595 }
0596 
0597 void isp1760_unregister(struct device *dev)
0598 {
0599     struct isp1760_device *isp = dev_get_drvdata(dev);
0600 
0601     isp1760_udc_unregister(isp);
0602     isp1760_hcd_unregister(&isp->hcd);
0603 }
0604 
0605 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
0606 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
0607 MODULE_LICENSE("GPL v2");
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