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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * xHCI host controller driver PCI Bus Glue.
0004  *
0005  * Copyright (C) 2008 Intel Corp.
0006  *
0007  * Author: Sarah Sharp
0008  * Some code borrowed from the Linux EHCI driver.
0009  */
0010 
0011 #include <linux/pci.h>
0012 #include <linux/slab.h>
0013 #include <linux/module.h>
0014 #include <linux/acpi.h>
0015 #include <linux/reset.h>
0016 
0017 #include "xhci.h"
0018 #include "xhci-trace.h"
0019 #include "xhci-pci.h"
0020 
0021 #define SSIC_PORT_NUM       2
0022 #define SSIC_PORT_CFG2      0x880c
0023 #define SSIC_PORT_CFG2_OFFSET   0x30
0024 #define PROG_DONE       (1 << 30)
0025 #define SSIC_PORT_UNUSED    (1 << 31)
0026 #define SPARSE_DISABLE_BIT  17
0027 #define SPARSE_CNTL_ENABLE  0xC12C
0028 
0029 /* Device for a quirk */
0030 #define PCI_VENDOR_ID_FRESCO_LOGIC  0x1b73
0031 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
0032 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009   0x1009
0033 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100   0x1100
0034 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400   0x1400
0035 
0036 #define PCI_VENDOR_ID_ETRON     0x1b6f
0037 #define PCI_DEVICE_ID_EJ168     0x7023
0038 
0039 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI  0x8c31
0040 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
0041 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI    0x9cb1
0042 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI     0x22b5
0043 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI     0xa12f
0044 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI    0x9d2f
0045 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI      0x0aa8
0046 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI      0x1aa8
0047 #define PCI_DEVICE_ID_INTEL_APL_XHCI            0x5aa8
0048 #define PCI_DEVICE_ID_INTEL_DNV_XHCI            0x19d0
0049 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI    0x15b5
0050 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI    0x15b6
0051 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI    0x15c1
0052 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI  0x15db
0053 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI  0x15d4
0054 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI     0x15e9
0055 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI     0x15ec
0056 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI     0x15f0
0057 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI       0x8a13
0058 #define PCI_DEVICE_ID_INTEL_CML_XHCI            0xa3af
0059 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI     0x9a13
0060 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI        0x1138
0061 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI     0x461e
0062 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI       0x464e
0063 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
0064 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI        0xa71e
0065 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI        0x7ec0
0066 
0067 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI           0x1639
0068 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4         0x43b9
0069 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3         0x43ba
0070 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2         0x43bb
0071 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1         0x43bc
0072 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1        0x161a
0073 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2        0x161b
0074 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3        0x161d
0075 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4        0x161e
0076 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5        0x15d6
0077 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6        0x15d7
0078 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7        0x161c
0079 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8        0x161f
0080 
0081 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI         0x1042
0082 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI        0x1142
0083 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI         0x1242
0084 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI         0x2142
0085 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI         0x3242
0086 
0087 static const char hcd_name[] = "xhci_hcd";
0088 
0089 static struct hc_driver __read_mostly xhci_pci_hc_driver;
0090 
0091 static int xhci_pci_setup(struct usb_hcd *hcd);
0092 
0093 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
0094     .reset = xhci_pci_setup,
0095 };
0096 
0097 /* called after powerup, by probe or system-pm "wakeup" */
0098 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
0099 {
0100     /*
0101      * TODO: Implement finding debug ports later.
0102      * TODO: see if there are any quirks that need to be added to handle
0103      * new extended capabilities.
0104      */
0105 
0106     /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
0107     if (!pci_set_mwi(pdev))
0108         xhci_dbg(xhci, "MWI active\n");
0109 
0110     xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
0111     return 0;
0112 }
0113 
0114 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
0115 {
0116     struct pci_dev                  *pdev = to_pci_dev(dev);
0117     struct xhci_driver_data         *driver_data;
0118     const struct pci_device_id      *id;
0119 
0120     id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
0121 
0122     if (id && id->driver_data) {
0123         driver_data = (struct xhci_driver_data *)id->driver_data;
0124         xhci->quirks |= driver_data->quirks;
0125     }
0126 
0127     /* Look for vendor-specific quirks */
0128     if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
0129             (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
0130              pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
0131         if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
0132                 pdev->revision == 0x0) {
0133             xhci->quirks |= XHCI_RESET_EP_QUIRK;
0134             xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
0135                 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated");
0136         }
0137         if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
0138                 pdev->revision == 0x4) {
0139             xhci->quirks |= XHCI_SLOW_SUSPEND;
0140             xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
0141                 "QUIRK: Fresco Logic xHC revision %u"
0142                 "must be suspended extra slowly",
0143                 pdev->revision);
0144         }
0145         if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
0146             xhci->quirks |= XHCI_BROKEN_STREAMS;
0147         /* Fresco Logic confirms: all revisions of this chip do not
0148          * support MSI, even though some of them claim to in their PCI
0149          * capabilities.
0150          */
0151         xhci->quirks |= XHCI_BROKEN_MSI;
0152         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
0153                 "QUIRK: Fresco Logic revision %u "
0154                 "has broken MSI implementation",
0155                 pdev->revision);
0156         xhci->quirks |= XHCI_TRUST_TX_LENGTH;
0157     }
0158 
0159     if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
0160             pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
0161         xhci->quirks |= XHCI_BROKEN_STREAMS;
0162 
0163     if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
0164             pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
0165         xhci->quirks |= XHCI_TRUST_TX_LENGTH;
0166 
0167     if (pdev->vendor == PCI_VENDOR_ID_NEC)
0168         xhci->quirks |= XHCI_NEC_HOST;
0169 
0170     if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
0171         xhci->quirks |= XHCI_AMD_0x96_HOST;
0172 
0173     /* AMD PLL quirk */
0174     if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
0175         xhci->quirks |= XHCI_AMD_PLL_FIX;
0176 
0177     if (pdev->vendor == PCI_VENDOR_ID_AMD &&
0178         (pdev->device == 0x145c ||
0179          pdev->device == 0x15e0 ||
0180          pdev->device == 0x15e1 ||
0181          pdev->device == 0x43bb))
0182         xhci->quirks |= XHCI_SUSPEND_DELAY;
0183 
0184     if (pdev->vendor == PCI_VENDOR_ID_AMD &&
0185         (pdev->device == 0x15e0 || pdev->device == 0x15e1))
0186         xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
0187 
0188     if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
0189         xhci->quirks |= XHCI_DISABLE_SPARSE;
0190         xhci->quirks |= XHCI_RESET_ON_RESUME;
0191     }
0192 
0193     if (pdev->vendor == PCI_VENDOR_ID_AMD)
0194         xhci->quirks |= XHCI_TRUST_TX_LENGTH;
0195 
0196     if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
0197         ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
0198         (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
0199         (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
0200         (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
0201         xhci->quirks |= XHCI_U2_DISABLE_WAKE;
0202 
0203     if (pdev->vendor == PCI_VENDOR_ID_AMD &&
0204         pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
0205         xhci->quirks |= XHCI_BROKEN_D3COLD;
0206 
0207     if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
0208         xhci->quirks |= XHCI_LPM_SUPPORT;
0209         xhci->quirks |= XHCI_INTEL_HOST;
0210         xhci->quirks |= XHCI_AVOID_BEI;
0211     }
0212     if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
0213             pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
0214         xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
0215         xhci->limit_active_eps = 64;
0216         xhci->quirks |= XHCI_SW_BW_CHECKING;
0217         /*
0218          * PPT desktop boards DH77EB and DH77DF will power back on after
0219          * a few seconds of being shutdown.  The fix for this is to
0220          * switch the ports from xHCI to EHCI on shutdown.  We can't use
0221          * DMI information to find those particular boards (since each
0222          * vendor will change the board name), so we have to key off all
0223          * PPT chipsets.
0224          */
0225         xhci->quirks |= XHCI_SPURIOUS_REBOOT;
0226     }
0227     if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
0228         (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
0229          pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
0230         xhci->quirks |= XHCI_SPURIOUS_REBOOT;
0231         xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
0232     }
0233     if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
0234         (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
0235          pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
0236          pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
0237          pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
0238          pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
0239          pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
0240          pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
0241          pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
0242         xhci->quirks |= XHCI_PME_STUCK_QUIRK;
0243     }
0244     if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
0245         pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
0246         xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
0247     if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
0248         (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
0249          pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
0250          pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
0251         xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
0252     if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
0253         (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
0254          pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
0255          pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
0256          pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
0257          pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
0258         xhci->quirks |= XHCI_MISSING_CAS;
0259 
0260     if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
0261         (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
0262          pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
0263          pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
0264          pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
0265          pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
0266          pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
0267          pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
0268          pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
0269          pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
0270          pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
0271          pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
0272          pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI ||
0273          pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI ||
0274          pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
0275          pdev->device == PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI ||
0276          pdev->device == PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI))
0277         xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
0278 
0279     if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
0280             pdev->device == PCI_DEVICE_ID_EJ168) {
0281         xhci->quirks |= XHCI_RESET_ON_RESUME;
0282         xhci->quirks |= XHCI_TRUST_TX_LENGTH;
0283         xhci->quirks |= XHCI_BROKEN_STREAMS;
0284     }
0285     if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
0286         pdev->device == 0x0014) {
0287         xhci->quirks |= XHCI_TRUST_TX_LENGTH;
0288         xhci->quirks |= XHCI_ZERO_64B_REGS;
0289     }
0290     if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
0291         pdev->device == 0x0015) {
0292         xhci->quirks |= XHCI_RESET_ON_RESUME;
0293         xhci->quirks |= XHCI_ZERO_64B_REGS;
0294     }
0295     if (pdev->vendor == PCI_VENDOR_ID_VIA)
0296         xhci->quirks |= XHCI_RESET_ON_RESUME;
0297 
0298     /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
0299     if (pdev->vendor == PCI_VENDOR_ID_VIA &&
0300             pdev->device == 0x3432)
0301         xhci->quirks |= XHCI_BROKEN_STREAMS;
0302 
0303     if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
0304         xhci->quirks |= XHCI_LPM_SUPPORT;
0305         xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
0306     }
0307 
0308     if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
0309         pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
0310         xhci->quirks |= XHCI_BROKEN_STREAMS;
0311     if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
0312         pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
0313         xhci->quirks |= XHCI_TRUST_TX_LENGTH;
0314         xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
0315     }
0316     if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
0317         (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
0318          pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
0319          pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
0320         xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
0321 
0322     if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
0323         pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
0324         xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
0325 
0326     if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
0327         xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
0328 
0329     if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
0330          pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
0331          pdev->device == 0x9026)
0332         xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
0333 
0334     if (pdev->vendor == PCI_VENDOR_ID_AMD &&
0335         (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
0336          pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
0337         xhci->quirks |= XHCI_NO_SOFT_RETRY;
0338 
0339     if (pdev->vendor == PCI_VENDOR_ID_AMD &&
0340         (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 ||
0341         pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 ||
0342         pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 ||
0343         pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 ||
0344         pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 ||
0345         pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 ||
0346         pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 ||
0347         pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8))
0348         xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
0349 
0350     if (xhci->quirks & XHCI_RESET_ON_RESUME)
0351         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
0352                 "QUIRK: Resetting on resume");
0353 }
0354 
0355 #ifdef CONFIG_ACPI
0356 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
0357 {
0358     static const guid_t intel_dsm_guid =
0359         GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
0360               0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
0361     union acpi_object *obj;
0362 
0363     obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
0364                 NULL);
0365     ACPI_FREE(obj);
0366 }
0367 #else
0368 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
0369 #endif /* CONFIG_ACPI */
0370 
0371 /* called during probe() after chip reset completes */
0372 static int xhci_pci_setup(struct usb_hcd *hcd)
0373 {
0374     struct xhci_hcd     *xhci;
0375     struct pci_dev      *pdev = to_pci_dev(hcd->self.controller);
0376     int         retval;
0377 
0378     xhci = hcd_to_xhci(hcd);
0379     if (!xhci->sbrn)
0380         pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
0381 
0382     /* imod_interval is the interrupt moderation value in nanoseconds. */
0383     xhci->imod_interval = 40000;
0384 
0385     retval = xhci_gen_setup(hcd, xhci_pci_quirks);
0386     if (retval)
0387         return retval;
0388 
0389     if (!usb_hcd_is_primary_hcd(hcd))
0390         return 0;
0391 
0392     if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
0393         xhci_pme_acpi_rtd3_enable(pdev);
0394 
0395     xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
0396 
0397     /* Find any debug ports */
0398     return xhci_pci_reinit(xhci, pdev);
0399 }
0400 
0401 /*
0402  * We need to register our own PCI probe function (instead of the USB core's
0403  * function) in order to create a second roothub under xHCI.
0404  */
0405 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
0406 {
0407     int retval;
0408     struct xhci_hcd *xhci;
0409     struct usb_hcd *hcd;
0410     struct xhci_driver_data *driver_data;
0411     struct reset_control *reset;
0412 
0413     driver_data = (struct xhci_driver_data *)id->driver_data;
0414     if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
0415         retval = renesas_xhci_check_request_fw(dev, id);
0416         if (retval)
0417             return retval;
0418     }
0419 
0420     reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
0421     if (IS_ERR(reset))
0422         return PTR_ERR(reset);
0423     reset_control_reset(reset);
0424 
0425     /* Prevent runtime suspending between USB-2 and USB-3 initialization */
0426     pm_runtime_get_noresume(&dev->dev);
0427 
0428     /* Register the USB 2.0 roothub.
0429      * FIXME: USB core must know to register the USB 2.0 roothub first.
0430      * This is sort of silly, because we could just set the HCD driver flags
0431      * to say USB 2.0, but I'm not sure what the implications would be in
0432      * the other parts of the HCD code.
0433      */
0434     retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
0435 
0436     if (retval)
0437         goto put_runtime_pm;
0438 
0439     /* USB 2.0 roothub is stored in the PCI device now. */
0440     hcd = dev_get_drvdata(&dev->dev);
0441     xhci = hcd_to_xhci(hcd);
0442     xhci->reset = reset;
0443     xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
0444                          pci_name(dev), hcd);
0445     if (!xhci->shared_hcd) {
0446         retval = -ENOMEM;
0447         goto dealloc_usb2_hcd;
0448     }
0449 
0450     retval = xhci_ext_cap_init(xhci);
0451     if (retval)
0452         goto put_usb3_hcd;
0453 
0454     retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
0455             IRQF_SHARED);
0456     if (retval)
0457         goto put_usb3_hcd;
0458     /* Roothub already marked as USB 3.0 speed */
0459 
0460     if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
0461             HCC_MAX_PSA(xhci->hcc_params) >= 4)
0462         xhci->shared_hcd->can_do_streams = 1;
0463 
0464     /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
0465     pm_runtime_put_noidle(&dev->dev);
0466 
0467     if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
0468         pm_runtime_allow(&dev->dev);
0469 
0470     return 0;
0471 
0472 put_usb3_hcd:
0473     usb_put_hcd(xhci->shared_hcd);
0474 dealloc_usb2_hcd:
0475     usb_hcd_pci_remove(dev);
0476 put_runtime_pm:
0477     pm_runtime_put_noidle(&dev->dev);
0478     return retval;
0479 }
0480 
0481 static void xhci_pci_remove(struct pci_dev *dev)
0482 {
0483     struct xhci_hcd *xhci;
0484 
0485     xhci = hcd_to_xhci(pci_get_drvdata(dev));
0486 
0487     xhci->xhc_state |= XHCI_STATE_REMOVING;
0488 
0489     if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
0490         pm_runtime_forbid(&dev->dev);
0491 
0492     if (xhci->shared_hcd) {
0493         usb_remove_hcd(xhci->shared_hcd);
0494         usb_put_hcd(xhci->shared_hcd);
0495         xhci->shared_hcd = NULL;
0496     }
0497 
0498     /* Workaround for spurious wakeups at shutdown with HSW */
0499     if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
0500         pci_set_power_state(dev, PCI_D3hot);
0501 
0502     usb_hcd_pci_remove(dev);
0503 }
0504 
0505 #ifdef CONFIG_PM
0506 /*
0507  * In some Intel xHCI controllers, in order to get D3 working,
0508  * through a vendor specific SSIC CONFIG register at offset 0x883c,
0509  * SSIC PORT need to be marked as "unused" before putting xHCI
0510  * into D3. After D3 exit, the SSIC port need to be marked as "used".
0511  * Without this change, xHCI might not enter D3 state.
0512  */
0513 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
0514 {
0515     struct xhci_hcd *xhci = hcd_to_xhci(hcd);
0516     u32 val;
0517     void __iomem *reg;
0518     int i;
0519 
0520     for (i = 0; i < SSIC_PORT_NUM; i++) {
0521         reg = (void __iomem *) xhci->cap_regs +
0522                 SSIC_PORT_CFG2 +
0523                 i * SSIC_PORT_CFG2_OFFSET;
0524 
0525         /* Notify SSIC that SSIC profile programming is not done. */
0526         val = readl(reg) & ~PROG_DONE;
0527         writel(val, reg);
0528 
0529         /* Mark SSIC port as unused(suspend) or used(resume) */
0530         val = readl(reg);
0531         if (suspend)
0532             val |= SSIC_PORT_UNUSED;
0533         else
0534             val &= ~SSIC_PORT_UNUSED;
0535         writel(val, reg);
0536 
0537         /* Notify SSIC that SSIC profile programming is done */
0538         val = readl(reg) | PROG_DONE;
0539         writel(val, reg);
0540         readl(reg);
0541     }
0542 }
0543 
0544 /*
0545  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
0546  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
0547  */
0548 static void xhci_pme_quirk(struct usb_hcd *hcd)
0549 {
0550     struct xhci_hcd *xhci = hcd_to_xhci(hcd);
0551     void __iomem *reg;
0552     u32 val;
0553 
0554     reg = (void __iomem *) xhci->cap_regs + 0x80a4;
0555     val = readl(reg);
0556     writel(val | BIT(28), reg);
0557     readl(reg);
0558 }
0559 
0560 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
0561 {
0562     u32 reg;
0563 
0564     reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
0565     reg &= ~BIT(SPARSE_DISABLE_BIT);
0566     writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
0567 }
0568 
0569 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
0570 {
0571     struct xhci_hcd *xhci = hcd_to_xhci(hcd);
0572     struct pci_dev      *pdev = to_pci_dev(hcd->self.controller);
0573     int         ret;
0574 
0575     /*
0576      * Systems with the TI redriver that loses port status change events
0577      * need to have the registers polled during D3, so avoid D3cold.
0578      */
0579     if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
0580         pci_d3cold_disable(pdev);
0581 
0582     if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
0583         xhci_pme_quirk(hcd);
0584 
0585     if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
0586         xhci_ssic_port_unused_quirk(hcd, true);
0587 
0588     if (xhci->quirks & XHCI_DISABLE_SPARSE)
0589         xhci_sparse_control_quirk(hcd);
0590 
0591     ret = xhci_suspend(xhci, do_wakeup);
0592     if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
0593         xhci_ssic_port_unused_quirk(hcd, false);
0594 
0595     return ret;
0596 }
0597 
0598 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
0599 {
0600     struct xhci_hcd     *xhci = hcd_to_xhci(hcd);
0601     struct pci_dev      *pdev = to_pci_dev(hcd->self.controller);
0602     int         retval = 0;
0603 
0604     reset_control_reset(xhci->reset);
0605 
0606     /* The BIOS on systems with the Intel Panther Point chipset may or may
0607      * not support xHCI natively.  That means that during system resume, it
0608      * may switch the ports back to EHCI so that users can use their
0609      * keyboard to select a kernel from GRUB after resume from hibernate.
0610      *
0611      * The BIOS is supposed to remember whether the OS had xHCI ports
0612      * enabled before resume, and switch the ports back to xHCI when the
0613      * BIOS/OS semaphore is written, but we all know we can't trust BIOS
0614      * writers.
0615      *
0616      * Unconditionally switch the ports back to xHCI after a system resume.
0617      * It should not matter whether the EHCI or xHCI controller is
0618      * resumed first. It's enough to do the switchover in xHCI because
0619      * USB core won't notice anything as the hub driver doesn't start
0620      * running again until after all the devices (including both EHCI and
0621      * xHCI host controllers) have been resumed.
0622      */
0623 
0624     if (pdev->vendor == PCI_VENDOR_ID_INTEL)
0625         usb_enable_intel_xhci_ports(pdev);
0626 
0627     if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
0628         xhci_ssic_port_unused_quirk(hcd, false);
0629 
0630     if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
0631         xhci_pme_quirk(hcd);
0632 
0633     retval = xhci_resume(xhci, hibernated);
0634     return retval;
0635 }
0636 
0637 static void xhci_pci_shutdown(struct usb_hcd *hcd)
0638 {
0639     struct xhci_hcd     *xhci = hcd_to_xhci(hcd);
0640     struct pci_dev      *pdev = to_pci_dev(hcd->self.controller);
0641 
0642     xhci_shutdown(hcd);
0643 
0644     /* Yet another workaround for spurious wakeups at shutdown with HSW */
0645     if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
0646         pci_set_power_state(pdev, PCI_D3hot);
0647 }
0648 #endif /* CONFIG_PM */
0649 
0650 /*-------------------------------------------------------------------------*/
0651 
0652 static const struct xhci_driver_data reneses_data = {
0653     .quirks  = XHCI_RENESAS_FW_QUIRK,
0654     .firmware = "renesas_usb_fw.mem",
0655 };
0656 
0657 /* PCI driver selection metadata; PCI hotplugging uses this */
0658 static const struct pci_device_id pci_ids[] = {
0659     { PCI_DEVICE(0x1912, 0x0014),
0660         .driver_data =  (unsigned long)&reneses_data,
0661     },
0662     { PCI_DEVICE(0x1912, 0x0015),
0663         .driver_data =  (unsigned long)&reneses_data,
0664     },
0665     /* handle any USB 3.0 xHCI controller */
0666     { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
0667     },
0668     { /* end: all zeroes */ }
0669 };
0670 MODULE_DEVICE_TABLE(pci, pci_ids);
0671 
0672 /*
0673  * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
0674  * load firmware, so don't encumber the xhci-pci driver with it.
0675  */
0676 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
0677 MODULE_FIRMWARE("renesas_usb_fw.mem");
0678 #endif
0679 
0680 /* pci driver glue; this is a "new style" PCI driver module */
0681 static struct pci_driver xhci_pci_driver = {
0682     .name =     hcd_name,
0683     .id_table = pci_ids,
0684 
0685     .probe =    xhci_pci_probe,
0686     .remove =   xhci_pci_remove,
0687     /* suspend and resume implemented later */
0688 
0689     .shutdown =     usb_hcd_pci_shutdown,
0690 #ifdef CONFIG_PM
0691     .driver = {
0692         .pm = &usb_hcd_pci_pm_ops
0693     },
0694 #endif
0695 };
0696 
0697 static int __init xhci_pci_init(void)
0698 {
0699     xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
0700 #ifdef CONFIG_PM
0701     xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
0702     xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
0703     xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
0704 #endif
0705     return pci_register_driver(&xhci_pci_driver);
0706 }
0707 module_init(xhci_pci_init);
0708 
0709 static void __exit xhci_pci_exit(void)
0710 {
0711     pci_unregister_driver(&xhci_pci_driver);
0712 }
0713 module_exit(xhci_pci_exit);
0714 
0715 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
0716 MODULE_LICENSE("GPL");
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