usb/host/xhci-mtk.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2015 MediaTek Inc.
0004  * Author:
0005  *  Zhigang.Wei <zhigang.wei@mediatek.com>
0006  *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
0007  */
0008
0009 #ifndef _XHCI_MTK_H_
0010 #define _XHCI_MTK_H_
0011
0012 #include <linux/clk.h>
0013 #include <linux/hashtable.h>
0014 #include <linux/regulator/consumer.h>
0015
0016 #include "xhci.h"
0017
0018 #define BULK_CLKS_NUM   5
0019 #define BULK_VREGS_NUM  2
0020
0021 /* support at most 64 ep, use 32 size hash table */
0022 #define SCH_EP_HASH_BITS    5
0023
0024 /**
0025  * To simplify scheduler algorithm, set a upper limit for ESIT,
0026  * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
0027  * round down to the limit value, that means allocating more
0028  * bandwidth to it.
0029  */
0030 #define XHCI_MTK_MAX_ESIT   (1 << 6)
0031 #define XHCI_MTK_BW_INDEX(x)    ((x) & (XHCI_MTK_MAX_ESIT - 1))
0032
0033 /**
0034  * @fs_bus_bw: array to keep track of bandwidth already used for FS
0035  * @ep_list: Endpoints using this TT
0036  */
0037 struct mu3h_sch_tt {
0038     u32 fs_bus_bw[XHCI_MTK_MAX_ESIT];
0039     struct list_head ep_list;
0040 };
0041
0042 /**
0043  * struct mu3h_sch_bw_info: schedule information for bandwidth domain
0044  *
0045  * @bus_bw: array to keep track of bandwidth already used at each uframes
0046  *
0047  * treat a HS root port as a bandwidth domain, but treat a SS root port as
0048  * two bandwidth domains, one for IN eps and another for OUT eps.
0049  */
0050 struct mu3h_sch_bw_info {
0051     u32 bus_bw[XHCI_MTK_MAX_ESIT];
0052 };
0053
0054 /**
0055  * struct mu3h_sch_ep_info: schedule information for endpoint
0056  *
0057  * @esit: unit is 125us, equal to 2 << Interval field in ep-context
0058  * @num_esit: number of @esit in a period
0059  * @num_budget_microframes: number of continuous uframes
0060  *      (@repeat==1) scheduled within the interval
0061  * @bw_cost_per_microframe: bandwidth cost per microframe
0062  * @hentry: hash table entry
0063  * @endpoint: linked into bandwidth domain which it belongs to
0064  * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
0065  * @bw_info: bandwidth domain which this endpoint belongs
0066  * @sch_tt: mu3h_sch_tt linked into
0067  * @ep_type: endpoint type
0068  * @maxpkt: max packet size of endpoint
0069  * @ep: address of usb_host_endpoint struct
0070  * @allocated: the bandwidth is aready allocated from bus_bw
0071  * @offset: which uframe of the interval that transfer should be
0072  *      scheduled first time within the interval
0073  * @repeat: the time gap between two uframes that transfers are
0074  *      scheduled within a interval. in the simple algorithm, only
0075  *      assign 0 or 1 to it; 0 means using only one uframe in a
0076  *      interval, and 1 means using @num_budget_microframes
0077  *      continuous uframes
0078  * @pkts: number of packets to be transferred in the scheduled uframes
0079  * @cs_count: number of CS that host will trigger
0080  * @burst_mode: burst mode for scheduling. 0: normal burst mode,
0081  *      distribute the bMaxBurst+1 packets for a single burst
0082  *      according to @pkts and @repeat, repeate the burst multiple
0083  *      times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
0084  *      according to @pkts and @repeat. normal mode is used by
0085  *      default
0086  */
0087 struct mu3h_sch_ep_info {
0088     u32 esit;
0089     u32 num_esit;
0090     u32 num_budget_microframes;
0091     u32 bw_cost_per_microframe;
0092     struct list_head endpoint;
0093     struct hlist_node hentry;
0094     struct list_head tt_endpoint;
0095     struct mu3h_sch_bw_info *bw_info;
0096     struct mu3h_sch_tt *sch_tt;
0097     u32 ep_type;
0098     u32 maxpkt;
0099     struct usb_host_endpoint *ep;
0100     enum usb_device_speed speed;
0101     bool allocated;
0102     /*
0103      * mtk xHCI scheduling information put into reserved DWs
0104      * in ep context
0105      */
0106     u32 offset;
0107     u32 repeat;
0108     u32 pkts;
0109     u32 cs_count;
0110     u32 burst_mode;
0111 };
0112
0113 #define MU3C_U3_PORT_MAX 4
0114 #define MU3C_U2_PORT_MAX 5
0115
0116 /**
0117  * struct mu3c_ippc_regs: MTK ssusb ip port control registers
0118  * @ip_pw_ctr0~3: ip power and clock control registers
0119  * @ip_pw_sts1~2: ip power and clock status registers
0120  * @ip_xhci_cap: ip xHCI capability register
0121  * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
0122  * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
0123  * @u2_phy_pll: usb2 phy pll control register
0124  */
0125 struct mu3c_ippc_regs {
0126     __le32 ip_pw_ctr0;
0127     __le32 ip_pw_ctr1;
0128     __le32 ip_pw_ctr2;
0129     __le32 ip_pw_ctr3;
0130     __le32 ip_pw_sts1;
0131     __le32 ip_pw_sts2;
0132     __le32 reserved0[3];
0133     __le32 ip_xhci_cap;
0134     __le32 reserved1[2];
0135     __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
0136     __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
0137     __le32 reserved2;
0138     __le32 u2_phy_pll;
0139     __le32 reserved3[33]; /* 0x80 ~ 0xff */
0140 };
0141
0142 struct xhci_hcd_mtk {
0143     struct device *dev;
0144     struct usb_hcd *hcd;
0145     struct mu3h_sch_bw_info *sch_array;
0146     struct list_head bw_ep_chk_list;
0147     DECLARE_HASHTABLE(sch_ep_hash, SCH_EP_HASH_BITS);
0148     struct mu3c_ippc_regs __iomem *ippc_regs;
0149     int num_u2_ports;
0150     int num_u3_ports;
0151     int u2p_dis_msk;
0152     int u3p_dis_msk;
0153     struct clk_bulk_data clks[BULK_CLKS_NUM];
0154     struct regulator_bulk_data supplies[BULK_VREGS_NUM];
0155     unsigned int has_ippc:1;
0156     unsigned int lpm_support:1;
0157     unsigned int u2_lpm_disable:1;
0158     /* usb remote wakeup */
0159     unsigned int uwk_en:1;
0160     struct regmap *uwk;
0161     u32 uwk_reg_base;
0162     u32 uwk_vers;
0163 };
0164
0165 static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
0166 {
0167     return dev_get_drvdata(hcd->self.controller);
0168 }
0169
0170 int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
0171 void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
0172 int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev,
0173             struct usb_host_endpoint *ep);
0174 int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev,
0175              struct usb_host_endpoint *ep);
0176 int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
0177 void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
0178
0179 #endif      /* _XHCI_MTK_H_ */