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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * MediaTek xHCI Host Controller Driver
0004  *
0005  * Copyright (c) 2015 MediaTek Inc.
0006  * Author:
0007  *  Chunfeng Yun <chunfeng.yun@mediatek.com>
0008  */
0009 
0010 #include <linux/dma-mapping.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/kernel.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/pm_wakeirq.h>
0019 #include <linux/regmap.h>
0020 #include <linux/regulator/consumer.h>
0021 #include <linux/reset.h>
0022 
0023 #include "xhci.h"
0024 #include "xhci-mtk.h"
0025 
0026 /* ip_pw_ctrl0 register */
0027 #define CTRL0_IP_SW_RST BIT(0)
0028 
0029 /* ip_pw_ctrl1 register */
0030 #define CTRL1_IP_HOST_PDN   BIT(0)
0031 
0032 /* ip_pw_ctrl2 register */
0033 #define CTRL2_IP_DEV_PDN    BIT(0)
0034 
0035 /* ip_pw_sts1 register */
0036 #define STS1_IP_SLEEP_STS   BIT(30)
0037 #define STS1_U3_MAC_RST BIT(16)
0038 #define STS1_XHCI_RST       BIT(11)
0039 #define STS1_SYS125_RST BIT(10)
0040 #define STS1_REF_RST        BIT(8)
0041 #define STS1_SYSPLL_STABLE  BIT(0)
0042 
0043 /* ip_xhci_cap register */
0044 #define CAP_U3_PORT_NUM(p)  ((p) & 0xff)
0045 #define CAP_U2_PORT_NUM(p)  (((p) >> 8) & 0xff)
0046 
0047 /* u3_ctrl_p register */
0048 #define CTRL_U3_PORT_HOST_SEL   BIT(2)
0049 #define CTRL_U3_PORT_PDN    BIT(1)
0050 #define CTRL_U3_PORT_DIS    BIT(0)
0051 
0052 /* u2_ctrl_p register */
0053 #define CTRL_U2_PORT_HOST_SEL   BIT(2)
0054 #define CTRL_U2_PORT_PDN    BIT(1)
0055 #define CTRL_U2_PORT_DIS    BIT(0)
0056 
0057 /* u2_phy_pll register */
0058 #define CTRL_U2_FORCE_PLL_STB   BIT(28)
0059 
0060 /* xHCI CSR */
0061 #define LS_EOF_CFG      0x930
0062 #define LSEOF_OFFSET        0x89
0063 
0064 #define FS_EOF_CFG      0x934
0065 #define FSEOF_OFFSET        0x2e
0066 
0067 #define SS_GEN1_EOF_CFG     0x93c
0068 #define SSG1EOF_OFFSET      0x78
0069 
0070 #define HFCNTR_CFG      0x944
0071 #define ITP_DELTA_CLK       (0xa << 1)
0072 #define ITP_DELTA_CLK_MASK  GENMASK(5, 1)
0073 #define FRMCNT_LEV1_RANG    (0x12b << 8)
0074 #define FRMCNT_LEV1_RANG_MASK   GENMASK(19, 8)
0075 
0076 #define SS_GEN2_EOF_CFG     0x990
0077 #define SSG2EOF_OFFSET      0x3c
0078 
0079 #define XSEOF_OFFSET_MASK   GENMASK(11, 0)
0080 
0081 /* usb remote wakeup registers in syscon */
0082 
0083 /* mt8173 etc */
0084 #define PERI_WK_CTRL1   0x4
0085 #define WC1_IS_C(x) (((x) & 0xf) << 26)  /* cycle debounce */
0086 #define WC1_IS_EN   BIT(25)
0087 #define WC1_IS_P    BIT(6)  /* polarity for ip sleep */
0088 
0089 /* mt8183 */
0090 #define PERI_WK_CTRL0   0x0
0091 #define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28))  /* cycle debounce */
0092 #define WC0_IS_P    BIT(12) /* polarity */
0093 #define WC0_IS_EN   BIT(6)
0094 
0095 /* mt8192 */
0096 #define WC0_SSUSB0_CDEN     BIT(6)
0097 #define WC0_IS_SPM_EN       BIT(1)
0098 
0099 /* mt8195 */
0100 #define PERI_WK_CTRL0_8195  0x04
0101 #define WC0_IS_P_95     BIT(30) /* polarity */
0102 #define WC0_IS_C_95(x)      ((u32)(((x) & 0x7) << 27))
0103 #define WC0_IS_EN_P3_95     BIT(26)
0104 #define WC0_IS_EN_P2_95     BIT(25)
0105 #define WC0_IS_EN_P1_95     BIT(24)
0106 
0107 #define PERI_WK_CTRL1_8195  0x20
0108 #define WC1_IS_C_95(x)      ((u32)(((x) & 0xf) << 28))
0109 #define WC1_IS_P_95     BIT(12)
0110 #define WC1_IS_EN_P0_95     BIT(6)
0111 
0112 /* mt2712 etc */
0113 #define PERI_SSUSB_SPM_CTRL 0x0
0114 #define SSC_IP_SLEEP_EN BIT(4)
0115 #define SSC_SPM_INT_EN      BIT(1)
0116 
0117 enum ssusb_uwk_vers {
0118     SSUSB_UWK_V1 = 1,
0119     SSUSB_UWK_V2,
0120     SSUSB_UWK_V1_1 = 101,   /* specific revision 1.01 */
0121     SSUSB_UWK_V1_2,     /* specific revision 1.2 */
0122     SSUSB_UWK_V1_3,     /* mt8195 IP0 */
0123     SSUSB_UWK_V1_4,     /* mt8195 IP1 */
0124     SSUSB_UWK_V1_5,     /* mt8195 IP2 */
0125     SSUSB_UWK_V1_6,     /* mt8195 IP3 */
0126 };
0127 
0128 /*
0129  * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
0130  * is calculated from the frame counter clock 24M, but in fact, the clock
0131  * is 48M, add workaround for it.
0132  */
0133 static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
0134 {
0135     struct device *dev = mtk->dev;
0136     struct usb_hcd *hcd = mtk->hcd;
0137     u32 value;
0138 
0139     if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
0140         return;
0141 
0142     value = readl(hcd->regs + HFCNTR_CFG);
0143     value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
0144     value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
0145     writel(value, hcd->regs + HFCNTR_CFG);
0146 
0147     value = readl(hcd->regs + LS_EOF_CFG);
0148     value &= ~XSEOF_OFFSET_MASK;
0149     value |= LSEOF_OFFSET;
0150     writel(value, hcd->regs + LS_EOF_CFG);
0151 
0152     value = readl(hcd->regs + FS_EOF_CFG);
0153     value &= ~XSEOF_OFFSET_MASK;
0154     value |= FSEOF_OFFSET;
0155     writel(value, hcd->regs + FS_EOF_CFG);
0156 
0157     value = readl(hcd->regs + SS_GEN1_EOF_CFG);
0158     value &= ~XSEOF_OFFSET_MASK;
0159     value |= SSG1EOF_OFFSET;
0160     writel(value, hcd->regs + SS_GEN1_EOF_CFG);
0161 
0162     value = readl(hcd->regs + SS_GEN2_EOF_CFG);
0163     value &= ~XSEOF_OFFSET_MASK;
0164     value |= SSG2EOF_OFFSET;
0165     writel(value, hcd->regs + SS_GEN2_EOF_CFG);
0166 }
0167 
0168 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
0169 {
0170     struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
0171     u32 value, check_val;
0172     int u3_ports_disabled = 0;
0173     int ret;
0174     int i;
0175 
0176     if (!mtk->has_ippc)
0177         return 0;
0178 
0179     /* power on host ip */
0180     value = readl(&ippc->ip_pw_ctr1);
0181     value &= ~CTRL1_IP_HOST_PDN;
0182     writel(value, &ippc->ip_pw_ctr1);
0183 
0184     /* power on and enable u3 ports except skipped ones */
0185     for (i = 0; i < mtk->num_u3_ports; i++) {
0186         if ((0x1 << i) & mtk->u3p_dis_msk) {
0187             u3_ports_disabled++;
0188             continue;
0189         }
0190 
0191         value = readl(&ippc->u3_ctrl_p[i]);
0192         value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
0193         value |= CTRL_U3_PORT_HOST_SEL;
0194         writel(value, &ippc->u3_ctrl_p[i]);
0195     }
0196 
0197     /* power on and enable all u2 ports except skipped ones */
0198     for (i = 0; i < mtk->num_u2_ports; i++) {
0199         if (BIT(i) & mtk->u2p_dis_msk)
0200             continue;
0201 
0202         value = readl(&ippc->u2_ctrl_p[i]);
0203         value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
0204         value |= CTRL_U2_PORT_HOST_SEL;
0205         writel(value, &ippc->u2_ctrl_p[i]);
0206     }
0207 
0208     /*
0209      * wait for clocks to be stable, and clock domains reset to
0210      * be inactive after power on and enable ports
0211      */
0212     check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
0213             STS1_SYS125_RST | STS1_XHCI_RST;
0214 
0215     if (mtk->num_u3_ports > u3_ports_disabled)
0216         check_val |= STS1_U3_MAC_RST;
0217 
0218     ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
0219               (check_val == (value & check_val)), 100, 20000);
0220     if (ret) {
0221         dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
0222         return ret;
0223     }
0224 
0225     return 0;
0226 }
0227 
0228 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
0229 {
0230     struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
0231     u32 value;
0232     int ret;
0233     int i;
0234 
0235     if (!mtk->has_ippc)
0236         return 0;
0237 
0238     /* power down u3 ports except skipped ones */
0239     for (i = 0; i < mtk->num_u3_ports; i++) {
0240         if ((0x1 << i) & mtk->u3p_dis_msk)
0241             continue;
0242 
0243         value = readl(&ippc->u3_ctrl_p[i]);
0244         value |= CTRL_U3_PORT_PDN;
0245         writel(value, &ippc->u3_ctrl_p[i]);
0246     }
0247 
0248     /* power down all u2 ports except skipped ones */
0249     for (i = 0; i < mtk->num_u2_ports; i++) {
0250         if (BIT(i) & mtk->u2p_dis_msk)
0251             continue;
0252 
0253         value = readl(&ippc->u2_ctrl_p[i]);
0254         value |= CTRL_U2_PORT_PDN;
0255         writel(value, &ippc->u2_ctrl_p[i]);
0256     }
0257 
0258     /* power down host ip */
0259     value = readl(&ippc->ip_pw_ctr1);
0260     value |= CTRL1_IP_HOST_PDN;
0261     writel(value, &ippc->ip_pw_ctr1);
0262 
0263     /* wait for host ip to sleep */
0264     ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
0265               (value & STS1_IP_SLEEP_STS), 100, 100000);
0266     if (ret)
0267         dev_err(mtk->dev, "ip sleep failed!!!\n");
0268     else /* workaound for platforms using low level latch */
0269         usleep_range(100, 200);
0270 
0271     return ret;
0272 }
0273 
0274 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
0275 {
0276     struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
0277     u32 value;
0278 
0279     if (!mtk->has_ippc)
0280         return 0;
0281 
0282     /* reset whole ip */
0283     value = readl(&ippc->ip_pw_ctr0);
0284     value |= CTRL0_IP_SW_RST;
0285     writel(value, &ippc->ip_pw_ctr0);
0286     udelay(1);
0287     value = readl(&ippc->ip_pw_ctr0);
0288     value &= ~CTRL0_IP_SW_RST;
0289     writel(value, &ippc->ip_pw_ctr0);
0290 
0291     /*
0292      * device ip is default power-on in fact
0293      * power down device ip, otherwise ip-sleep will fail
0294      */
0295     value = readl(&ippc->ip_pw_ctr2);
0296     value |= CTRL2_IP_DEV_PDN;
0297     writel(value, &ippc->ip_pw_ctr2);
0298 
0299     value = readl(&ippc->ip_xhci_cap);
0300     mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
0301     mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
0302     dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
0303             mtk->num_u2_ports, mtk->num_u3_ports);
0304 
0305     return xhci_mtk_host_enable(mtk);
0306 }
0307 
0308 /* only clocks can be turn off for ip-sleep wakeup mode */
0309 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
0310 {
0311     u32 reg, msk, val;
0312 
0313     switch (mtk->uwk_vers) {
0314     case SSUSB_UWK_V1:
0315         reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
0316         msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
0317         val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
0318         break;
0319     case SSUSB_UWK_V1_1:
0320         reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
0321         msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
0322         val = enable ? (WC0_IS_EN | WC0_IS_C(0x1)) : 0;
0323         break;
0324     case SSUSB_UWK_V1_2:
0325         reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
0326         msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
0327         val = enable ? msk : 0;
0328         break;
0329     case SSUSB_UWK_V1_3:
0330         reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195;
0331         msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;
0332         val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0;
0333         break;
0334     case SSUSB_UWK_V1_4:
0335         reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
0336         msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
0337         val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0;
0338         break;
0339     case SSUSB_UWK_V1_5:
0340         reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
0341         msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
0342         val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0;
0343         break;
0344     case SSUSB_UWK_V1_6:
0345         reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
0346         msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
0347         val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0;
0348         break;
0349     case SSUSB_UWK_V2:
0350         reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
0351         msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
0352         val = enable ? msk : 0;
0353         break;
0354     default:
0355         return;
0356     }
0357     regmap_update_bits(mtk->uwk, reg, msk, val);
0358 }
0359 
0360 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
0361                 struct device_node *dn)
0362 {
0363     struct of_phandle_args args;
0364     int ret;
0365 
0366     /* Wakeup function is optional */
0367     mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
0368     if (!mtk->uwk_en)
0369         return 0;
0370 
0371     ret = of_parse_phandle_with_fixed_args(dn,
0372                 "mediatek,syscon-wakeup", 2, 0, &args);
0373     if (ret)
0374         return ret;
0375 
0376     mtk->uwk_reg_base = args.args[0];
0377     mtk->uwk_vers = args.args[1];
0378     mtk->uwk = syscon_node_to_regmap(args.np);
0379     of_node_put(args.np);
0380     dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
0381             mtk->uwk_reg_base, mtk->uwk_vers);
0382 
0383     return PTR_ERR_OR_ZERO(mtk->uwk);
0384 }
0385 
0386 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
0387 {
0388     if (mtk->uwk_en)
0389         usb_wakeup_ip_sleep_set(mtk, enable);
0390 }
0391 
0392 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
0393 {
0394     struct clk_bulk_data *clks = mtk->clks;
0395 
0396     clks[0].id = "sys_ck";
0397     clks[1].id = "xhci_ck";
0398     clks[2].id = "ref_ck";
0399     clks[3].id = "mcu_ck";
0400     clks[4].id = "dma_ck";
0401 
0402     return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks);
0403 }
0404 
0405 static int xhci_mtk_vregs_get(struct xhci_hcd_mtk *mtk)
0406 {
0407     struct regulator_bulk_data *supplies = mtk->supplies;
0408 
0409     supplies[0].supply = "vbus";
0410     supplies[1].supply = "vusb33";
0411 
0412     return devm_regulator_bulk_get(mtk->dev, BULK_VREGS_NUM, supplies);
0413 }
0414 
0415 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
0416 {
0417     struct usb_hcd *hcd = xhci_to_hcd(xhci);
0418     struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
0419 
0420     /*
0421      * As of now platform drivers don't provide MSI support so we ensure
0422      * here that the generic code does not try to make a pci_dev from our
0423      * dev struct in order to setup MSI
0424      */
0425     xhci->quirks |= XHCI_PLAT;
0426     xhci->quirks |= XHCI_MTK_HOST;
0427     /*
0428      * MTK host controller gives a spurious successful event after a
0429      * short transfer. Ignore it.
0430      */
0431     xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
0432     if (mtk->lpm_support)
0433         xhci->quirks |= XHCI_LPM_SUPPORT;
0434     if (mtk->u2_lpm_disable)
0435         xhci->quirks |= XHCI_HW_LPM_DISABLE;
0436 
0437     /*
0438      * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
0439      * and it's 3 when support it.
0440      */
0441     if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
0442         xhci->quirks |= XHCI_BROKEN_STREAMS;
0443 }
0444 
0445 /* called during probe() after chip reset completes */
0446 static int xhci_mtk_setup(struct usb_hcd *hcd)
0447 {
0448     struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
0449     int ret;
0450 
0451     if (usb_hcd_is_primary_hcd(hcd)) {
0452         ret = xhci_mtk_ssusb_config(mtk);
0453         if (ret)
0454             return ret;
0455 
0456         /* workaround only for mt8195 */
0457         xhci_mtk_set_frame_interval(mtk);
0458     }
0459 
0460     ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
0461     if (ret)
0462         return ret;
0463 
0464     if (usb_hcd_is_primary_hcd(hcd))
0465         ret = xhci_mtk_sch_init(mtk);
0466 
0467     return ret;
0468 }
0469 
0470 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
0471     .reset = xhci_mtk_setup,
0472     .add_endpoint = xhci_mtk_add_ep,
0473     .drop_endpoint = xhci_mtk_drop_ep,
0474     .check_bandwidth = xhci_mtk_check_bandwidth,
0475     .reset_bandwidth = xhci_mtk_reset_bandwidth,
0476 };
0477 
0478 static struct hc_driver __read_mostly xhci_mtk_hc_driver;
0479 
0480 static int xhci_mtk_probe(struct platform_device *pdev)
0481 {
0482     struct device *dev = &pdev->dev;
0483     struct device_node *node = dev->of_node;
0484     struct xhci_hcd_mtk *mtk;
0485     const struct hc_driver *driver;
0486     struct xhci_hcd *xhci;
0487     struct resource *res;
0488     struct usb_hcd *hcd;
0489     int ret = -ENODEV;
0490     int wakeup_irq;
0491     int irq;
0492 
0493     if (usb_disabled())
0494         return -ENODEV;
0495 
0496     driver = &xhci_mtk_hc_driver;
0497     mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
0498     if (!mtk)
0499         return -ENOMEM;
0500 
0501     mtk->dev = dev;
0502 
0503     ret = xhci_mtk_vregs_get(mtk);
0504     if (ret)
0505         return dev_err_probe(dev, ret, "Failed to get regulators\n");
0506 
0507     ret = xhci_mtk_clks_get(mtk);
0508     if (ret)
0509         return ret;
0510 
0511     irq = platform_get_irq_byname_optional(pdev, "host");
0512     if (irq < 0) {
0513         if (irq == -EPROBE_DEFER)
0514             return irq;
0515 
0516         /* for backward compatibility */
0517         irq = platform_get_irq(pdev, 0);
0518         if (irq < 0)
0519             return irq;
0520     }
0521 
0522     wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
0523     if (wakeup_irq == -EPROBE_DEFER)
0524         return wakeup_irq;
0525 
0526     mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
0527     mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable");
0528     /* optional property, ignore the error if it does not exist */
0529     of_property_read_u32(node, "mediatek,u3p-dis-msk",
0530                  &mtk->u3p_dis_msk);
0531     of_property_read_u32(node, "mediatek,u2p-dis-msk",
0532                  &mtk->u2p_dis_msk);
0533 
0534     ret = usb_wakeup_of_property_parse(mtk, node);
0535     if (ret) {
0536         dev_err(dev, "failed to parse uwk property\n");
0537         return ret;
0538     }
0539 
0540     pm_runtime_set_active(dev);
0541     pm_runtime_use_autosuspend(dev);
0542     pm_runtime_set_autosuspend_delay(dev, 4000);
0543     pm_runtime_enable(dev);
0544     pm_runtime_get_sync(dev);
0545 
0546     ret = regulator_bulk_enable(BULK_VREGS_NUM, mtk->supplies);
0547     if (ret)
0548         goto disable_pm;
0549 
0550     ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
0551     if (ret)
0552         goto disable_ldos;
0553 
0554     ret = device_reset_optional(dev);
0555     if (ret) {
0556         dev_err_probe(dev, ret, "failed to reset controller\n");
0557         goto disable_clk;
0558     }
0559 
0560     hcd = usb_create_hcd(driver, dev, dev_name(dev));
0561     if (!hcd) {
0562         ret = -ENOMEM;
0563         goto disable_clk;
0564     }
0565 
0566     /*
0567      * USB 2.0 roothub is stored in the platform_device.
0568      * Swap it with mtk HCD.
0569      */
0570     mtk->hcd = platform_get_drvdata(pdev);
0571     platform_set_drvdata(pdev, mtk);
0572 
0573     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
0574     hcd->regs = devm_ioremap_resource(dev, res);
0575     if (IS_ERR(hcd->regs)) {
0576         ret = PTR_ERR(hcd->regs);
0577         goto put_usb2_hcd;
0578     }
0579     hcd->rsrc_start = res->start;
0580     hcd->rsrc_len = resource_size(res);
0581 
0582     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
0583     if (res) {  /* ippc register is optional */
0584         mtk->ippc_regs = devm_ioremap_resource(dev, res);
0585         if (IS_ERR(mtk->ippc_regs)) {
0586             ret = PTR_ERR(mtk->ippc_regs);
0587             goto put_usb2_hcd;
0588         }
0589         mtk->has_ippc = true;
0590     }
0591 
0592     device_init_wakeup(dev, true);
0593 
0594     xhci = hcd_to_xhci(hcd);
0595     xhci->main_hcd = hcd;
0596 
0597     /*
0598      * imod_interval is the interrupt moderation value in nanoseconds.
0599      * The increment interval is 8 times as much as that defined in
0600      * the xHCI spec on MTK's controller.
0601      */
0602     xhci->imod_interval = 5000;
0603     device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
0604 
0605     xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
0606             dev_name(dev), hcd);
0607     if (!xhci->shared_hcd) {
0608         ret = -ENOMEM;
0609         goto disable_device_wakeup;
0610     }
0611 
0612     ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
0613     if (ret)
0614         goto put_usb3_hcd;
0615 
0616     if (HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
0617         !(xhci->quirks & XHCI_BROKEN_STREAMS))
0618         xhci->shared_hcd->can_do_streams = 1;
0619 
0620     ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
0621     if (ret)
0622         goto dealloc_usb2_hcd;
0623 
0624     if (wakeup_irq > 0) {
0625         ret = dev_pm_set_dedicated_wake_irq_reverse(dev, wakeup_irq);
0626         if (ret) {
0627             dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq);
0628             goto dealloc_usb3_hcd;
0629         }
0630         dev_info(dev, "wakeup irq %d\n", wakeup_irq);
0631     }
0632 
0633     device_enable_async_suspend(dev);
0634     pm_runtime_mark_last_busy(dev);
0635     pm_runtime_put_autosuspend(dev);
0636     pm_runtime_forbid(dev);
0637 
0638     return 0;
0639 
0640 dealloc_usb3_hcd:
0641     usb_remove_hcd(xhci->shared_hcd);
0642     xhci->shared_hcd = NULL;
0643 
0644 dealloc_usb2_hcd:
0645     usb_remove_hcd(hcd);
0646 
0647 put_usb3_hcd:
0648     xhci_mtk_sch_exit(mtk);
0649     usb_put_hcd(xhci->shared_hcd);
0650 
0651 disable_device_wakeup:
0652     device_init_wakeup(dev, false);
0653 
0654 put_usb2_hcd:
0655     usb_put_hcd(hcd);
0656 
0657 disable_clk:
0658     clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
0659 
0660 disable_ldos:
0661     regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies);
0662 
0663 disable_pm:
0664     pm_runtime_put_noidle(dev);
0665     pm_runtime_disable(dev);
0666     return ret;
0667 }
0668 
0669 static int xhci_mtk_remove(struct platform_device *pdev)
0670 {
0671     struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev);
0672     struct usb_hcd  *hcd = mtk->hcd;
0673     struct xhci_hcd *xhci = hcd_to_xhci(hcd);
0674     struct usb_hcd  *shared_hcd = xhci->shared_hcd;
0675     struct device *dev = &pdev->dev;
0676 
0677     pm_runtime_get_sync(dev);
0678     xhci->xhc_state |= XHCI_STATE_REMOVING;
0679     dev_pm_clear_wake_irq(dev);
0680     device_init_wakeup(dev, false);
0681 
0682     usb_remove_hcd(shared_hcd);
0683     xhci->shared_hcd = NULL;
0684     usb_remove_hcd(hcd);
0685     usb_put_hcd(shared_hcd);
0686     usb_put_hcd(hcd);
0687     xhci_mtk_sch_exit(mtk);
0688     clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
0689     regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies);
0690 
0691     pm_runtime_disable(dev);
0692     pm_runtime_put_noidle(dev);
0693     pm_runtime_set_suspended(dev);
0694 
0695     return 0;
0696 }
0697 
0698 static int __maybe_unused xhci_mtk_suspend(struct device *dev)
0699 {
0700     struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
0701     struct usb_hcd *hcd = mtk->hcd;
0702     struct xhci_hcd *xhci = hcd_to_xhci(hcd);
0703     int ret;
0704 
0705     xhci_dbg(xhci, "%s: stop port polling\n", __func__);
0706     clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
0707     del_timer_sync(&hcd->rh_timer);
0708     clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
0709     del_timer_sync(&xhci->shared_hcd->rh_timer);
0710 
0711     ret = xhci_mtk_host_disable(mtk);
0712     if (ret)
0713         goto restart_poll_rh;
0714 
0715     clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
0716     usb_wakeup_set(mtk, true);
0717     return 0;
0718 
0719 restart_poll_rh:
0720     xhci_dbg(xhci, "%s: restart port polling\n", __func__);
0721     set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
0722     usb_hcd_poll_rh_status(xhci->shared_hcd);
0723     set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
0724     usb_hcd_poll_rh_status(hcd);
0725     return ret;
0726 }
0727 
0728 static int __maybe_unused xhci_mtk_resume(struct device *dev)
0729 {
0730     struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
0731     struct usb_hcd *hcd = mtk->hcd;
0732     struct xhci_hcd *xhci = hcd_to_xhci(hcd);
0733     int ret;
0734 
0735     usb_wakeup_set(mtk, false);
0736     ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
0737     if (ret)
0738         goto enable_wakeup;
0739 
0740     ret = xhci_mtk_host_enable(mtk);
0741     if (ret)
0742         goto disable_clks;
0743 
0744     xhci_dbg(xhci, "%s: restart port polling\n", __func__);
0745     set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
0746     usb_hcd_poll_rh_status(xhci->shared_hcd);
0747     set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
0748     usb_hcd_poll_rh_status(hcd);
0749     return 0;
0750 
0751 disable_clks:
0752     clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
0753 enable_wakeup:
0754     usb_wakeup_set(mtk, true);
0755     return ret;
0756 }
0757 
0758 static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev)
0759 {
0760     struct xhci_hcd_mtk  *mtk = dev_get_drvdata(dev);
0761     struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
0762     int ret = 0;
0763 
0764     if (xhci->xhc_state)
0765         return -ESHUTDOWN;
0766 
0767     if (device_may_wakeup(dev))
0768         ret = xhci_mtk_suspend(dev);
0769 
0770     /* -EBUSY: let PM automatically reschedule another autosuspend */
0771     return ret ? -EBUSY : 0;
0772 }
0773 
0774 static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev)
0775 {
0776     struct xhci_hcd_mtk  *mtk = dev_get_drvdata(dev);
0777     struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
0778     int ret = 0;
0779 
0780     if (xhci->xhc_state)
0781         return -ESHUTDOWN;
0782 
0783     if (device_may_wakeup(dev))
0784         ret = xhci_mtk_resume(dev);
0785 
0786     return ret;
0787 }
0788 
0789 static const struct dev_pm_ops xhci_mtk_pm_ops = {
0790     SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
0791     SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend,
0792                xhci_mtk_runtime_resume, NULL)
0793 };
0794 
0795 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL)
0796 
0797 static const struct of_device_id mtk_xhci_of_match[] = {
0798     { .compatible = "mediatek,mt8173-xhci"},
0799     { .compatible = "mediatek,mt8195-xhci"},
0800     { .compatible = "mediatek,mtk-xhci"},
0801     { },
0802 };
0803 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
0804 
0805 static struct platform_driver mtk_xhci_driver = {
0806     .probe  = xhci_mtk_probe,
0807     .remove = xhci_mtk_remove,
0808     .driver = {
0809         .name = "xhci-mtk",
0810         .pm = DEV_PM_OPS,
0811         .of_match_table = mtk_xhci_of_match,
0812     },
0813 };
0814 
0815 static int __init xhci_mtk_init(void)
0816 {
0817     xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
0818     return platform_driver_register(&mtk_xhci_driver);
0819 }
0820 module_init(xhci_mtk_init);
0821 
0822 static void __exit xhci_mtk_exit(void)
0823 {
0824     platform_driver_unregister(&mtk_xhci_driver);
0825 }
0826 module_exit(xhci_mtk_exit);
0827 
0828 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
0829 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
0830 MODULE_LICENSE("GPL v2");
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