usb/host/r8a66597.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * R8A66597 HCD (Host Controller Driver)
0004  *
0005  * Copyright (C) 2006-2007 Renesas Solutions Corp.
0006  * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
0007  * Portions Copyright (C) 2004-2005 David Brownell
0008  * Portions Copyright (C) 1999 Roman Weissgaerber
0009  *
0010  * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
0011  */
0012
0013 #ifndef __R8A66597_H__
0014 #define __R8A66597_H__
0015
0016 #include <linux/clk.h>
0017 #include <linux/usb/r8a66597.h>
0018
0019 #define R8A66597_MAX_NUM_PIPE       10
0020 #define R8A66597_BUF_BSIZE      8
0021 #define R8A66597_MAX_DEVICE     10
0022 #define R8A66597_MAX_ROOT_HUB       2
0023 #define R8A66597_MAX_SAMPLING       5
0024 #define R8A66597_RH_POLL_TIME       10
0025 #define R8A66597_MAX_DMA_CHANNEL    2
0026 #define R8A66597_PIPE_NO_DMA        R8A66597_MAX_DMA_CHANNEL
0027 #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
0028 #define check_interrupt(pipenum)    ((pipenum >= 6 && pipenum <= 9))
0029 #define make_devsel(addr)       (addr << 12)
0030
0031 struct r8a66597_pipe_info {
0032     unsigned long timer_interval;
0033     u16 pipenum;
0034     u16 address;    /* R8A66597 HCD usb address */
0035     u16 epnum;
0036     u16 maxpacket;
0037     u16 type;
0038     u16 bufnum;
0039     u16 buf_bsize;
0040     u16 interval;
0041     u16 dir_in;
0042 };
0043
0044 struct r8a66597_pipe {
0045     struct r8a66597_pipe_info info;
0046
0047     unsigned long fifoaddr;
0048     unsigned long fifosel;
0049     unsigned long fifoctr;
0050     unsigned long pipectr;
0051     unsigned long pipetre;
0052     unsigned long pipetrn;
0053 };
0054
0055 struct r8a66597_td {
0056     struct r8a66597_pipe *pipe;
0057     struct urb *urb;
0058     struct list_head queue;
0059
0060     u16 type;
0061     u16 pipenum;
0062     int iso_cnt;
0063
0064     u16 address;        /* R8A66597's USB address */
0065     u16 maxpacket;
0066
0067     unsigned zero_packet:1;
0068     unsigned short_packet:1;
0069     unsigned set_address:1;
0070 };
0071
0072 struct r8a66597_device {
0073     u16 address;    /* R8A66597's USB address */
0074     u16 hub_port;
0075     u16 root_port;
0076
0077     unsigned short ep_in_toggle;
0078     unsigned short ep_out_toggle;
0079     unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
0080     unsigned char dma_map;
0081
0082     enum usb_device_state state;
0083
0084     struct usb_device *udev;
0085     int usb_address;
0086     struct list_head device_list;
0087 };
0088
0089 struct r8a66597_root_hub {
0090     u32 port;
0091     u16 old_syssts;
0092     int scount;
0093
0094     struct r8a66597_device  *dev;
0095 };
0096
0097 struct r8a66597;
0098
0099 struct r8a66597_timers {
0100     struct timer_list td;
0101     struct timer_list interval;
0102     struct r8a66597 *r8a66597;
0103 };
0104
0105 struct r8a66597 {
0106     spinlock_t lock;
0107     void __iomem *reg;
0108     struct clk *clk;
0109     struct r8a66597_platdata    *pdata;
0110     struct r8a66597_device      device0;
0111     struct r8a66597_root_hub    root_hub[R8A66597_MAX_ROOT_HUB];
0112     struct list_head        pipe_queue[R8A66597_MAX_NUM_PIPE];
0113
0114     struct timer_list rh_timer;
0115     struct r8a66597_timers timers[R8A66597_MAX_NUM_PIPE];
0116
0117     unsigned short address_map;
0118     unsigned short timeout_map;
0119     unsigned short interval_map;
0120     unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
0121     unsigned char dma_map;
0122     unsigned int max_root_hub;
0123
0124     struct list_head child_device;
0125     unsigned long child_connect_map[4];
0126
0127     unsigned bus_suspended:1;
0128     unsigned irq_sense_low:1;
0129 };
0130
0131 static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
0132 {
0133     return (struct r8a66597 *)(hcd->hcd_priv);
0134 }
0135
0136 static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
0137 {
0138     return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
0139 }
0140
0141 static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
0142                           u16 pipenum)
0143 {
0144     if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
0145         return NULL;
0146
0147     return list_entry(r8a66597->pipe_queue[pipenum].next,
0148               struct r8a66597_td, queue);
0149 }
0150
0151 static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
0152                        u16 pipenum)
0153 {
0154     struct r8a66597_td *td;
0155
0156     td = r8a66597_get_td(r8a66597, pipenum);
0157     return (td ? td->urb : NULL);
0158 }
0159
0160 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
0161 {
0162     return ioread16(r8a66597->reg + offset);
0163 }
0164
0165 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
0166                       unsigned long offset, u16 *buf,
0167                       int len)
0168 {
0169     void __iomem *fifoaddr = r8a66597->reg + offset;
0170     unsigned long count;
0171
0172     if (r8a66597->pdata->on_chip) {
0173         count = len / 4;
0174         ioread32_rep(fifoaddr, buf, count);
0175
0176         if (len & 0x00000003) {
0177             unsigned long tmp = ioread32(fifoaddr);
0178             memcpy((unsigned char *)buf + count * 4, &tmp,
0179                    len & 0x03);
0180         }
0181     } else {
0182         len = (len + 1) / 2;
0183         ioread16_rep(fifoaddr, buf, len);
0184     }
0185 }
0186
0187 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
0188                   unsigned long offset)
0189 {
0190     iowrite16(val, r8a66597->reg + offset);
0191 }
0192
0193 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
0194                  u16 val, u16 pat, unsigned long offset)
0195 {
0196     u16 tmp;
0197     tmp = r8a66597_read(r8a66597, offset);
0198     tmp = tmp & (~pat);
0199     tmp = tmp | val;
0200     r8a66597_write(r8a66597, tmp, offset);
0201 }
0202
0203 #define r8a66597_bclr(r8a66597, val, offset)    \
0204             r8a66597_mdfy(r8a66597, 0, val, offset)
0205 #define r8a66597_bset(r8a66597, val, offset)    \
0206             r8a66597_mdfy(r8a66597, val, 0, offset)
0207
0208 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
0209                        struct r8a66597_pipe *pipe, u16 *buf,
0210                        int len)
0211 {
0212     void __iomem *fifoaddr = r8a66597->reg + pipe->fifoaddr;
0213     unsigned long count;
0214     unsigned char *pb;
0215     int i;
0216
0217     if (r8a66597->pdata->on_chip) {
0218         count = len / 4;
0219         iowrite32_rep(fifoaddr, buf, count);
0220
0221         if (len & 0x00000003) {
0222             pb = (unsigned char *)buf + count * 4;
0223             for (i = 0; i < (len & 0x00000003); i++) {
0224                 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
0225                     iowrite8(pb[i], fifoaddr + i);
0226                 else
0227                     iowrite8(pb[i], fifoaddr + 3 - i);
0228             }
0229         }
0230     } else {
0231         int odd = len & 0x0001;
0232
0233         len = len / 2;
0234         iowrite16_rep(fifoaddr, buf, len);
0235         if (unlikely(odd)) {
0236             buf = &buf[len];
0237             if (r8a66597->pdata->wr0_shorted_to_wr1)
0238                 r8a66597_bclr(r8a66597, MBW_16, pipe->fifosel);
0239             iowrite8((unsigned char)*buf, fifoaddr);
0240             if (r8a66597->pdata->wr0_shorted_to_wr1)
0241                 r8a66597_bset(r8a66597, MBW_16, pipe->fifosel);
0242         }
0243     }
0244 }
0245
0246 static inline unsigned long get_syscfg_reg(int port)
0247 {
0248     return port == 0 ? SYSCFG0 : SYSCFG1;
0249 }
0250
0251 static inline unsigned long get_syssts_reg(int port)
0252 {
0253     return port == 0 ? SYSSTS0 : SYSSTS1;
0254 }
0255
0256 static inline unsigned long get_dvstctr_reg(int port)
0257 {
0258     return port == 0 ? DVSTCTR0 : DVSTCTR1;
0259 }
0260
0261 static inline unsigned long get_dmacfg_reg(int port)
0262 {
0263     return port == 0 ? DMA0CFG : DMA1CFG;
0264 }
0265
0266 static inline unsigned long get_intenb_reg(int port)
0267 {
0268     return port == 0 ? INTENB1 : INTENB2;
0269 }
0270
0271 static inline unsigned long get_intsts_reg(int port)
0272 {
0273     return port == 0 ? INTSTS1 : INTSTS2;
0274 }
0275
0276 static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
0277 {
0278     unsigned long dvstctr_reg = get_dvstctr_reg(port);
0279
0280     return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
0281 }
0282
0283 static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
0284                        int power)
0285 {
0286     unsigned long dvstctr_reg = get_dvstctr_reg(port);
0287
0288     if (r8a66597->pdata->port_power) {
0289         r8a66597->pdata->port_power(port, power);
0290     } else {
0291         if (power)
0292             r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
0293         else
0294             r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
0295     }
0296 }
0297
0298 static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
0299 {
0300     u16 clock = 0;
0301
0302     switch (pdata->xtal) {
0303     case R8A66597_PLATDATA_XTAL_12MHZ:
0304         clock = XTAL12;
0305         break;
0306     case R8A66597_PLATDATA_XTAL_24MHZ:
0307         clock = XTAL24;
0308         break;
0309     case R8A66597_PLATDATA_XTAL_48MHZ:
0310         clock = XTAL48;
0311         break;
0312     default:
0313         printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
0314         break;
0315     }
0316
0317     return clock;
0318 }
0319
0320 #define get_pipectr_addr(pipenum)   (PIPE1CTR + (pipenum - 1) * 2)
0321 #define get_pipetre_addr(pipenum)   (PIPE1TRE + (pipenum - 1) * 4)
0322 #define get_pipetrn_addr(pipenum)   (PIPE1TRN + (pipenum - 1) * 4)
0323 #define get_devadd_addr(address)    (DEVADD0 + address * 2)
0324
0325 #define enable_irq_ready(r8a66597, pipenum) \
0326     enable_pipe_irq(r8a66597, pipenum, BRDYENB)
0327 #define disable_irq_ready(r8a66597, pipenum)    \
0328     disable_pipe_irq(r8a66597, pipenum, BRDYENB)
0329 #define enable_irq_empty(r8a66597, pipenum) \
0330     enable_pipe_irq(r8a66597, pipenum, BEMPENB)
0331 #define disable_irq_empty(r8a66597, pipenum)    \
0332     disable_pipe_irq(r8a66597, pipenum, BEMPENB)
0333 #define enable_irq_nrdy(r8a66597, pipenum)  \
0334     enable_pipe_irq(r8a66597, pipenum, NRDYENB)
0335 #define disable_irq_nrdy(r8a66597, pipenum) \
0336     disable_pipe_irq(r8a66597, pipenum, NRDYENB)
0337
0338 #endif  /* __R8A66597_H__ */
0339