Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * This file contains code to reset and initialize USB host controllers.
0004  * Some of it includes work-arounds for PCI hardware and BIOS quirks.
0005  * It may need to run early during booting -- before USB would normally
0006  * initialize -- to ensure that Linux doesn't use any legacy modes.
0007  *
0008  *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
0009  *  (and others)
0010  */
0011 
0012 #include <linux/types.h>
0013 #include <linux/kernel.h>
0014 #include <linux/pci.h>
0015 #include <linux/delay.h>
0016 #include <linux/export.h>
0017 #include <linux/acpi.h>
0018 #include <linux/dmi.h>
0019 #include <linux/of.h>
0020 #include <linux/iopoll.h>
0021 
0022 #include "pci-quirks.h"
0023 #include "xhci-ext-caps.h"
0024 
0025 
0026 #define UHCI_USBLEGSUP      0xc0        /* legacy support */
0027 #define UHCI_USBCMD     0       /* command register */
0028 #define UHCI_USBINTR        4       /* interrupt register */
0029 #define UHCI_USBLEGSUP_RWC  0x8f00      /* the R/WC bits */
0030 #define UHCI_USBLEGSUP_RO   0x5040      /* R/O and reserved bits */
0031 #define UHCI_USBCMD_RUN     0x0001      /* RUN/STOP bit */
0032 #define UHCI_USBCMD_HCRESET 0x0002      /* Host Controller reset */
0033 #define UHCI_USBCMD_EGSM    0x0008      /* Global Suspend Mode */
0034 #define UHCI_USBCMD_CONFIGURE   0x0040      /* Config Flag */
0035 #define UHCI_USBINTR_RESUME 0x0002      /* Resume interrupt enable */
0036 
0037 #define OHCI_CONTROL        0x04
0038 #define OHCI_CMDSTATUS      0x08
0039 #define OHCI_INTRSTATUS     0x0c
0040 #define OHCI_INTRENABLE     0x10
0041 #define OHCI_INTRDISABLE    0x14
0042 #define OHCI_FMINTERVAL     0x34
0043 #define OHCI_HCFS       (3 << 6)    /* hc functional state */
0044 #define OHCI_HCR        (1 << 0)    /* host controller reset */
0045 #define OHCI_OCR        (1 << 3)    /* ownership change request */
0046 #define OHCI_CTRL_RWC       (1 << 9)    /* remote wakeup connected */
0047 #define OHCI_CTRL_IR        (1 << 8)    /* interrupt routing */
0048 #define OHCI_INTR_OC        (1 << 30)   /* ownership change */
0049 
0050 #define EHCI_HCC_PARAMS     0x08        /* extended capabilities */
0051 #define EHCI_USBCMD     0       /* command register */
0052 #define EHCI_USBCMD_RUN     (1 << 0)    /* RUN/STOP bit */
0053 #define EHCI_USBSTS     4       /* status register */
0054 #define EHCI_USBSTS_HALTED  (1 << 12)   /* HCHalted bit */
0055 #define EHCI_USBINTR        8       /* interrupt register */
0056 #define EHCI_CONFIGFLAG     0x40        /* configured flag register */
0057 #define EHCI_USBLEGSUP      0       /* legacy support register */
0058 #define EHCI_USBLEGSUP_BIOS (1 << 16)   /* BIOS semaphore */
0059 #define EHCI_USBLEGSUP_OS   (1 << 24)   /* OS semaphore */
0060 #define EHCI_USBLEGCTLSTS   4       /* legacy control/status */
0061 #define EHCI_USBLEGCTLSTS_SOOE  (1 << 13)   /* SMI on ownership change */
0062 
0063 /* AMD quirk use */
0064 #define AB_REG_BAR_LOW      0xe0
0065 #define AB_REG_BAR_HIGH     0xe1
0066 #define AB_REG_BAR_SB700    0xf0
0067 #define AB_INDX(addr)       ((addr) + 0x00)
0068 #define AB_DATA(addr)       ((addr) + 0x04)
0069 #define AX_INDXC        0x30
0070 #define AX_DATAC        0x34
0071 
0072 #define PT_ADDR_INDX        0xE8
0073 #define PT_READ_INDX        0xE4
0074 #define PT_SIG_1_ADDR       0xA520
0075 #define PT_SIG_2_ADDR       0xA521
0076 #define PT_SIG_3_ADDR       0xA522
0077 #define PT_SIG_4_ADDR       0xA523
0078 #define PT_SIG_1_DATA       0x78
0079 #define PT_SIG_2_DATA       0x56
0080 #define PT_SIG_3_DATA       0x34
0081 #define PT_SIG_4_DATA       0x12
0082 #define PT4_P1_REG      0xB521
0083 #define PT4_P2_REG      0xB522
0084 #define PT2_P1_REG      0xD520
0085 #define PT2_P2_REG      0xD521
0086 #define PT1_P1_REG      0xD522
0087 #define PT1_P2_REG      0xD523
0088 
0089 #define NB_PCIE_INDX_ADDR   0xe0
0090 #define NB_PCIE_INDX_DATA   0xe4
0091 #define PCIE_P_CNTL     0x10040
0092 #define BIF_NB          0x10002
0093 #define NB_PIF0_PWRDOWN_0   0x01100012
0094 #define NB_PIF0_PWRDOWN_1   0x01100013
0095 
0096 #define USB_INTEL_XUSB2PR      0xD0
0097 #define USB_INTEL_USB2PRM      0xD4
0098 #define USB_INTEL_USB3_PSSEN   0xD8
0099 #define USB_INTEL_USB3PRM      0xDC
0100 
0101 /* ASMEDIA quirk use */
0102 #define ASMT_DATA_WRITE0_REG    0xF8
0103 #define ASMT_DATA_WRITE1_REG    0xFC
0104 #define ASMT_CONTROL_REG    0xE0
0105 #define ASMT_CONTROL_WRITE_BIT  0x02
0106 #define ASMT_WRITEREG_CMD   0x10423
0107 #define ASMT_FLOWCTL_ADDR   0xFA30
0108 #define ASMT_FLOWCTL_DATA   0xBA
0109 #define ASMT_PSEUDO_DATA    0
0110 
0111 /*
0112  * amd_chipset_gen values represent AMD different chipset generations
0113  */
0114 enum amd_chipset_gen {
0115     NOT_AMD_CHIPSET = 0,
0116     AMD_CHIPSET_SB600,
0117     AMD_CHIPSET_SB700,
0118     AMD_CHIPSET_SB800,
0119     AMD_CHIPSET_HUDSON2,
0120     AMD_CHIPSET_BOLTON,
0121     AMD_CHIPSET_YANGTZE,
0122     AMD_CHIPSET_TAISHAN,
0123     AMD_CHIPSET_UNKNOWN,
0124 };
0125 
0126 struct amd_chipset_type {
0127     enum amd_chipset_gen gen;
0128     u8 rev;
0129 };
0130 
0131 static struct amd_chipset_info {
0132     struct pci_dev  *nb_dev;
0133     struct pci_dev  *smbus_dev;
0134     int nb_type;
0135     struct amd_chipset_type sb_type;
0136     int isoc_reqs;
0137     int probe_count;
0138     bool need_pll_quirk;
0139 } amd_chipset;
0140 
0141 static DEFINE_SPINLOCK(amd_lock);
0142 
0143 /*
0144  * amd_chipset_sb_type_init - initialize amd chipset southbridge type
0145  *
0146  * AMD FCH/SB generation and revision is identified by SMBus controller
0147  * vendor, device and revision IDs.
0148  *
0149  * Returns: 1 if it is an AMD chipset, 0 otherwise.
0150  */
0151 static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo)
0152 {
0153     u8 rev = 0;
0154     pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN;
0155 
0156     pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
0157             PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
0158     if (pinfo->smbus_dev) {
0159         rev = pinfo->smbus_dev->revision;
0160         if (rev >= 0x10 && rev <= 0x1f)
0161             pinfo->sb_type.gen = AMD_CHIPSET_SB600;
0162         else if (rev >= 0x30 && rev <= 0x3f)
0163             pinfo->sb_type.gen = AMD_CHIPSET_SB700;
0164         else if (rev >= 0x40 && rev <= 0x4f)
0165             pinfo->sb_type.gen = AMD_CHIPSET_SB800;
0166     } else {
0167         pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
0168                 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
0169 
0170         if (pinfo->smbus_dev) {
0171             rev = pinfo->smbus_dev->revision;
0172             if (rev >= 0x11 && rev <= 0x14)
0173                 pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2;
0174             else if (rev >= 0x15 && rev <= 0x18)
0175                 pinfo->sb_type.gen = AMD_CHIPSET_BOLTON;
0176             else if (rev >= 0x39 && rev <= 0x3a)
0177                 pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE;
0178         } else {
0179             pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
0180                               0x145c, NULL);
0181             if (pinfo->smbus_dev) {
0182                 rev = pinfo->smbus_dev->revision;
0183                 pinfo->sb_type.gen = AMD_CHIPSET_TAISHAN;
0184             } else {
0185                 pinfo->sb_type.gen = NOT_AMD_CHIPSET;
0186                 return 0;
0187             }
0188         }
0189     }
0190     pinfo->sb_type.rev = rev;
0191     return 1;
0192 }
0193 
0194 void sb800_prefetch(struct device *dev, int on)
0195 {
0196     u16 misc;
0197     struct pci_dev *pdev = to_pci_dev(dev);
0198 
0199     pci_read_config_word(pdev, 0x50, &misc);
0200     if (on == 0)
0201         pci_write_config_word(pdev, 0x50, misc & 0xfcff);
0202     else
0203         pci_write_config_word(pdev, 0x50, misc | 0x0300);
0204 }
0205 EXPORT_SYMBOL_GPL(sb800_prefetch);
0206 
0207 static void usb_amd_find_chipset_info(void)
0208 {
0209     unsigned long flags;
0210     struct amd_chipset_info info;
0211     info.need_pll_quirk = false;
0212 
0213     spin_lock_irqsave(&amd_lock, flags);
0214 
0215     /* probe only once */
0216     if (amd_chipset.probe_count > 0) {
0217         amd_chipset.probe_count++;
0218         spin_unlock_irqrestore(&amd_lock, flags);
0219         return;
0220     }
0221     memset(&info, 0, sizeof(info));
0222     spin_unlock_irqrestore(&amd_lock, flags);
0223 
0224     if (!amd_chipset_sb_type_init(&info)) {
0225         goto commit;
0226     }
0227 
0228     switch (info.sb_type.gen) {
0229     case AMD_CHIPSET_SB700:
0230         info.need_pll_quirk = info.sb_type.rev <= 0x3B;
0231         break;
0232     case AMD_CHIPSET_SB800:
0233     case AMD_CHIPSET_HUDSON2:
0234     case AMD_CHIPSET_BOLTON:
0235         info.need_pll_quirk = true;
0236         break;
0237     default:
0238         info.need_pll_quirk = false;
0239         break;
0240     }
0241 
0242     if (!info.need_pll_quirk) {
0243         if (info.smbus_dev) {
0244             pci_dev_put(info.smbus_dev);
0245             info.smbus_dev = NULL;
0246         }
0247         goto commit;
0248     }
0249 
0250     info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
0251     if (info.nb_dev) {
0252         info.nb_type = 1;
0253     } else {
0254         info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
0255         if (info.nb_dev) {
0256             info.nb_type = 2;
0257         } else {
0258             info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
0259                              0x9600, NULL);
0260             if (info.nb_dev)
0261                 info.nb_type = 3;
0262         }
0263     }
0264 
0265     printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
0266 
0267 commit:
0268 
0269     spin_lock_irqsave(&amd_lock, flags);
0270     if (amd_chipset.probe_count > 0) {
0271         /* race - someone else was faster - drop devices */
0272 
0273         /* Mark that we where here */
0274         amd_chipset.probe_count++;
0275 
0276         spin_unlock_irqrestore(&amd_lock, flags);
0277 
0278         pci_dev_put(info.nb_dev);
0279         pci_dev_put(info.smbus_dev);
0280 
0281     } else {
0282         /* no race - commit the result */
0283         info.probe_count++;
0284         amd_chipset = info;
0285         spin_unlock_irqrestore(&amd_lock, flags);
0286     }
0287 }
0288 
0289 int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev)
0290 {
0291     /* Make sure amd chipset type has already been initialized */
0292     usb_amd_find_chipset_info();
0293     if (amd_chipset.sb_type.gen == AMD_CHIPSET_YANGTZE ||
0294         amd_chipset.sb_type.gen == AMD_CHIPSET_TAISHAN) {
0295         dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n");
0296         return 1;
0297     }
0298     return 0;
0299 }
0300 EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk);
0301 
0302 bool usb_amd_hang_symptom_quirk(void)
0303 {
0304     u8 rev;
0305 
0306     usb_amd_find_chipset_info();
0307     rev = amd_chipset.sb_type.rev;
0308     /* SB600 and old version of SB700 have hang symptom bug */
0309     return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 ||
0310             (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
0311              rev >= 0x3a && rev <= 0x3b);
0312 }
0313 EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk);
0314 
0315 bool usb_amd_prefetch_quirk(void)
0316 {
0317     usb_amd_find_chipset_info();
0318     /* SB800 needs pre-fetch fix */
0319     return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800;
0320 }
0321 EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk);
0322 
0323 bool usb_amd_quirk_pll_check(void)
0324 {
0325     usb_amd_find_chipset_info();
0326     return amd_chipset.need_pll_quirk;
0327 }
0328 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_check);
0329 
0330 /*
0331  * The hardware normally enables the A-link power management feature, which
0332  * lets the system lower the power consumption in idle states.
0333  *
0334  * This USB quirk prevents the link going into that lower power state
0335  * during isochronous transfers.
0336  *
0337  * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
0338  * some AMD platforms may stutter or have breaks occasionally.
0339  */
0340 static void usb_amd_quirk_pll(int disable)
0341 {
0342     u32 addr, addr_low, addr_high, val;
0343     u32 bit = disable ? 0 : 1;
0344     unsigned long flags;
0345 
0346     spin_lock_irqsave(&amd_lock, flags);
0347 
0348     if (disable) {
0349         amd_chipset.isoc_reqs++;
0350         if (amd_chipset.isoc_reqs > 1) {
0351             spin_unlock_irqrestore(&amd_lock, flags);
0352             return;
0353         }
0354     } else {
0355         amd_chipset.isoc_reqs--;
0356         if (amd_chipset.isoc_reqs > 0) {
0357             spin_unlock_irqrestore(&amd_lock, flags);
0358             return;
0359         }
0360     }
0361 
0362     if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 ||
0363             amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 ||
0364             amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) {
0365         outb_p(AB_REG_BAR_LOW, 0xcd6);
0366         addr_low = inb_p(0xcd7);
0367         outb_p(AB_REG_BAR_HIGH, 0xcd6);
0368         addr_high = inb_p(0xcd7);
0369         addr = addr_high << 8 | addr_low;
0370 
0371         outl_p(0x30, AB_INDX(addr));
0372         outl_p(0x40, AB_DATA(addr));
0373         outl_p(0x34, AB_INDX(addr));
0374         val = inl_p(AB_DATA(addr));
0375     } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
0376             amd_chipset.sb_type.rev <= 0x3b) {
0377         pci_read_config_dword(amd_chipset.smbus_dev,
0378                     AB_REG_BAR_SB700, &addr);
0379         outl(AX_INDXC, AB_INDX(addr));
0380         outl(0x40, AB_DATA(addr));
0381         outl(AX_DATAC, AB_INDX(addr));
0382         val = inl(AB_DATA(addr));
0383     } else {
0384         spin_unlock_irqrestore(&amd_lock, flags);
0385         return;
0386     }
0387 
0388     if (disable) {
0389         val &= ~0x08;
0390         val |= (1 << 4) | (1 << 9);
0391     } else {
0392         val |= 0x08;
0393         val &= ~((1 << 4) | (1 << 9));
0394     }
0395     outl_p(val, AB_DATA(addr));
0396 
0397     if (!amd_chipset.nb_dev) {
0398         spin_unlock_irqrestore(&amd_lock, flags);
0399         return;
0400     }
0401 
0402     if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
0403         addr = PCIE_P_CNTL;
0404         pci_write_config_dword(amd_chipset.nb_dev,
0405                     NB_PCIE_INDX_ADDR, addr);
0406         pci_read_config_dword(amd_chipset.nb_dev,
0407                     NB_PCIE_INDX_DATA, &val);
0408 
0409         val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
0410         val |= bit | (bit << 3) | (bit << 12);
0411         val |= ((!bit) << 4) | ((!bit) << 9);
0412         pci_write_config_dword(amd_chipset.nb_dev,
0413                     NB_PCIE_INDX_DATA, val);
0414 
0415         addr = BIF_NB;
0416         pci_write_config_dword(amd_chipset.nb_dev,
0417                     NB_PCIE_INDX_ADDR, addr);
0418         pci_read_config_dword(amd_chipset.nb_dev,
0419                     NB_PCIE_INDX_DATA, &val);
0420         val &= ~(1 << 8);
0421         val |= bit << 8;
0422 
0423         pci_write_config_dword(amd_chipset.nb_dev,
0424                     NB_PCIE_INDX_DATA, val);
0425     } else if (amd_chipset.nb_type == 2) {
0426         addr = NB_PIF0_PWRDOWN_0;
0427         pci_write_config_dword(amd_chipset.nb_dev,
0428                     NB_PCIE_INDX_ADDR, addr);
0429         pci_read_config_dword(amd_chipset.nb_dev,
0430                     NB_PCIE_INDX_DATA, &val);
0431         if (disable)
0432             val &= ~(0x3f << 7);
0433         else
0434             val |= 0x3f << 7;
0435 
0436         pci_write_config_dword(amd_chipset.nb_dev,
0437                     NB_PCIE_INDX_DATA, val);
0438 
0439         addr = NB_PIF0_PWRDOWN_1;
0440         pci_write_config_dword(amd_chipset.nb_dev,
0441                     NB_PCIE_INDX_ADDR, addr);
0442         pci_read_config_dword(amd_chipset.nb_dev,
0443                     NB_PCIE_INDX_DATA, &val);
0444         if (disable)
0445             val &= ~(0x3f << 7);
0446         else
0447             val |= 0x3f << 7;
0448 
0449         pci_write_config_dword(amd_chipset.nb_dev,
0450                     NB_PCIE_INDX_DATA, val);
0451     }
0452 
0453     spin_unlock_irqrestore(&amd_lock, flags);
0454     return;
0455 }
0456 
0457 void usb_amd_quirk_pll_disable(void)
0458 {
0459     usb_amd_quirk_pll(1);
0460 }
0461 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
0462 
0463 static int usb_asmedia_wait_write(struct pci_dev *pdev)
0464 {
0465     unsigned long retry_count;
0466     unsigned char value;
0467 
0468     for (retry_count = 1000; retry_count > 0; --retry_count) {
0469 
0470         pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value);
0471 
0472         if (value == 0xff) {
0473             dev_err(&pdev->dev, "%s: check_ready ERROR", __func__);
0474             return -EIO;
0475         }
0476 
0477         if ((value & ASMT_CONTROL_WRITE_BIT) == 0)
0478             return 0;
0479 
0480         udelay(50);
0481     }
0482 
0483     dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__);
0484     return -ETIMEDOUT;
0485 }
0486 
0487 void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev)
0488 {
0489     if (usb_asmedia_wait_write(pdev) != 0)
0490         return;
0491 
0492     /* send command and address to device */
0493     pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD);
0494     pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR);
0495     pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
0496 
0497     if (usb_asmedia_wait_write(pdev) != 0)
0498         return;
0499 
0500     /* send data to device */
0501     pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA);
0502     pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA);
0503     pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
0504 }
0505 EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol);
0506 
0507 void usb_amd_quirk_pll_enable(void)
0508 {
0509     usb_amd_quirk_pll(0);
0510 }
0511 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
0512 
0513 void usb_amd_dev_put(void)
0514 {
0515     struct pci_dev *nb, *smbus;
0516     unsigned long flags;
0517 
0518     spin_lock_irqsave(&amd_lock, flags);
0519 
0520     amd_chipset.probe_count--;
0521     if (amd_chipset.probe_count > 0) {
0522         spin_unlock_irqrestore(&amd_lock, flags);
0523         return;
0524     }
0525 
0526     /* save them to pci_dev_put outside of spinlock */
0527     nb    = amd_chipset.nb_dev;
0528     smbus = amd_chipset.smbus_dev;
0529 
0530     amd_chipset.nb_dev = NULL;
0531     amd_chipset.smbus_dev = NULL;
0532     amd_chipset.nb_type = 0;
0533     memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type));
0534     amd_chipset.isoc_reqs = 0;
0535     amd_chipset.need_pll_quirk = false;
0536 
0537     spin_unlock_irqrestore(&amd_lock, flags);
0538 
0539     pci_dev_put(nb);
0540     pci_dev_put(smbus);
0541 }
0542 EXPORT_SYMBOL_GPL(usb_amd_dev_put);
0543 
0544 /*
0545  * Check if port is disabled in BIOS on AMD Promontory host.
0546  * BIOS Disabled ports may wake on connect/disconnect and need
0547  * driver workaround to keep them disabled.
0548  * Returns true if port is marked disabled.
0549  */
0550 bool usb_amd_pt_check_port(struct device *device, int port)
0551 {
0552     unsigned char value, port_shift;
0553     struct pci_dev *pdev;
0554     u16 reg;
0555 
0556     pdev = to_pci_dev(device);
0557     pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_1_ADDR);
0558 
0559     pci_read_config_byte(pdev, PT_READ_INDX, &value);
0560     if (value != PT_SIG_1_DATA)
0561         return false;
0562 
0563     pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_2_ADDR);
0564 
0565     pci_read_config_byte(pdev, PT_READ_INDX, &value);
0566     if (value != PT_SIG_2_DATA)
0567         return false;
0568 
0569     pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_3_ADDR);
0570 
0571     pci_read_config_byte(pdev, PT_READ_INDX, &value);
0572     if (value != PT_SIG_3_DATA)
0573         return false;
0574 
0575     pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_4_ADDR);
0576 
0577     pci_read_config_byte(pdev, PT_READ_INDX, &value);
0578     if (value != PT_SIG_4_DATA)
0579         return false;
0580 
0581     /* Check disabled port setting, if bit is set port is enabled */
0582     switch (pdev->device) {
0583     case 0x43b9:
0584     case 0x43ba:
0585     /*
0586      * device is AMD_PROMONTORYA_4(0x43b9) or PROMONTORYA_3(0x43ba)
0587      * PT4_P1_REG bits[7..1] represents USB2.0 ports 6 to 0
0588      * PT4_P2_REG bits[6..0] represents ports 13 to 7
0589      */
0590         if (port > 6) {
0591             reg = PT4_P2_REG;
0592             port_shift = port - 7;
0593         } else {
0594             reg = PT4_P1_REG;
0595             port_shift = port + 1;
0596         }
0597         break;
0598     case 0x43bb:
0599     /*
0600      * device is AMD_PROMONTORYA_2(0x43bb)
0601      * PT2_P1_REG bits[7..5] represents USB2.0 ports 2 to 0
0602      * PT2_P2_REG bits[5..0] represents ports 9 to 3
0603      */
0604         if (port > 2) {
0605             reg = PT2_P2_REG;
0606             port_shift = port - 3;
0607         } else {
0608             reg = PT2_P1_REG;
0609             port_shift = port + 5;
0610         }
0611         break;
0612     case 0x43bc:
0613     /*
0614      * device is AMD_PROMONTORYA_1(0x43bc)
0615      * PT1_P1_REG[7..4] represents USB2.0 ports 3 to 0
0616      * PT1_P2_REG[5..0] represents ports 9 to 4
0617      */
0618         if (port > 3) {
0619             reg = PT1_P2_REG;
0620             port_shift = port - 4;
0621         } else {
0622             reg = PT1_P1_REG;
0623             port_shift = port + 4;
0624         }
0625         break;
0626     default:
0627         return false;
0628     }
0629     pci_write_config_word(pdev, PT_ADDR_INDX, reg);
0630     pci_read_config_byte(pdev, PT_READ_INDX, &value);
0631 
0632     return !(value & BIT(port_shift));
0633 }
0634 EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);
0635 
0636 /*
0637  * Make sure the controller is completely inactive, unable to
0638  * generate interrupts or do DMA.
0639  */
0640 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
0641 {
0642     /* Turn off PIRQ enable and SMI enable.  (This also turns off the
0643      * BIOS's USB Legacy Support.)  Turn off all the R/WC bits too.
0644      */
0645     pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
0646 
0647     /* Reset the HC - this will force us to get a
0648      * new notification of any already connected
0649      * ports due to the virtual disconnect that it
0650      * implies.
0651      */
0652     outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
0653     mb();
0654     udelay(5);
0655     if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
0656         dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
0657 
0658     /* Just to be safe, disable interrupt requests and
0659      * make sure the controller is stopped.
0660      */
0661     outw(0, base + UHCI_USBINTR);
0662     outw(0, base + UHCI_USBCMD);
0663 }
0664 EXPORT_SYMBOL_GPL(uhci_reset_hc);
0665 
0666 /*
0667  * Initialize a controller that was newly discovered or has just been
0668  * resumed.  In either case we can't be sure of its previous state.
0669  *
0670  * Returns: 1 if the controller was reset, 0 otherwise.
0671  */
0672 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
0673 {
0674     u16 legsup;
0675     unsigned int cmd, intr;
0676 
0677     /*
0678      * When restarting a suspended controller, we expect all the
0679      * settings to be the same as we left them:
0680      *
0681      *  PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
0682      *  Controller is stopped and configured with EGSM set;
0683      *  No interrupts enabled except possibly Resume Detect.
0684      *
0685      * If any of these conditions are violated we do a complete reset.
0686      */
0687     pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
0688     if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
0689         dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
0690                 __func__, legsup);
0691         goto reset_needed;
0692     }
0693 
0694     cmd = inw(base + UHCI_USBCMD);
0695     if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
0696             !(cmd & UHCI_USBCMD_EGSM)) {
0697         dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
0698                 __func__, cmd);
0699         goto reset_needed;
0700     }
0701 
0702     intr = inw(base + UHCI_USBINTR);
0703     if (intr & (~UHCI_USBINTR_RESUME)) {
0704         dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
0705                 __func__, intr);
0706         goto reset_needed;
0707     }
0708     return 0;
0709 
0710 reset_needed:
0711     dev_dbg(&pdev->dev, "Performing full reset\n");
0712     uhci_reset_hc(pdev, base);
0713     return 1;
0714 }
0715 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
0716 
0717 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
0718 {
0719     u16 cmd;
0720     return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
0721 }
0722 
0723 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
0724 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
0725 
0726 static void quirk_usb_handoff_uhci(struct pci_dev *pdev)
0727 {
0728     unsigned long base = 0;
0729     int i;
0730 
0731     if (!pio_enabled(pdev))
0732         return;
0733 
0734     for (i = 0; i < PCI_STD_NUM_BARS; i++)
0735         if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
0736             base = pci_resource_start(pdev, i);
0737             break;
0738         }
0739 
0740     if (base)
0741         uhci_check_and_reset_hc(pdev, base);
0742 }
0743 
0744 static int mmio_resource_enabled(struct pci_dev *pdev, int idx)
0745 {
0746     return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
0747 }
0748 
0749 static void quirk_usb_handoff_ohci(struct pci_dev *pdev)
0750 {
0751     void __iomem *base;
0752     u32 control;
0753     u32 fminterval = 0;
0754     bool no_fminterval = false;
0755     int cnt;
0756 
0757     if (!mmio_resource_enabled(pdev, 0))
0758         return;
0759 
0760     base = pci_ioremap_bar(pdev, 0);
0761     if (base == NULL)
0762         return;
0763 
0764     /*
0765      * ULi M5237 OHCI controller locks the whole system when accessing
0766      * the OHCI_FMINTERVAL offset.
0767      */
0768     if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237)
0769         no_fminterval = true;
0770 
0771     control = readl(base + OHCI_CONTROL);
0772 
0773 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
0774 #ifdef __hppa__
0775 #define OHCI_CTRL_MASK      (OHCI_CTRL_RWC | OHCI_CTRL_IR)
0776 #else
0777 #define OHCI_CTRL_MASK      OHCI_CTRL_RWC
0778 
0779     if (control & OHCI_CTRL_IR) {
0780         int wait_time = 500; /* arbitrary; 5 seconds */
0781         writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
0782         writel(OHCI_OCR, base + OHCI_CMDSTATUS);
0783         while (wait_time > 0 &&
0784                 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
0785             wait_time -= 10;
0786             msleep(10);
0787         }
0788         if (wait_time <= 0)
0789             dev_warn(&pdev->dev,
0790                  "OHCI: BIOS handoff failed (BIOS bug?) %08x\n",
0791                  readl(base + OHCI_CONTROL));
0792     }
0793 #endif
0794 
0795     /* disable interrupts */
0796     writel((u32) ~0, base + OHCI_INTRDISABLE);
0797 
0798     /* Go into the USB_RESET state, preserving RWC (and possibly IR) */
0799     writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
0800     readl(base + OHCI_CONTROL);
0801 
0802     /* software reset of the controller, preserving HcFmInterval */
0803     if (!no_fminterval)
0804         fminterval = readl(base + OHCI_FMINTERVAL);
0805 
0806     writel(OHCI_HCR, base + OHCI_CMDSTATUS);
0807 
0808     /* reset requires max 10 us delay */
0809     for (cnt = 30; cnt > 0; --cnt) {    /* ... allow extra time */
0810         if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
0811             break;
0812         udelay(1);
0813     }
0814 
0815     if (!no_fminterval)
0816         writel(fminterval, base + OHCI_FMINTERVAL);
0817 
0818     /* Now the controller is safely in SUSPEND and nothing can wake it up */
0819     iounmap(base);
0820 }
0821 
0822 static const struct dmi_system_id ehci_dmi_nohandoff_table[] = {
0823     {
0824         /*  Pegatron Lucid (ExoPC) */
0825         .matches = {
0826             DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
0827             DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
0828         },
0829     },
0830     {
0831         /*  Pegatron Lucid (Ordissimo AIRIS) */
0832         .matches = {
0833             DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
0834             DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
0835         },
0836     },
0837     {
0838         /*  Pegatron Lucid (Ordissimo) */
0839         .matches = {
0840             DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"),
0841             DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
0842         },
0843     },
0844     {
0845         /* HASEE E200 */
0846         .matches = {
0847             DMI_MATCH(DMI_BOARD_VENDOR, "HASEE"),
0848             DMI_MATCH(DMI_BOARD_NAME, "E210"),
0849             DMI_MATCH(DMI_BIOS_VERSION, "6.00"),
0850         },
0851     },
0852     { }
0853 };
0854 
0855 static void ehci_bios_handoff(struct pci_dev *pdev,
0856                     void __iomem *op_reg_base,
0857                     u32 cap, u8 offset)
0858 {
0859     int try_handoff = 1, tried_handoff = 0;
0860 
0861     /*
0862      * The Pegatron Lucid tablet sporadically waits for 98 seconds trying
0863      * the handoff on its unused controller.  Skip it.
0864      *
0865      * The HASEE E200 hangs when the semaphore is set (bugzilla #77021).
0866      */
0867     if (pdev->vendor == 0x8086 && (pdev->device == 0x283a ||
0868             pdev->device == 0x27cc)) {
0869         if (dmi_check_system(ehci_dmi_nohandoff_table))
0870             try_handoff = 0;
0871     }
0872 
0873     if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
0874         dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
0875 
0876 #if 0
0877 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
0878  * but that seems dubious in general (the BIOS left it off intentionally)
0879  * and is known to prevent some systems from booting.  so we won't do this
0880  * unless maybe we can determine when we're on a system that needs SMI forced.
0881  */
0882         /* BIOS workaround (?): be sure the pre-Linux code
0883          * receives the SMI
0884          */
0885         pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
0886         pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
0887                        val | EHCI_USBLEGCTLSTS_SOOE);
0888 #endif
0889 
0890         /* some systems get upset if this semaphore is
0891          * set for any other reason than forcing a BIOS
0892          * handoff..
0893          */
0894         pci_write_config_byte(pdev, offset + 3, 1);
0895     }
0896 
0897     /* if boot firmware now owns EHCI, spin till it hands it over. */
0898     if (try_handoff) {
0899         int msec = 1000;
0900         while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
0901             tried_handoff = 1;
0902             msleep(10);
0903             msec -= 10;
0904             pci_read_config_dword(pdev, offset, &cap);
0905         }
0906     }
0907 
0908     if (cap & EHCI_USBLEGSUP_BIOS) {
0909         /* well, possibly buggy BIOS... try to shut it down,
0910          * and hope nothing goes too wrong
0911          */
0912         if (try_handoff)
0913             dev_warn(&pdev->dev,
0914                  "EHCI: BIOS handoff failed (BIOS bug?) %08x\n",
0915                  cap);
0916         pci_write_config_byte(pdev, offset + 2, 0);
0917     }
0918 
0919     /* just in case, always disable EHCI SMIs */
0920     pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
0921 
0922     /* If the BIOS ever owned the controller then we can't expect
0923      * any power sessions to remain intact.
0924      */
0925     if (tried_handoff)
0926         writel(0, op_reg_base + EHCI_CONFIGFLAG);
0927 }
0928 
0929 static void quirk_usb_disable_ehci(struct pci_dev *pdev)
0930 {
0931     void __iomem *base, *op_reg_base;
0932     u32 hcc_params, cap, val;
0933     u8  offset, cap_length;
0934     int wait_time, count = 256/4;
0935 
0936     if (!mmio_resource_enabled(pdev, 0))
0937         return;
0938 
0939     base = pci_ioremap_bar(pdev, 0);
0940     if (base == NULL)
0941         return;
0942 
0943     cap_length = readb(base);
0944     op_reg_base = base + cap_length;
0945 
0946     /* EHCI 0.96 and later may have "extended capabilities"
0947      * spec section 5.1 explains the bios handoff, e.g. for
0948      * booting from USB disk or using a usb keyboard
0949      */
0950     hcc_params = readl(base + EHCI_HCC_PARAMS);
0951     offset = (hcc_params >> 8) & 0xff;
0952     while (offset && --count) {
0953         pci_read_config_dword(pdev, offset, &cap);
0954 
0955         switch (cap & 0xff) {
0956         case 1:
0957             ehci_bios_handoff(pdev, op_reg_base, cap, offset);
0958             break;
0959         case 0: /* Illegal reserved cap, set cap=0 so we exit */
0960             cap = 0;
0961             fallthrough;
0962         default:
0963             dev_warn(&pdev->dev,
0964                  "EHCI: unrecognized capability %02x\n",
0965                  cap & 0xff);
0966         }
0967         offset = (cap >> 8) & 0xff;
0968     }
0969     if (!count)
0970         dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
0971 
0972     /*
0973      * halt EHCI & disable its interrupts in any case
0974      */
0975     val = readl(op_reg_base + EHCI_USBSTS);
0976     if ((val & EHCI_USBSTS_HALTED) == 0) {
0977         val = readl(op_reg_base + EHCI_USBCMD);
0978         val &= ~EHCI_USBCMD_RUN;
0979         writel(val, op_reg_base + EHCI_USBCMD);
0980 
0981         wait_time = 2000;
0982         do {
0983             writel(0x3f, op_reg_base + EHCI_USBSTS);
0984             udelay(100);
0985             wait_time -= 100;
0986             val = readl(op_reg_base + EHCI_USBSTS);
0987             if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
0988                 break;
0989             }
0990         } while (wait_time > 0);
0991     }
0992     writel(0, op_reg_base + EHCI_USBINTR);
0993     writel(0x3f, op_reg_base + EHCI_USBSTS);
0994 
0995     iounmap(base);
0996 }
0997 
0998 /*
0999  * handshake - spin reading a register until handshake completes
1000  * @ptr: address of hc register to be read
1001  * @mask: bits to look at in result of read
1002  * @done: value of those bits when handshake succeeds
1003  * @wait_usec: timeout in microseconds
1004  * @delay_usec: delay in microseconds to wait between polling
1005  *
1006  * Polls a register every delay_usec microseconds.
1007  * Returns 0 when the mask bits have the value done.
1008  * Returns -ETIMEDOUT if this condition is not true after
1009  * wait_usec microseconds have passed.
1010  */
1011 static int handshake(void __iomem *ptr, u32 mask, u32 done,
1012         int wait_usec, int delay_usec)
1013 {
1014     u32 result;
1015 
1016     return readl_poll_timeout_atomic(ptr, result,
1017                      ((result & mask) == done),
1018                      delay_usec, wait_usec);
1019 }
1020 
1021 /*
1022  * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
1023  * share some number of ports.  These ports can be switched between either
1024  * controller.  Not all of the ports under the EHCI host controller may be
1025  * switchable.
1026  *
1027  * The ports should be switched over to xHCI before PCI probes for any device
1028  * start.  This avoids active devices under EHCI being disconnected during the
1029  * port switchover, which could cause loss of data on USB storage devices, or
1030  * failed boot when the root file system is on a USB mass storage device and is
1031  * enumerated under EHCI first.
1032  *
1033  * We write into the xHC's PCI configuration space in some Intel-specific
1034  * registers to switch the ports over.  The USB 3.0 terminations and the USB
1035  * 2.0 data wires are switched separately.  We want to enable the SuperSpeed
1036  * terminations before switching the USB 2.0 wires over, so that USB 3.0
1037  * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
1038  */
1039 void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev)
1040 {
1041     u32     ports_available;
1042     bool        ehci_found = false;
1043     struct pci_dev  *companion = NULL;
1044 
1045     /* Sony VAIO t-series with subsystem device ID 90a8 is not capable of
1046      * switching ports from EHCI to xHCI
1047      */
1048     if (xhci_pdev->subsystem_vendor == PCI_VENDOR_ID_SONY &&
1049         xhci_pdev->subsystem_device == 0x90a8)
1050         return;
1051 
1052     /* make sure an intel EHCI controller exists */
1053     for_each_pci_dev(companion) {
1054         if (companion->class == PCI_CLASS_SERIAL_USB_EHCI &&
1055             companion->vendor == PCI_VENDOR_ID_INTEL) {
1056             ehci_found = true;
1057             break;
1058         }
1059     }
1060 
1061     if (!ehci_found)
1062         return;
1063 
1064     /* Don't switchover the ports if the user hasn't compiled the xHCI
1065      * driver.  Otherwise they will see "dead" USB ports that don't power
1066      * the devices.
1067      */
1068     if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) {
1069         dev_warn(&xhci_pdev->dev,
1070              "CONFIG_USB_XHCI_HCD is turned off, defaulting to EHCI.\n");
1071         dev_warn(&xhci_pdev->dev,
1072                 "USB 3.0 devices will work at USB 2.0 speeds.\n");
1073         usb_disable_xhci_ports(xhci_pdev);
1074         return;
1075     }
1076 
1077     /* Read USB3PRM, the USB 3.0 Port Routing Mask Register
1078      * Indicate the ports that can be changed from OS.
1079      */
1080     pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM,
1081             &ports_available);
1082 
1083     dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n",
1084             ports_available);
1085 
1086     /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
1087      * Register, to turn on SuperSpeed terminations for the
1088      * switchable ports.
1089      */
1090     pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
1091             ports_available);
1092 
1093     pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
1094             &ports_available);
1095     dev_dbg(&xhci_pdev->dev,
1096         "USB 3.0 ports that are now enabled under xHCI: 0x%x\n",
1097         ports_available);
1098 
1099     /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register
1100      * Indicate the USB 2.0 ports to be controlled by the xHCI host.
1101      */
1102 
1103     pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM,
1104             &ports_available);
1105 
1106     dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
1107             ports_available);
1108 
1109     /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
1110      * switch the USB 2.0 power and data lines over to the xHCI
1111      * host.
1112      */
1113     pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
1114             ports_available);
1115 
1116     pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
1117             &ports_available);
1118     dev_dbg(&xhci_pdev->dev,
1119         "USB 2.0 ports that are now switched over to xHCI: 0x%x\n",
1120         ports_available);
1121 }
1122 EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports);
1123 
1124 void usb_disable_xhci_ports(struct pci_dev *xhci_pdev)
1125 {
1126     pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0);
1127     pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0);
1128 }
1129 EXPORT_SYMBOL_GPL(usb_disable_xhci_ports);
1130 
1131 /*
1132  * PCI Quirks for xHCI.
1133  *
1134  * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
1135  * It signals to the BIOS that the OS wants control of the host controller,
1136  * and then waits 1 second for the BIOS to hand over control.
1137  * If we timeout, assume the BIOS is broken and take control anyway.
1138  */
1139 static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
1140 {
1141     void __iomem *base;
1142     int ext_cap_offset;
1143     void __iomem *op_reg_base;
1144     u32 val;
1145     int timeout;
1146     int len = pci_resource_len(pdev, 0);
1147 
1148     if (!mmio_resource_enabled(pdev, 0))
1149         return;
1150 
1151     base = ioremap(pci_resource_start(pdev, 0), len);
1152     if (base == NULL)
1153         return;
1154 
1155     /*
1156      * Find the Legacy Support Capability register -
1157      * this is optional for xHCI host controllers.
1158      */
1159     ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY);
1160 
1161     if (!ext_cap_offset)
1162         goto hc_init;
1163 
1164     if ((ext_cap_offset + sizeof(val)) > len) {
1165         /* We're reading garbage from the controller */
1166         dev_warn(&pdev->dev, "xHCI controller failing to respond");
1167         goto iounmap;
1168     }
1169     val = readl(base + ext_cap_offset);
1170 
1171     /* Auto handoff never worked for these devices. Force it and continue */
1172     if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) ||
1173             (pdev->vendor == PCI_VENDOR_ID_RENESAS
1174              && pdev->device == 0x0014)) {
1175         val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED;
1176         writel(val, base + ext_cap_offset);
1177     }
1178 
1179     /* If the BIOS owns the HC, signal that the OS wants it, and wait */
1180     if (val & XHCI_HC_BIOS_OWNED) {
1181         writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
1182 
1183         /* Wait for 1 second with 10 microsecond polling interval */
1184         timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
1185                 0, 1000000, 10);
1186 
1187         /* Assume a buggy BIOS and take HC ownership anyway */
1188         if (timeout) {
1189             dev_warn(&pdev->dev,
1190                  "xHCI BIOS handoff failed (BIOS bug ?) %08x\n",
1191                  val);
1192             writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
1193         }
1194     }
1195 
1196     val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
1197     /* Mask off (turn off) any enabled SMIs */
1198     val &= XHCI_LEGACY_DISABLE_SMI;
1199     /* Mask all SMI events bits, RW1C */
1200     val |= XHCI_LEGACY_SMI_EVENTS;
1201     /* Disable any BIOS SMIs and clear all SMI events*/
1202     writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
1203 
1204 hc_init:
1205     if (pdev->vendor == PCI_VENDOR_ID_INTEL)
1206         usb_enable_intel_xhci_ports(pdev);
1207 
1208     op_reg_base = base + XHCI_HC_LENGTH(readl(base));
1209 
1210     /* Wait for the host controller to be ready before writing any
1211      * operational or runtime registers.  Wait 5 seconds and no more.
1212      */
1213     timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
1214             5000000, 10);
1215     /* Assume a buggy HC and start HC initialization anyway */
1216     if (timeout) {
1217         val = readl(op_reg_base + XHCI_STS_OFFSET);
1218         dev_warn(&pdev->dev,
1219              "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n",
1220              val);
1221     }
1222 
1223     /* Send the halt and disable interrupts command */
1224     val = readl(op_reg_base + XHCI_CMD_OFFSET);
1225     val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
1226     writel(val, op_reg_base + XHCI_CMD_OFFSET);
1227 
1228     /* Wait for the HC to halt - poll every 125 usec (one microframe). */
1229     timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
1230             XHCI_MAX_HALT_USEC, 125);
1231     if (timeout) {
1232         val = readl(op_reg_base + XHCI_STS_OFFSET);
1233         dev_warn(&pdev->dev,
1234              "xHCI HW did not halt within %d usec status = 0x%x\n",
1235              XHCI_MAX_HALT_USEC, val);
1236     }
1237 
1238 iounmap:
1239     iounmap(base);
1240 }
1241 
1242 static void quirk_usb_early_handoff(struct pci_dev *pdev)
1243 {
1244     struct device_node *parent;
1245     bool is_rpi;
1246 
1247     /* Skip Netlogic mips SoC's internal PCI USB controller.
1248      * This device does not need/support EHCI/OHCI handoff
1249      */
1250     if (pdev->vendor == 0x184e) /* vendor Netlogic */
1251         return;
1252 
1253     /*
1254      * Bypass the Raspberry Pi 4 controller xHCI controller, things are
1255      * taken care of by the board's co-processor.
1256      */
1257     if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
1258         parent = of_get_parent(pdev->bus->dev.of_node);
1259         is_rpi = of_device_is_compatible(parent, "brcm,bcm2711-pcie");
1260         of_node_put(parent);
1261         if (is_rpi)
1262             return;
1263     }
1264 
1265     if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
1266             pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
1267             pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&
1268             pdev->class != PCI_CLASS_SERIAL_USB_XHCI)
1269         return;
1270 
1271     if (pci_enable_device(pdev) < 0) {
1272         dev_warn(&pdev->dev,
1273              "Can't enable PCI device, BIOS handoff failed.\n");
1274         return;
1275     }
1276     if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
1277         quirk_usb_handoff_uhci(pdev);
1278     else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
1279         quirk_usb_handoff_ohci(pdev);
1280     else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
1281         quirk_usb_disable_ehci(pdev);
1282     else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
1283         quirk_usb_handoff_xhci(pdev);
1284     pci_disable_device(pdev);
1285 }
1286 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1287             PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!