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0001 /* SPDX-License-Identifier: GPL-1.0+ */
0002 /*
0003  * OHCI HCD (Host Controller Driver) for USB.
0004  *
0005  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
0006  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
0007  *
0008  * This file is licenced under the GPL.
0009  */
0010 
0011 /*
0012  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
0013  * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
0014  * host controller implementation.
0015  */
0016 typedef __u32 __bitwise __hc32;
0017 typedef __u16 __bitwise __hc16;
0018 
0019 /*
0020  * OHCI Endpoint Descriptor (ED) ... holds TD queue
0021  * See OHCI spec, section 4.2
0022  *
0023  * This is a "Queue Head" for those transfers, which is why
0024  * both EHCI and UHCI call similar structures a "QH".
0025  */
0026 struct ed {
0027     /* first fields are hardware-specified */
0028     __hc32          hwINFO;      /* endpoint config bitmap */
0029     /* info bits defined by hcd */
0030 #define ED_DEQUEUE  (1 << 27)
0031     /* info bits defined by the hardware */
0032 #define ED_ISO      (1 << 15)
0033 #define ED_SKIP     (1 << 14)
0034 #define ED_LOWSPEED (1 << 13)
0035 #define ED_OUT      (0x01 << 11)
0036 #define ED_IN       (0x02 << 11)
0037     __hc32          hwTailP;    /* tail of TD list */
0038     __hc32          hwHeadP;    /* head of TD list (hc r/w) */
0039 #define ED_C        (0x02)          /* toggle carry */
0040 #define ED_H        (0x01)          /* halted */
0041     __hc32          hwNextED;   /* next ED in list */
0042 
0043     /* rest are purely for the driver's use */
0044     dma_addr_t      dma;        /* addr of ED */
0045     struct td       *dummy;     /* next TD to activate */
0046 
0047     /* host's view of schedule */
0048     struct ed       *ed_next;   /* on schedule or rm_list */
0049     struct ed       *ed_prev;   /* for non-interrupt EDs */
0050     struct list_head    td_list;    /* "shadow list" of our TDs */
0051     struct list_head    in_use_list;
0052 
0053     /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
0054      * usually:  OPER --> UNLINK --> (IDLE | OPER) --> ...
0055      */
0056     u8          state;      /* ED_{IDLE,UNLINK,OPER} */
0057 #define ED_IDLE     0x00        /* NOT linked to HC */
0058 #define ED_UNLINK   0x01        /* being unlinked from hc */
0059 #define ED_OPER     0x02        /* IS linked to hc */
0060 
0061     u8          type;       /* PIPE_{BULK,...} */
0062 
0063     /* periodic scheduling params (for intr and iso) */
0064     u8          branch;
0065     u16         interval;
0066     u16         load;
0067     u16         last_iso;   /* iso only */
0068 
0069     /* HC may see EDs on rm_list until next frame (frame_no == tick) */
0070     u16         tick;
0071 
0072     /* Detect TDs not added to the done queue */
0073     unsigned        takeback_wdh_cnt;
0074     struct td       *pending_td;
0075 #define OKAY_TO_TAKEBACK(ohci, ed)          \
0076         ((int) (ohci->wdh_cnt - ed->takeback_wdh_cnt) >= 0)
0077 
0078 } __attribute__ ((aligned(16)));
0079 
0080 #define ED_MASK ((u32)~0x0f)        /* strip hw status in low addr bits */
0081 
0082 
0083 /*
0084  * OHCI Transfer Descriptor (TD) ... one per transfer segment
0085  * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
0086  * and 4.3.2 (iso)
0087  */
0088 struct td {
0089     /* first fields are hardware-specified */
0090     __hc32      hwINFO;     /* transfer info bitmask */
0091 
0092     /* hwINFO bits for both general and iso tds: */
0093 #define TD_CC       0xf0000000          /* condition code */
0094 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
0095 //#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
0096 #define TD_DI       0x00E00000          /* frames before interrupt */
0097 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
0098     /* these two bits are available for definition/use by HCDs in both
0099      * general and iso tds ... others are available for only one type
0100      */
0101 #define TD_DONE     0x00020000          /* retired to donelist */
0102 #define TD_ISO      0x00010000          /* copy of ED_ISO */
0103 
0104     /* hwINFO bits for general tds: */
0105 #define TD_EC       0x0C000000          /* error count */
0106 #define TD_T        0x03000000          /* data toggle state */
0107 #define TD_T_DATA0  0x02000000              /* DATA0 */
0108 #define TD_T_DATA1  0x03000000              /* DATA1 */
0109 #define TD_T_TOGGLE 0x00000000              /* uses ED_C */
0110 #define TD_DP       0x00180000          /* direction/pid */
0111 #define TD_DP_SETUP 0x00000000          /* SETUP pid */
0112 #define TD_DP_IN    0x00100000              /* IN pid */
0113 #define TD_DP_OUT   0x00080000              /* OUT pid */
0114                             /* 0x00180000 rsvd */
0115 #define TD_R        0x00040000          /* round: short packets OK? */
0116 
0117     /* (no hwINFO #defines yet for iso tds) */
0118 
0119     __hc32      hwCBP;      /* Current Buffer Pointer (or 0) */
0120     __hc32      hwNextTD;   /* Next TD Pointer */
0121     __hc32      hwBE;       /* Memory Buffer End Pointer */
0122 
0123     /* PSW is only for ISO.  Only 1 PSW entry is used, but on
0124      * big-endian PPC hardware that's the second entry.
0125      */
0126 #define MAXPSW  2
0127     __hc16      hwPSW [MAXPSW];
0128 
0129     /* rest are purely for the driver's use */
0130     __u8        index;
0131     struct ed   *ed;
0132     struct td   *td_hash;   /* dma-->td hashtable */
0133     struct td   *next_dl_td;
0134     struct urb  *urb;
0135 
0136     dma_addr_t  td_dma;     /* addr of this TD */
0137     dma_addr_t  data_dma;   /* addr of data it points to */
0138 
0139     struct list_head td_list;   /* "shadow list", TDs on same ED */
0140 } __attribute__ ((aligned(32)));    /* c/b/i need 16; only iso needs 32 */
0141 
0142 #define TD_MASK ((u32)~0x1f)        /* strip hw status in low addr bits */
0143 
0144 /*
0145  * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW
0146  */
0147 #define TD_CC_NOERROR      0x00
0148 #define TD_CC_CRC          0x01
0149 #define TD_CC_BITSTUFFING  0x02
0150 #define TD_CC_DATATOGGLEM  0x03
0151 #define TD_CC_STALL        0x04
0152 #define TD_DEVNOTRESP      0x05
0153 #define TD_PIDCHECKFAIL    0x06
0154 #define TD_UNEXPECTEDPID   0x07
0155 #define TD_DATAOVERRUN     0x08
0156 #define TD_DATAUNDERRUN    0x09
0157     /* 0x0A, 0x0B reserved for hardware */
0158 #define TD_BUFFEROVERRUN   0x0C
0159 #define TD_BUFFERUNDERRUN  0x0D
0160     /* 0x0E, 0x0F reserved for HCD */
0161 #define TD_NOTACCESSED     0x0F
0162 
0163 
0164 /* map OHCI TD status codes (CC) to errno values */
0165 static const int __maybe_unused cc_to_error [16] = {
0166     /* No  Error  */               0,
0167     /* CRC Error  */               -EILSEQ,
0168     /* Bit Stuff  */               -EPROTO,
0169     /* Data Togg  */               -EILSEQ,
0170     /* Stall      */               -EPIPE,
0171     /* DevNotResp */               -ETIME,
0172     /* PIDCheck   */               -EPROTO,
0173     /* UnExpPID   */               -EPROTO,
0174     /* DataOver   */               -EOVERFLOW,
0175     /* DataUnder  */               -EREMOTEIO,
0176     /* (for hw)   */               -EIO,
0177     /* (for hw)   */               -EIO,
0178     /* BufferOver */               -ECOMM,
0179     /* BuffUnder  */               -ENOSR,
0180     /* (for HCD)  */               -EALREADY,
0181     /* (for HCD)  */               -EALREADY
0182 };
0183 
0184 
0185 /*
0186  * The HCCA (Host Controller Communications Area) is a 256 byte
0187  * structure defined section 4.4.1 of the OHCI spec. The HC is
0188  * told the base address of it.  It must be 256-byte aligned.
0189  */
0190 struct ohci_hcca {
0191 #define NUM_INTS 32
0192     __hc32  int_table [NUM_INTS];   /* periodic schedule */
0193 
0194     /*
0195      * OHCI defines u16 frame_no, followed by u16 zero pad.
0196      * Since some processors can't do 16 bit bus accesses,
0197      * portable access must be a 32 bits wide.
0198      */
0199     __hc32  frame_no;       /* current frame number */
0200     __hc32  done_head;      /* info returned for an interrupt */
0201     u8  reserved_for_hc [116];
0202     u8  what [4];       /* spec only identifies 252 bytes :) */
0203 } __attribute__ ((aligned(256)));
0204 
0205 /*
0206  * This is the structure of the OHCI controller's memory mapped I/O region.
0207  * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
0208  * Layout is in section 7 (and appendix B) of the spec.
0209  */
0210 struct ohci_regs {
0211     /* control and status registers (section 7.1) */
0212     __hc32  revision;
0213     __hc32  control;
0214     __hc32  cmdstatus;
0215     __hc32  intrstatus;
0216     __hc32  intrenable;
0217     __hc32  intrdisable;
0218 
0219     /* memory pointers (section 7.2) */
0220     __hc32  hcca;
0221     __hc32  ed_periodcurrent;
0222     __hc32  ed_controlhead;
0223     __hc32  ed_controlcurrent;
0224     __hc32  ed_bulkhead;
0225     __hc32  ed_bulkcurrent;
0226     __hc32  donehead;
0227 
0228     /* frame counters (section 7.3) */
0229     __hc32  fminterval;
0230     __hc32  fmremaining;
0231     __hc32  fmnumber;
0232     __hc32  periodicstart;
0233     __hc32  lsthresh;
0234 
0235     /* Root hub ports (section 7.4) */
0236     struct  ohci_roothub_regs {
0237         __hc32  a;
0238         __hc32  b;
0239         __hc32  status;
0240 #define MAX_ROOT_PORTS  15  /* maximum OHCI root hub ports (RH_A_NDP) */
0241         __hc32  portstatus [MAX_ROOT_PORTS];
0242     } roothub;
0243 
0244     /* and optional "legacy support" registers (appendix B) at 0x0100 */
0245 
0246 } __attribute__ ((aligned(32)));
0247 
0248 
0249 /* OHCI CONTROL AND STATUS REGISTER MASKS */
0250 
0251 /*
0252  * HcControl (control) register masks
0253  */
0254 #define OHCI_CTRL_CBSR  (3 << 0)    /* control/bulk service ratio */
0255 #define OHCI_CTRL_PLE   (1 << 2)    /* periodic list enable */
0256 #define OHCI_CTRL_IE    (1 << 3)    /* isochronous enable */
0257 #define OHCI_CTRL_CLE   (1 << 4)    /* control list enable */
0258 #define OHCI_CTRL_BLE   (1 << 5)    /* bulk list enable */
0259 #define OHCI_CTRL_HCFS  (3 << 6)    /* host controller functional state */
0260 #define OHCI_CTRL_IR    (1 << 8)    /* interrupt routing */
0261 #define OHCI_CTRL_RWC   (1 << 9)    /* remote wakeup connected */
0262 #define OHCI_CTRL_RWE   (1 << 10)   /* remote wakeup enable */
0263 
0264 /* pre-shifted values for HCFS */
0265 #   define OHCI_USB_RESET   (0 << 6)
0266 #   define OHCI_USB_RESUME  (1 << 6)
0267 #   define OHCI_USB_OPER    (2 << 6)
0268 #   define OHCI_USB_SUSPEND (3 << 6)
0269 
0270 /*
0271  * HcCommandStatus (cmdstatus) register masks
0272  */
0273 #define OHCI_HCR    (1 << 0)    /* host controller reset */
0274 #define OHCI_CLF    (1 << 1)    /* control list filled */
0275 #define OHCI_BLF    (1 << 2)    /* bulk list filled */
0276 #define OHCI_OCR    (1 << 3)    /* ownership change request */
0277 #define OHCI_SOC    (3 << 16)   /* scheduling overrun count */
0278 
0279 /*
0280  * masks used with interrupt registers:
0281  * HcInterruptStatus (intrstatus)
0282  * HcInterruptEnable (intrenable)
0283  * HcInterruptDisable (intrdisable)
0284  */
0285 #define OHCI_INTR_SO    (1 << 0)    /* scheduling overrun */
0286 #define OHCI_INTR_WDH   (1 << 1)    /* writeback of done_head */
0287 #define OHCI_INTR_SF    (1 << 2)    /* start frame */
0288 #define OHCI_INTR_RD    (1 << 3)    /* resume detect */
0289 #define OHCI_INTR_UE    (1 << 4)    /* unrecoverable error */
0290 #define OHCI_INTR_FNO   (1 << 5)    /* frame number overflow */
0291 #define OHCI_INTR_RHSC  (1 << 6)    /* root hub status change */
0292 #define OHCI_INTR_OC    (1 << 30)   /* ownership change */
0293 #define OHCI_INTR_MIE   (1 << 31)   /* master interrupt enable */
0294 
0295 
0296 /* OHCI ROOT HUB REGISTER MASKS */
0297 
0298 /* roothub.portstatus [i] bits */
0299 #define RH_PS_CCS            0x00000001     /* current connect status */
0300 #define RH_PS_PES            0x00000002     /* port enable status*/
0301 #define RH_PS_PSS            0x00000004     /* port suspend status */
0302 #define RH_PS_POCI           0x00000008     /* port over current indicator */
0303 #define RH_PS_PRS            0x00000010     /* port reset status */
0304 #define RH_PS_PPS            0x00000100     /* port power status */
0305 #define RH_PS_LSDA           0x00000200     /* low speed device attached */
0306 #define RH_PS_CSC            0x00010000     /* connect status change */
0307 #define RH_PS_PESC           0x00020000     /* port enable status change */
0308 #define RH_PS_PSSC           0x00040000     /* port suspend status change */
0309 #define RH_PS_OCIC           0x00080000     /* over current indicator change */
0310 #define RH_PS_PRSC           0x00100000     /* port reset status change */
0311 
0312 /* roothub.status bits */
0313 #define RH_HS_LPS        0x00000001     /* local power status */
0314 #define RH_HS_OCI        0x00000002     /* over current indicator */
0315 #define RH_HS_DRWE       0x00008000     /* device remote wakeup enable */
0316 #define RH_HS_LPSC       0x00010000     /* local power status change */
0317 #define RH_HS_OCIC       0x00020000     /* over current indicator change */
0318 #define RH_HS_CRWE       0x80000000     /* clear remote wakeup enable */
0319 
0320 /* roothub.b masks */
0321 #define RH_B_DR     0x0000ffff      /* device removable flags */
0322 #define RH_B_PPCM   0xffff0000      /* port power control mask */
0323 
0324 /* roothub.a masks */
0325 #define RH_A_NDP    (0xff << 0)     /* number of downstream ports */
0326 #define RH_A_PSM    (1 << 8)        /* power switching mode */
0327 #define RH_A_NPS    (1 << 9)        /* no power switching */
0328 #define RH_A_DT     (1 << 10)       /* device type (mbz) */
0329 #define RH_A_OCPM   (1 << 11)       /* over current protection mode */
0330 #define RH_A_NOCP   (1 << 12)       /* no over current protection */
0331 #define RH_A_POTPGT (0xff << 24)        /* power on to power good time */
0332 
0333 
0334 /* hcd-private per-urb state */
0335 typedef struct urb_priv {
0336     struct ed       *ed;
0337     u16         length;     // # tds in this request
0338     u16         td_cnt;     // tds already serviced
0339     struct list_head    pending;
0340     struct td       *td[];      // all TDs in this request
0341 
0342 } urb_priv_t;
0343 
0344 #define TD_HASH_SIZE    64    /* power'o'two */
0345 // sizeof (struct td) ~= 64 == 2^6 ...
0346 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
0347 
0348 
0349 /*
0350  * This is the full ohci controller description
0351  *
0352  * Note how the "proper" USB information is just
0353  * a subset of what the full implementation needs. (Linus)
0354  */
0355 
0356 enum ohci_rh_state {
0357     OHCI_RH_HALTED,
0358     OHCI_RH_SUSPENDED,
0359     OHCI_RH_RUNNING
0360 };
0361 
0362 struct ohci_hcd {
0363     spinlock_t      lock;
0364 
0365     /*
0366      * I/O memory used to communicate with the HC (dma-consistent)
0367      */
0368     struct ohci_regs __iomem *regs;
0369 
0370     /*
0371      * main memory used to communicate with the HC (dma-consistent).
0372      * hcd adds to schedule for a live hc any time, but removals finish
0373      * only at the start of the next frame.
0374      */
0375     struct ohci_hcca    *hcca;
0376     dma_addr_t      hcca_dma;
0377 
0378     struct ed       *ed_rm_list;        /* to be removed */
0379 
0380     struct ed       *ed_bulktail;       /* last in bulk list */
0381     struct ed       *ed_controltail;    /* last in ctrl list */
0382     struct ed       *periodic [NUM_INTS];   /* shadow int_table */
0383 
0384     void (*start_hnp)(struct ohci_hcd *ohci);
0385 
0386     /*
0387      * memory management for queue data structures
0388      *
0389      * @td_cache and @ed_cache are %NULL if &usb_hcd.localmem_pool is used.
0390      */
0391     struct dma_pool     *td_cache;
0392     struct dma_pool     *ed_cache;
0393     struct td       *td_hash [TD_HASH_SIZE];
0394     struct td       *dl_start, *dl_end; /* the done list */
0395     struct list_head    pending;
0396     struct list_head    eds_in_use; /* all EDs with at least 1 TD */
0397 
0398     /*
0399      * driver state
0400      */
0401     enum ohci_rh_state  rh_state;
0402     int         num_ports;
0403     int         load [NUM_INTS];
0404     u32         hc_control; /* copy of hc control reg */
0405     unsigned long       next_statechange;   /* suspend/resume */
0406     u32         fminterval;     /* saved register */
0407     unsigned        autostop:1; /* rh auto stopping/stopped */
0408     unsigned        working:1;
0409     unsigned        restart_work:1;
0410 
0411     unsigned long       flags;      /* for HC bugs */
0412 #define OHCI_QUIRK_AMD756   0x01            /* erratum #4 */
0413 #define OHCI_QUIRK_SUPERIO  0x02            /* natsemi */
0414 #define OHCI_QUIRK_INITRESET    0x04            /* SiS, OPTi, ... */
0415 #define OHCI_QUIRK_BE_DESC  0x08            /* BE descriptors */
0416 #define OHCI_QUIRK_BE_MMIO  0x10            /* BE registers */
0417 #define OHCI_QUIRK_ZFMICRO  0x20            /* Compaq ZFMicro chipset*/
0418 #define OHCI_QUIRK_NEC      0x40            /* lost interrupts */
0419 #define OHCI_QUIRK_FRAME_NO 0x80            /* no big endian frame_no shift */
0420 #define OHCI_QUIRK_HUB_POWER    0x100           /* distrust firmware power/oc setup */
0421 #define OHCI_QUIRK_AMD_PLL  0x200           /* AMD PLL quirk*/
0422 #define OHCI_QUIRK_AMD_PREFETCH 0x400           /* pre-fetch for ISO transfer */
0423 #define OHCI_QUIRK_GLOBAL_SUSPEND   0x800       /* must suspend ports */
0424 #define OHCI_QUIRK_QEMU     0x1000          /* relax timing expectations */
0425 
0426     // there are also chip quirks/bugs in init logic
0427 
0428     unsigned        prev_frame_no;
0429     unsigned        wdh_cnt, prev_wdh_cnt;
0430     u32         prev_donehead;
0431     struct timer_list   io_watchdog;
0432 
0433     struct work_struct  nec_work;   /* Worker for NEC quirk */
0434 
0435     struct dentry       *debug_dir;
0436 
0437     /* platform-specific data -- must come last */
0438     unsigned long           priv[] __aligned(sizeof(s64));
0439 
0440 };
0441 
0442 #ifdef CONFIG_USB_PCI
0443 static inline int quirk_nec(struct ohci_hcd *ohci)
0444 {
0445     return ohci->flags & OHCI_QUIRK_NEC;
0446 }
0447 static inline int quirk_zfmicro(struct ohci_hcd *ohci)
0448 {
0449     return ohci->flags & OHCI_QUIRK_ZFMICRO;
0450 }
0451 static inline int quirk_amdiso(struct ohci_hcd *ohci)
0452 {
0453     return ohci->flags & OHCI_QUIRK_AMD_PLL;
0454 }
0455 static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
0456 {
0457     return ohci->flags & OHCI_QUIRK_AMD_PREFETCH;
0458 }
0459 #else
0460 static inline int quirk_nec(struct ohci_hcd *ohci)
0461 {
0462     return 0;
0463 }
0464 static inline int quirk_zfmicro(struct ohci_hcd *ohci)
0465 {
0466     return 0;
0467 }
0468 static inline int quirk_amdiso(struct ohci_hcd *ohci)
0469 {
0470     return 0;
0471 }
0472 static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
0473 {
0474     return 0;
0475 }
0476 #endif
0477 
0478 /* convert between an hcd pointer and the corresponding ohci_hcd */
0479 static inline struct ohci_hcd *hcd_to_ohci (struct usb_hcd *hcd)
0480 {
0481     return (struct ohci_hcd *) (hcd->hcd_priv);
0482 }
0483 static inline struct usb_hcd *ohci_to_hcd (const struct ohci_hcd *ohci)
0484 {
0485     return container_of ((void *) ohci, struct usb_hcd, hcd_priv);
0486 }
0487 
0488 /*-------------------------------------------------------------------------*/
0489 
0490 #define ohci_dbg(ohci, fmt, args...) \
0491     dev_dbg (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
0492 #define ohci_err(ohci, fmt, args...) \
0493     dev_err (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
0494 #define ohci_info(ohci, fmt, args...) \
0495     dev_info (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
0496 #define ohci_warn(ohci, fmt, args...) \
0497     dev_warn (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
0498 
0499 /*-------------------------------------------------------------------------*/
0500 
0501 /*
0502  * While most USB host controllers implement their registers and
0503  * in-memory communication descriptors in little-endian format,
0504  * a minority (notably the IBM STB04XXX and the Motorola MPC5200
0505  * processors) implement them in big endian format.
0506  *
0507  * In addition some more exotic implementations like the Toshiba
0508  * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
0509  * they have a different endianness for registers vs. in-memory
0510  * descriptors.
0511  *
0512  * This attempts to support either format at compile time without a
0513  * runtime penalty, or both formats with the additional overhead
0514  * of checking a flag bit.
0515  *
0516  * That leads to some tricky Kconfig rules howevber. There are
0517  * different defaults based on some arch/ppc platforms, though
0518  * the basic rules are:
0519  *
0520  * Controller type              Kconfig options needed
0521  * ---------------              ----------------------
0522  * little endian                CONFIG_USB_OHCI_LITTLE_ENDIAN
0523  *
0524  * fully big endian             CONFIG_USB_OHCI_BIG_ENDIAN_DESC _and_
0525  *                              CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
0526  *
0527  * mixed endian                 CONFIG_USB_OHCI_LITTLE_ENDIAN _and_
0528  *                              CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
0529  *
0530  * (If you have a mixed endian controller, you -must- also define
0531  * CONFIG_USB_OHCI_LITTLE_ENDIAN or things will not work when building
0532  * both your mixed endian and a fully big endian controller support in
0533  * the same kernel image).
0534  */
0535 
0536 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_DESC
0537 #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN
0538 #define big_endian_desc(ohci)   (ohci->flags & OHCI_QUIRK_BE_DESC)
0539 #else
0540 #define big_endian_desc(ohci)   1       /* only big endian */
0541 #endif
0542 #else
0543 #define big_endian_desc(ohci)   0       /* only little endian */
0544 #endif
0545 
0546 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
0547 #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN
0548 #define big_endian_mmio(ohci)   (ohci->flags & OHCI_QUIRK_BE_MMIO)
0549 #else
0550 #define big_endian_mmio(ohci)   1       /* only big endian */
0551 #endif
0552 #else
0553 #define big_endian_mmio(ohci)   0       /* only little endian */
0554 #endif
0555 
0556 /*
0557  * Big-endian read/write functions are arch-specific.
0558  * Other arches can be added if/when they're needed.
0559  *
0560  */
0561 static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci,
0562                     __hc32 __iomem * regs)
0563 {
0564 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
0565     return big_endian_mmio(ohci) ?
0566         readl_be (regs) :
0567         readl (regs);
0568 #else
0569     return readl (regs);
0570 #endif
0571 }
0572 
0573 static inline void _ohci_writel (const struct ohci_hcd *ohci,
0574                  const unsigned int val, __hc32 __iomem *regs)
0575 {
0576 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
0577     big_endian_mmio(ohci) ?
0578         writel_be (val, regs) :
0579         writel (val, regs);
0580 #else
0581         writel (val, regs);
0582 #endif
0583 }
0584 
0585 #define ohci_readl(o,r)     _ohci_readl(o,r)
0586 #define ohci_writel(o,v,r)  _ohci_writel(o,v,r)
0587 
0588 
0589 /*-------------------------------------------------------------------------*/
0590 
0591 /* cpu to ohci */
0592 static inline __hc16 cpu_to_hc16 (const struct ohci_hcd *ohci, const u16 x)
0593 {
0594     return big_endian_desc(ohci) ?
0595         (__force __hc16)cpu_to_be16(x) :
0596         (__force __hc16)cpu_to_le16(x);
0597 }
0598 
0599 static inline __hc16 cpu_to_hc16p (const struct ohci_hcd *ohci, const u16 *x)
0600 {
0601     return big_endian_desc(ohci) ?
0602         cpu_to_be16p(x) :
0603         cpu_to_le16p(x);
0604 }
0605 
0606 static inline __hc32 cpu_to_hc32 (const struct ohci_hcd *ohci, const u32 x)
0607 {
0608     return big_endian_desc(ohci) ?
0609         (__force __hc32)cpu_to_be32(x) :
0610         (__force __hc32)cpu_to_le32(x);
0611 }
0612 
0613 static inline __hc32 cpu_to_hc32p (const struct ohci_hcd *ohci, const u32 *x)
0614 {
0615     return big_endian_desc(ohci) ?
0616         cpu_to_be32p(x) :
0617         cpu_to_le32p(x);
0618 }
0619 
0620 /* ohci to cpu */
0621 static inline u16 hc16_to_cpu (const struct ohci_hcd *ohci, const __hc16 x)
0622 {
0623     return big_endian_desc(ohci) ?
0624         be16_to_cpu((__force __be16)x) :
0625         le16_to_cpu((__force __le16)x);
0626 }
0627 
0628 static inline u16 hc16_to_cpup (const struct ohci_hcd *ohci, const __hc16 *x)
0629 {
0630     return big_endian_desc(ohci) ?
0631         be16_to_cpup((__force __be16 *)x) :
0632         le16_to_cpup((__force __le16 *)x);
0633 }
0634 
0635 static inline u32 hc32_to_cpu (const struct ohci_hcd *ohci, const __hc32 x)
0636 {
0637     return big_endian_desc(ohci) ?
0638         be32_to_cpu((__force __be32)x) :
0639         le32_to_cpu((__force __le32)x);
0640 }
0641 
0642 static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x)
0643 {
0644     return big_endian_desc(ohci) ?
0645         be32_to_cpup((__force __be32 *)x) :
0646         le32_to_cpup((__force __le32 *)x);
0647 }
0648 
0649 /*-------------------------------------------------------------------------*/
0650 
0651 /*
0652  * The HCCA frame number is 16 bits, but is accessed as 32 bits since not all
0653  * hardware handles 16 bit reads.  Depending on the SoC implementation, the
0654  * frame number can wind up in either bits [31:16] (default) or
0655  * [15:0] (OHCI_QUIRK_FRAME_NO) on big endian hosts.
0656  *
0657  * Somewhat similarly, the 16-bit PSW fields in a transfer descriptor are
0658  * reordered on BE.
0659  */
0660 
0661 static inline u16 ohci_frame_no(const struct ohci_hcd *ohci)
0662 {
0663     u32 tmp;
0664     if (big_endian_desc(ohci)) {
0665         tmp = be32_to_cpup((__force __be32 *)&ohci->hcca->frame_no);
0666         if (!(ohci->flags & OHCI_QUIRK_FRAME_NO))
0667             tmp >>= 16;
0668     } else
0669         tmp = le32_to_cpup((__force __le32 *)&ohci->hcca->frame_no);
0670 
0671     return (u16)tmp;
0672 }
0673 
0674 static inline __hc16 *ohci_hwPSWp(const struct ohci_hcd *ohci,
0675                                  const struct td *td, int index)
0676 {
0677     return (__hc16 *)(big_endian_desc(ohci) ?
0678             &td->hwPSW[index ^ 1] : &td->hwPSW[index]);
0679 }
0680 
0681 static inline u16 ohci_hwPSW(const struct ohci_hcd *ohci,
0682                                const struct td *td, int index)
0683 {
0684     return hc16_to_cpup(ohci, ohci_hwPSWp(ohci, td, index));
0685 }
0686 
0687 /*-------------------------------------------------------------------------*/
0688 
0689 #define FI          0x2edf      /* 12000 bits per frame (-1) */
0690 #define FSMP(fi)        (0x7fff & ((6 * ((fi) - 210)) / 7))
0691 #define FIT         (1 << 31)
0692 #define LSTHRESH        0x628       /* lowspeed bit threshold */
0693 
0694 static inline void periodic_reinit (struct ohci_hcd *ohci)
0695 {
0696     u32 fi = ohci->fminterval & 0x03fff;
0697     u32 fit = ohci_readl(ohci, &ohci->regs->fminterval) & FIT;
0698 
0699     ohci_writel (ohci, (fit ^ FIT) | ohci->fminterval,
0700                         &ohci->regs->fminterval);
0701     ohci_writel (ohci, ((9 * fi) / 10) & 0x3fff,
0702                         &ohci->regs->periodicstart);
0703 }
0704 
0705 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
0706  * The erratum (#4) description is incorrect.  AMD's workaround waits
0707  * till some bits (mostly reserved) are clear; ok for all revs.
0708  */
0709 #define read_roothub(hc, register, mask) ({ \
0710     u32 temp = ohci_readl (hc, &hc->regs->roothub.register); \
0711     if (temp == -1) \
0712         hc->rh_state = OHCI_RH_HALTED; \
0713     else if (hc->flags & OHCI_QUIRK_AMD756) \
0714         while (temp & mask) \
0715             temp = ohci_readl (hc, &hc->regs->roothub.register); \
0716     temp; })
0717 
0718 static inline u32 roothub_a (struct ohci_hcd *hc)
0719     { return read_roothub (hc, a, 0xfc0fe000); }
0720 static inline u32 roothub_b (struct ohci_hcd *hc)
0721     { return ohci_readl (hc, &hc->regs->roothub.b); }
0722 static inline u32 roothub_status (struct ohci_hcd *hc)
0723     { return ohci_readl (hc, &hc->regs->roothub.status); }
0724 static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i)
0725     { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
0726 
0727 /* Declarations of things exported for use by ohci platform drivers */
0728 
0729 struct ohci_driver_overrides {
0730     const char  *product_desc;
0731     size_t      extra_priv_size;
0732     int     (*reset)(struct usb_hcd *hcd);
0733 };
0734 
0735 extern void ohci_init_driver(struct hc_driver *drv,
0736                 const struct ohci_driver_overrides *over);
0737 extern int  ohci_restart(struct ohci_hcd *ohci);
0738 extern int  ohci_setup(struct usb_hcd *hcd);
0739 extern int  ohci_suspend(struct usb_hcd *hcd, bool do_wakeup);
0740 extern int  ohci_resume(struct usb_hcd *hcd, bool hibernated);
0741 extern int  ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
0742                  u16 wIndex, char *buf, u16 wLength);
0743 extern int  ohci_hub_status_data(struct usb_hcd *hcd, char *buf);
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