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0001 // SPDX-License-Identifier: GPL-1.0+
0002 /*
0003  * OHCI HCD (Host Controller Driver) for USB.
0004  *
0005  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
0006  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
0007  * (C) Copyright 2002 Hewlett-Packard Company
0008  *
0009  * Bus Glue for pxa27x
0010  *
0011  * Written by Christopher Hoover <ch@hpl.hp.com>
0012  * Based on fragments of previous driver by Russell King et al.
0013  *
0014  * Modified for LH7A404 from ohci-sa1111.c
0015  *  by Durgesh Pattamatta <pattamattad@sharpsec.com>
0016  *
0017  * Modified for pxa27x from ohci-lh7a404.c
0018  *  by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
0019  *
0020  * This file is licenced under the GPL.
0021  */
0022 
0023 #include <linux/clk.h>
0024 #include <linux/device.h>
0025 #include <linux/dma-mapping.h>
0026 #include <linux/io.h>
0027 #include <linux/kernel.h>
0028 #include <linux/module.h>
0029 #include <linux/of_platform.h>
0030 #include <linux/of_gpio.h>
0031 #include <linux/platform_data/usb-ohci-pxa27x.h>
0032 #include <linux/platform_data/usb-pxa3xx-ulpi.h>
0033 #include <linux/platform_device.h>
0034 #include <linux/regulator/consumer.h>
0035 #include <linux/signal.h>
0036 #include <linux/usb.h>
0037 #include <linux/usb/hcd.h>
0038 #include <linux/usb/otg.h>
0039 #include <linux/soc/pxa/cpu.h>
0040 
0041 #include "ohci.h"
0042 
0043 #define DRIVER_DESC "OHCI PXA27x/PXA3x driver"
0044 
0045 /*
0046  * UHC: USB Host Controller (OHCI-like) register definitions
0047  */
0048 #define UHCREV      (0x0000) /* UHC HCI Spec Revision */
0049 #define UHCHCON     (0x0004) /* UHC Host Control Register */
0050 #define UHCCOMS     (0x0008) /* UHC Command Status Register */
0051 #define UHCINTS     (0x000C) /* UHC Interrupt Status Register */
0052 #define UHCINTE     (0x0010) /* UHC Interrupt Enable */
0053 #define UHCINTD     (0x0014) /* UHC Interrupt Disable */
0054 #define UHCHCCA     (0x0018) /* UHC Host Controller Comm. Area */
0055 #define UHCPCED     (0x001C) /* UHC Period Current Endpt Descr */
0056 #define UHCCHED     (0x0020) /* UHC Control Head Endpt Descr */
0057 #define UHCCCED     (0x0024) /* UHC Control Current Endpt Descr */
0058 #define UHCBHED     (0x0028) /* UHC Bulk Head Endpt Descr */
0059 #define UHCBCED     (0x002C) /* UHC Bulk Current Endpt Descr */
0060 #define UHCDHEAD    (0x0030) /* UHC Done Head */
0061 #define UHCFMI      (0x0034) /* UHC Frame Interval */
0062 #define UHCFMR      (0x0038) /* UHC Frame Remaining */
0063 #define UHCFMN      (0x003C) /* UHC Frame Number */
0064 #define UHCPERS     (0x0040) /* UHC Periodic Start */
0065 #define UHCLS       (0x0044) /* UHC Low Speed Threshold */
0066 
0067 #define UHCRHDA     (0x0048) /* UHC Root Hub Descriptor A */
0068 #define UHCRHDA_NOCP    (1 << 12)   /* No over current protection */
0069 #define UHCRHDA_OCPM    (1 << 11)   /* Over Current Protection Mode */
0070 #define UHCRHDA_POTPGT(x) \
0071             (((x) & 0xff) << 24) /* Power On To Power Good Time */
0072 
0073 #define UHCRHDB     (0x004C) /* UHC Root Hub Descriptor B */
0074 #define UHCRHS      (0x0050) /* UHC Root Hub Status */
0075 #define UHCRHPS1    (0x0054) /* UHC Root Hub Port 1 Status */
0076 #define UHCRHPS2    (0x0058) /* UHC Root Hub Port 2 Status */
0077 #define UHCRHPS3    (0x005C) /* UHC Root Hub Port 3 Status */
0078 
0079 #define UHCSTAT     (0x0060) /* UHC Status Register */
0080 #define UHCSTAT_UPS3    (1 << 16)   /* USB Power Sense Port3 */
0081 #define UHCSTAT_SBMAI   (1 << 15)   /* System Bus Master Abort Interrupt*/
0082 #define UHCSTAT_SBTAI   (1 << 14)   /* System Bus Target Abort Interrupt*/
0083 #define UHCSTAT_UPRI    (1 << 13)   /* USB Port Resume Interrupt */
0084 #define UHCSTAT_UPS2    (1 << 12)   /* USB Power Sense Port 2 */
0085 #define UHCSTAT_UPS1    (1 << 11)   /* USB Power Sense Port 1 */
0086 #define UHCSTAT_HTA (1 << 10)   /* HCI Target Abort */
0087 #define UHCSTAT_HBA (1 << 8)    /* HCI Buffer Active */
0088 #define UHCSTAT_RWUE    (1 << 7)    /* HCI Remote Wake Up Event */
0089 
0090 #define UHCHR           (0x0064) /* UHC Reset Register */
0091 #define UHCHR_SSEP3 (1 << 11)   /* Sleep Standby Enable for Port3 */
0092 #define UHCHR_SSEP2 (1 << 10)   /* Sleep Standby Enable for Port2 */
0093 #define UHCHR_SSEP1 (1 << 9)    /* Sleep Standby Enable for Port1 */
0094 #define UHCHR_PCPL  (1 << 7)    /* Power control polarity low */
0095 #define UHCHR_PSPL  (1 << 6)    /* Power sense polarity low */
0096 #define UHCHR_SSE   (1 << 5)    /* Sleep Standby Enable */
0097 #define UHCHR_UIT   (1 << 4)    /* USB Interrupt Test */
0098 #define UHCHR_SSDC  (1 << 3)    /* Simulation Scale Down Clock */
0099 #define UHCHR_CGR   (1 << 2)    /* Clock Generation Reset */
0100 #define UHCHR_FHR   (1 << 1)    /* Force Host Controller Reset */
0101 #define UHCHR_FSBIR (1 << 0)    /* Force System Bus Iface Reset */
0102 
0103 #define UHCHIE          (0x0068) /* UHC Interrupt Enable Register*/
0104 #define UHCHIE_UPS3IE   (1 << 14)   /* Power Sense Port3 IntEn */
0105 #define UHCHIE_UPRIE    (1 << 13)   /* Port Resume IntEn */
0106 #define UHCHIE_UPS2IE   (1 << 12)   /* Power Sense Port2 IntEn */
0107 #define UHCHIE_UPS1IE   (1 << 11)   /* Power Sense Port1 IntEn */
0108 #define UHCHIE_TAIE (1 << 10)   /* HCI Interface Transfer Abort
0109                        Interrupt Enable*/
0110 #define UHCHIE_HBAIE    (1 << 8)    /* HCI Buffer Active IntEn */
0111 #define UHCHIE_RWIE (1 << 7)    /* Remote Wake-up IntEn */
0112 
0113 #define UHCHIT          (0x006C) /* UHC Interrupt Test register */
0114 
0115 #define PXA_UHC_MAX_PORTNUM    3
0116 
0117 static const char hcd_name[] = "ohci-pxa27x";
0118 
0119 static struct hc_driver __read_mostly ohci_pxa27x_hc_driver;
0120 
0121 struct pxa27x_ohci {
0122     struct clk  *clk;
0123     void __iomem    *mmio_base;
0124     struct regulator *vbus[3];
0125     bool        vbus_enabled[3];
0126 };
0127 
0128 #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv)
0129 
0130 /*
0131   PMM_NPS_MODE -- PMM Non-power switching mode
0132       Ports are powered continuously.
0133 
0134   PMM_GLOBAL_MODE -- PMM global switching mode
0135       All ports are powered at the same time.
0136 
0137   PMM_PERPORT_MODE -- PMM per port switching mode
0138       Ports are powered individually.
0139  */
0140 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode)
0141 {
0142     uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
0143     uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
0144 
0145     switch (mode) {
0146     case PMM_NPS_MODE:
0147         uhcrhda |= RH_A_NPS;
0148         break;
0149     case PMM_GLOBAL_MODE:
0150         uhcrhda &= ~(RH_A_NPS | RH_A_PSM);
0151         break;
0152     case PMM_PERPORT_MODE:
0153         uhcrhda &= ~(RH_A_NPS);
0154         uhcrhda |= RH_A_PSM;
0155 
0156         /* Set port power control mask bits, only 3 ports. */
0157         uhcrhdb |= (0x7<<17);
0158         break;
0159     default:
0160         printk( KERN_ERR
0161             "Invalid mode %d, set to non-power switch mode.\n",
0162             mode );
0163 
0164         uhcrhda |= RH_A_NPS;
0165     }
0166 
0167     __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
0168     __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
0169     return 0;
0170 }
0171 
0172 static int pxa27x_ohci_set_vbus_power(struct pxa27x_ohci *pxa_ohci,
0173                       unsigned int port, bool enable)
0174 {
0175     struct regulator *vbus = pxa_ohci->vbus[port];
0176     int ret = 0;
0177 
0178     if (IS_ERR_OR_NULL(vbus))
0179         return 0;
0180 
0181     if (enable && !pxa_ohci->vbus_enabled[port])
0182         ret = regulator_enable(vbus);
0183     else if (!enable && pxa_ohci->vbus_enabled[port])
0184         ret = regulator_disable(vbus);
0185 
0186     if (ret < 0)
0187         return ret;
0188 
0189     pxa_ohci->vbus_enabled[port] = enable;
0190 
0191     return 0;
0192 }
0193 
0194 static int pxa27x_ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
0195                    u16 wIndex, char *buf, u16 wLength)
0196 {
0197     struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
0198     int ret;
0199 
0200     switch (typeReq) {
0201     case SetPortFeature:
0202     case ClearPortFeature:
0203         if (!wIndex || wIndex > 3)
0204             return -EPIPE;
0205 
0206         if (wValue != USB_PORT_FEAT_POWER)
0207             break;
0208 
0209         ret = pxa27x_ohci_set_vbus_power(pxa_ohci, wIndex - 1,
0210                          typeReq == SetPortFeature);
0211         if (ret)
0212             return ret;
0213         break;
0214     }
0215 
0216     return ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
0217 }
0218 /*-------------------------------------------------------------------------*/
0219 
0220 static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci,
0221                    struct pxaohci_platform_data *inf)
0222 {
0223     uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
0224     uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
0225 
0226     if (inf->flags & ENABLE_PORT1)
0227         uhchr &= ~UHCHR_SSEP1;
0228 
0229     if (inf->flags & ENABLE_PORT2)
0230         uhchr &= ~UHCHR_SSEP2;
0231 
0232     if (inf->flags & ENABLE_PORT3)
0233         uhchr &= ~UHCHR_SSEP3;
0234 
0235     if (inf->flags & POWER_CONTROL_LOW)
0236         uhchr |= UHCHR_PCPL;
0237 
0238     if (inf->flags & POWER_SENSE_LOW)
0239         uhchr |= UHCHR_PSPL;
0240 
0241     if (inf->flags & NO_OC_PROTECTION)
0242         uhcrhda |= UHCRHDA_NOCP;
0243     else
0244         uhcrhda &= ~UHCRHDA_NOCP;
0245 
0246     if (inf->flags & OC_MODE_PERPORT)
0247         uhcrhda |= UHCRHDA_OCPM;
0248     else
0249         uhcrhda &= ~UHCRHDA_OCPM;
0250 
0251     if (inf->power_on_delay) {
0252         uhcrhda &= ~UHCRHDA_POTPGT(0xff);
0253         uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
0254     }
0255 
0256     __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
0257     __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
0258 }
0259 
0260 static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci)
0261 {
0262     uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
0263 
0264     __raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
0265     udelay(11);
0266     __raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
0267 }
0268 
0269 #ifdef CONFIG_PXA27x
0270 extern void pxa27x_clear_otgph(void);
0271 #else
0272 #define pxa27x_clear_otgph()    do {} while (0)
0273 #endif
0274 
0275 static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
0276 {
0277     int retval;
0278     struct pxaohci_platform_data *inf;
0279     uint32_t uhchr;
0280     struct usb_hcd *hcd = dev_get_drvdata(dev);
0281 
0282     inf = dev_get_platdata(dev);
0283 
0284     retval = clk_prepare_enable(pxa_ohci->clk);
0285     if (retval)
0286         return retval;
0287 
0288     pxa27x_reset_hc(pxa_ohci);
0289 
0290     uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
0291     __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
0292 
0293     while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
0294         cpu_relax();
0295 
0296     pxa27x_setup_hc(pxa_ohci, inf);
0297 
0298     if (inf->init)
0299         retval = inf->init(dev);
0300 
0301     if (retval < 0) {
0302         clk_disable_unprepare(pxa_ohci->clk);
0303         return retval;
0304     }
0305 
0306     if (cpu_is_pxa3xx())
0307         pxa3xx_u2d_start_hc(&hcd->self);
0308 
0309     uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
0310     __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
0311     __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
0312 
0313     /* Clear any OTG Pin Hold */
0314     pxa27x_clear_otgph();
0315     return 0;
0316 }
0317 
0318 static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
0319 {
0320     struct pxaohci_platform_data *inf;
0321     struct usb_hcd *hcd = dev_get_drvdata(dev);
0322     uint32_t uhccoms;
0323 
0324     inf = dev_get_platdata(dev);
0325 
0326     if (cpu_is_pxa3xx())
0327         pxa3xx_u2d_stop_hc(&hcd->self);
0328 
0329     if (inf->exit)
0330         inf->exit(dev);
0331 
0332     pxa27x_reset_hc(pxa_ohci);
0333 
0334     /* Host Controller Reset */
0335     uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;
0336     __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
0337     udelay(10);
0338 
0339     clk_disable_unprepare(pxa_ohci->clk);
0340 }
0341 
0342 #ifdef CONFIG_OF
0343 static const struct of_device_id pxa_ohci_dt_ids[] = {
0344     { .compatible = "marvell,pxa-ohci" },
0345     { }
0346 };
0347 
0348 MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);
0349 
0350 static int ohci_pxa_of_init(struct platform_device *pdev)
0351 {
0352     struct device_node *np = pdev->dev.of_node;
0353     struct pxaohci_platform_data *pdata;
0354     u32 tmp;
0355     int ret;
0356 
0357     if (!np)
0358         return 0;
0359 
0360     /* Right now device-tree probed devices don't get dma_mask set.
0361      * Since shared usb code relies on it, set it here for now.
0362      * Once we have dma capability bindings this can go away.
0363      */
0364     ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
0365     if (ret)
0366         return ret;
0367 
0368     pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
0369     if (!pdata)
0370         return -ENOMEM;
0371 
0372     if (of_property_read_bool(np, "marvell,enable-port1"))
0373         pdata->flags |= ENABLE_PORT1;
0374     if (of_property_read_bool(np, "marvell,enable-port2"))
0375         pdata->flags |= ENABLE_PORT2;
0376     if (of_property_read_bool(np, "marvell,enable-port3"))
0377         pdata->flags |= ENABLE_PORT3;
0378     if (of_property_read_bool(np, "marvell,port-sense-low"))
0379         pdata->flags |= POWER_SENSE_LOW;
0380     if (of_property_read_bool(np, "marvell,power-control-low"))
0381         pdata->flags |= POWER_CONTROL_LOW;
0382     if (of_property_read_bool(np, "marvell,no-oc-protection"))
0383         pdata->flags |= NO_OC_PROTECTION;
0384     if (of_property_read_bool(np, "marvell,oc-mode-perport"))
0385         pdata->flags |= OC_MODE_PERPORT;
0386     if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
0387         pdata->power_on_delay = tmp;
0388     if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
0389         pdata->port_mode = tmp;
0390     if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
0391         pdata->power_budget = tmp;
0392 
0393     pdev->dev.platform_data = pdata;
0394 
0395     return 0;
0396 }
0397 #else
0398 static int ohci_pxa_of_init(struct platform_device *pdev)
0399 {
0400     return 0;
0401 }
0402 #endif
0403 
0404 /*-------------------------------------------------------------------------*/
0405 
0406 /* configure so an HC device and id are always provided */
0407 /* always called with process context; sleeping is OK */
0408 
0409 
0410 /**
0411  * ohci_hcd_pxa27x_probe - initialize pxa27x-based HCDs
0412  * @pdev:   USB Host controller to probe
0413  *
0414  * Context: task context, might sleep
0415  *
0416  * Allocates basic resources for this USB host controller, and
0417  * then invokes the start() method for the HCD associated with it
0418  * through the hotplug entry's driver_data.
0419  */
0420 static int ohci_hcd_pxa27x_probe(struct platform_device *pdev)
0421 {
0422     int retval, irq;
0423     struct usb_hcd *hcd;
0424     struct pxaohci_platform_data *inf;
0425     struct pxa27x_ohci *pxa_ohci;
0426     struct ohci_hcd *ohci;
0427     struct resource *r;
0428     struct clk *usb_clk;
0429     unsigned int i;
0430 
0431     retval = ohci_pxa_of_init(pdev);
0432     if (retval)
0433         return retval;
0434 
0435     inf = dev_get_platdata(&pdev->dev);
0436 
0437     if (!inf)
0438         return -ENODEV;
0439 
0440     irq = platform_get_irq(pdev, 0);
0441     if (irq < 0) {
0442         pr_err("no resource of IORESOURCE_IRQ");
0443         return irq;
0444     }
0445 
0446     usb_clk = devm_clk_get(&pdev->dev, NULL);
0447     if (IS_ERR(usb_clk))
0448         return PTR_ERR(usb_clk);
0449 
0450     hcd = usb_create_hcd(&ohci_pxa27x_hc_driver, &pdev->dev, "pxa27x");
0451     if (!hcd)
0452         return -ENOMEM;
0453 
0454     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0455     hcd->regs = devm_ioremap_resource(&pdev->dev, r);
0456     if (IS_ERR(hcd->regs)) {
0457         retval = PTR_ERR(hcd->regs);
0458         goto err;
0459     }
0460     hcd->rsrc_start = r->start;
0461     hcd->rsrc_len = resource_size(r);
0462 
0463     /* initialize "struct pxa27x_ohci" */
0464     pxa_ohci = to_pxa27x_ohci(hcd);
0465     pxa_ohci->clk = usb_clk;
0466     pxa_ohci->mmio_base = (void __iomem *)hcd->regs;
0467 
0468     for (i = 0; i < 3; ++i) {
0469         char name[6];
0470 
0471         if (!(inf->flags & (ENABLE_PORT1 << i)))
0472             continue;
0473 
0474         sprintf(name, "vbus%u", i + 1);
0475         pxa_ohci->vbus[i] = devm_regulator_get(&pdev->dev, name);
0476     }
0477 
0478     retval = pxa27x_start_hc(pxa_ohci, &pdev->dev);
0479     if (retval < 0) {
0480         pr_debug("pxa27x_start_hc failed");
0481         goto err;
0482     }
0483 
0484     /* Select Power Management Mode */
0485     pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
0486 
0487     if (inf->power_budget)
0488         hcd->power_budget = inf->power_budget;
0489 
0490     /* The value of NDP in roothub_a is incorrect on this hardware */
0491     ohci = hcd_to_ohci(hcd);
0492     ohci->num_ports = 3;
0493 
0494     retval = usb_add_hcd(hcd, irq, 0);
0495     if (retval == 0) {
0496         device_wakeup_enable(hcd->self.controller);
0497         return retval;
0498     }
0499 
0500     pxa27x_stop_hc(pxa_ohci, &pdev->dev);
0501  err:
0502     usb_put_hcd(hcd);
0503     return retval;
0504 }
0505 
0506 
0507 /* may be called without controller electrically present */
0508 /* may be called with controller, bus, and devices active */
0509 
0510 /**
0511  * ohci_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
0512  * @pdev: USB Host Controller being removed
0513  *
0514  * Context: task context, might sleep
0515  *
0516  * Reverses the effect of ohci_hcd_pxa27x_probe(), first invoking
0517  * the HCD's stop() method.  It is always called from a thread
0518  * context, normally "rmmod", "apmd", or something similar.
0519  */
0520 static int ohci_hcd_pxa27x_remove(struct platform_device *pdev)
0521 {
0522     struct usb_hcd *hcd = platform_get_drvdata(pdev);
0523     struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
0524     unsigned int i;
0525 
0526     usb_remove_hcd(hcd);
0527     pxa27x_stop_hc(pxa_ohci, &pdev->dev);
0528 
0529     for (i = 0; i < 3; ++i)
0530         pxa27x_ohci_set_vbus_power(pxa_ohci, i, false);
0531 
0532     usb_put_hcd(hcd);
0533     return 0;
0534 }
0535 
0536 /*-------------------------------------------------------------------------*/
0537 
0538 #ifdef CONFIG_PM
0539 static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
0540 {
0541     struct usb_hcd *hcd = dev_get_drvdata(dev);
0542     struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
0543     struct ohci_hcd *ohci = hcd_to_ohci(hcd);
0544     bool do_wakeup = device_may_wakeup(dev);
0545     int ret;
0546 
0547 
0548     if (time_before(jiffies, ohci->next_statechange))
0549         msleep(5);
0550     ohci->next_statechange = jiffies;
0551 
0552     ret = ohci_suspend(hcd, do_wakeup);
0553     if (ret)
0554         return ret;
0555 
0556     pxa27x_stop_hc(pxa_ohci, dev);
0557     return ret;
0558 }
0559 
0560 static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
0561 {
0562     struct usb_hcd *hcd = dev_get_drvdata(dev);
0563     struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
0564     struct pxaohci_platform_data *inf = dev_get_platdata(dev);
0565     struct ohci_hcd *ohci = hcd_to_ohci(hcd);
0566     int status;
0567 
0568     if (time_before(jiffies, ohci->next_statechange))
0569         msleep(5);
0570     ohci->next_statechange = jiffies;
0571 
0572     status = pxa27x_start_hc(pxa_ohci, dev);
0573     if (status < 0)
0574         return status;
0575 
0576     /* Select Power Management Mode */
0577     pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
0578 
0579     ohci_resume(hcd, false);
0580     return 0;
0581 }
0582 
0583 static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
0584     .suspend    = ohci_hcd_pxa27x_drv_suspend,
0585     .resume     = ohci_hcd_pxa27x_drv_resume,
0586 };
0587 #endif
0588 
0589 static struct platform_driver ohci_hcd_pxa27x_driver = {
0590     .probe      = ohci_hcd_pxa27x_probe,
0591     .remove     = ohci_hcd_pxa27x_remove,
0592     .shutdown   = usb_hcd_platform_shutdown,
0593     .driver     = {
0594         .name   = "pxa27x-ohci",
0595         .of_match_table = of_match_ptr(pxa_ohci_dt_ids),
0596 #ifdef CONFIG_PM
0597         .pm = &ohci_hcd_pxa27x_pm_ops,
0598 #endif
0599     },
0600 };
0601 
0602 static const struct ohci_driver_overrides pxa27x_overrides __initconst = {
0603     .extra_priv_size =      sizeof(struct pxa27x_ohci),
0604 };
0605 
0606 static int __init ohci_pxa27x_init(void)
0607 {
0608     if (usb_disabled())
0609         return -ENODEV;
0610 
0611     pr_info("%s: " DRIVER_DESC "\n", hcd_name);
0612 
0613     ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides);
0614     ohci_pxa27x_hc_driver.hub_control = pxa27x_ohci_hub_control;
0615 
0616     return platform_driver_register(&ohci_hcd_pxa27x_driver);
0617 }
0618 module_init(ohci_pxa27x_init);
0619 
0620 static void __exit ohci_pxa27x_cleanup(void)
0621 {
0622     platform_driver_unregister(&ohci_hcd_pxa27x_driver);
0623 }
0624 module_exit(ohci_pxa27x_cleanup);
0625 
0626 MODULE_DESCRIPTION(DRIVER_DESC);
0627 MODULE_LICENSE("GPL");
0628 MODULE_ALIAS("platform:pxa27x-ohci");
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