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0001 // SPDX-License-Identifier: GPL-1.0+
0002 /*
0003  * Open Host Controller Interface (OHCI) driver for USB.
0004  *
0005  * Maintainer: Alan Stern <stern@rowland.harvard.edu>
0006  *
0007  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
0008  * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
0009  *
0010  * [ Initialisation is based on Linus'  ]
0011  * [ uhci code and gregs ohci fragments ]
0012  * [ (C) Copyright 1999 Linus Torvalds  ]
0013  * [ (C) Copyright 1999 Gregory P. Smith]
0014  *
0015  *
0016  * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
0017  * interfaces (though some non-x86 Intel chips use it).  It supports
0018  * smarter hardware than UHCI.  A download link for the spec available
0019  * through the https://www.usb.org website.
0020  *
0021  * This file is licenced under the GPL.
0022  */
0023 
0024 #include <linux/module.h>
0025 #include <linux/moduleparam.h>
0026 #include <linux/pci.h>
0027 #include <linux/kernel.h>
0028 #include <linux/delay.h>
0029 #include <linux/ioport.h>
0030 #include <linux/sched.h>
0031 #include <linux/slab.h>
0032 #include <linux/errno.h>
0033 #include <linux/init.h>
0034 #include <linux/timer.h>
0035 #include <linux/list.h>
0036 #include <linux/usb.h>
0037 #include <linux/usb/otg.h>
0038 #include <linux/usb/hcd.h>
0039 #include <linux/dma-mapping.h>
0040 #include <linux/dmapool.h>
0041 #include <linux/workqueue.h>
0042 #include <linux/debugfs.h>
0043 #include <linux/genalloc.h>
0044 
0045 #include <asm/io.h>
0046 #include <asm/irq.h>
0047 #include <asm/unaligned.h>
0048 #include <asm/byteorder.h>
0049 
0050 
0051 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
0052 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
0053 
0054 /*-------------------------------------------------------------------------*/
0055 
0056 /* For initializing controller (mask in an HCFS mode too) */
0057 #define OHCI_CONTROL_INIT   OHCI_CTRL_CBSR
0058 #define OHCI_INTR_INIT \
0059         (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
0060         | OHCI_INTR_RD | OHCI_INTR_WDH)
0061 
0062 #ifdef __hppa__
0063 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
0064 #define IR_DISABLE
0065 #endif
0066 
0067 #ifdef CONFIG_ARCH_OMAP
0068 /* OMAP doesn't support IR (no SMM; not needed) */
0069 #define IR_DISABLE
0070 #endif
0071 
0072 /*-------------------------------------------------------------------------*/
0073 
0074 static const char   hcd_name [] = "ohci_hcd";
0075 
0076 #define STATECHANGE_DELAY   msecs_to_jiffies(300)
0077 #define IO_WATCHDOG_DELAY   msecs_to_jiffies(275)
0078 #define IO_WATCHDOG_OFF     0xffffff00
0079 
0080 #include "ohci.h"
0081 #include "pci-quirks.h"
0082 
0083 static void ohci_dump(struct ohci_hcd *ohci);
0084 static void ohci_stop(struct usb_hcd *hcd);
0085 static void io_watchdog_func(struct timer_list *t);
0086 
0087 #include "ohci-hub.c"
0088 #include "ohci-dbg.c"
0089 #include "ohci-mem.c"
0090 #include "ohci-q.c"
0091 
0092 
0093 /*
0094  * On architectures with edge-triggered interrupts we must never return
0095  * IRQ_NONE.
0096  */
0097 #if defined(CONFIG_SA1111)  /* ... or other edge-triggered systems */
0098 #define IRQ_NOTMINE IRQ_HANDLED
0099 #else
0100 #define IRQ_NOTMINE IRQ_NONE
0101 #endif
0102 
0103 
0104 /* Some boards misreport power switching/overcurrent */
0105 static bool distrust_firmware;
0106 module_param (distrust_firmware, bool, 0);
0107 MODULE_PARM_DESC (distrust_firmware,
0108     "true to distrust firmware power/overcurrent setup");
0109 
0110 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
0111 static bool no_handshake;
0112 module_param (no_handshake, bool, 0);
0113 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
0114 
0115 /*-------------------------------------------------------------------------*/
0116 
0117 static int number_of_tds(struct urb *urb)
0118 {
0119     int         len, i, num, this_sg_len;
0120     struct scatterlist  *sg;
0121 
0122     len = urb->transfer_buffer_length;
0123     i = urb->num_mapped_sgs;
0124 
0125     if (len > 0 && i > 0) {     /* Scatter-gather transfer */
0126         num = 0;
0127         sg = urb->sg;
0128         for (;;) {
0129             this_sg_len = min_t(int, sg_dma_len(sg), len);
0130             num += DIV_ROUND_UP(this_sg_len, 4096);
0131             len -= this_sg_len;
0132             if (--i <= 0 || len <= 0)
0133                 break;
0134             sg = sg_next(sg);
0135         }
0136 
0137     } else {            /* Non-SG transfer */
0138         /* one TD for every 4096 Bytes (could be up to 8K) */
0139         num = DIV_ROUND_UP(len, 4096);
0140     }
0141     return num;
0142 }
0143 
0144 /*
0145  * queue up an urb for anything except the root hub
0146  */
0147 static int ohci_urb_enqueue (
0148     struct usb_hcd  *hcd,
0149     struct urb  *urb,
0150     gfp_t       mem_flags
0151 ) {
0152     struct ohci_hcd *ohci = hcd_to_ohci (hcd);
0153     struct ed   *ed;
0154     urb_priv_t  *urb_priv;
0155     unsigned int    pipe = urb->pipe;
0156     int     i, size = 0;
0157     unsigned long   flags;
0158     int     retval = 0;
0159 
0160     /* every endpoint has a ed, locate and maybe (re)initialize it */
0161     ed = ed_get(ohci, urb->ep, urb->dev, pipe, urb->interval);
0162     if (! ed)
0163         return -ENOMEM;
0164 
0165     /* for the private part of the URB we need the number of TDs (size) */
0166     switch (ed->type) {
0167         case PIPE_CONTROL:
0168             /* td_submit_urb() doesn't yet handle these */
0169             if (urb->transfer_buffer_length > 4096)
0170                 return -EMSGSIZE;
0171 
0172             /* 1 TD for setup, 1 for ACK, plus ... */
0173             size = 2;
0174             fallthrough;
0175         // case PIPE_INTERRUPT:
0176         // case PIPE_BULK:
0177         default:
0178             size += number_of_tds(urb);
0179             /* maybe a zero-length packet to wrap it up */
0180             if (size == 0)
0181                 size++;
0182             else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
0183                 && (urb->transfer_buffer_length
0184                     % usb_maxpacket(urb->dev, pipe)) == 0)
0185                 size++;
0186             break;
0187         case PIPE_ISOCHRONOUS: /* number of packets from URB */
0188             size = urb->number_of_packets;
0189             break;
0190     }
0191 
0192     /* allocate the private part of the URB */
0193     urb_priv = kzalloc(struct_size(urb_priv, td, size), mem_flags);
0194     if (!urb_priv)
0195         return -ENOMEM;
0196     INIT_LIST_HEAD (&urb_priv->pending);
0197     urb_priv->length = size;
0198     urb_priv->ed = ed;
0199 
0200     /* allocate the TDs (deferring hash chain updates) */
0201     for (i = 0; i < size; i++) {
0202         urb_priv->td [i] = td_alloc (ohci, mem_flags);
0203         if (!urb_priv->td [i]) {
0204             urb_priv->length = i;
0205             urb_free_priv (ohci, urb_priv);
0206             return -ENOMEM;
0207         }
0208     }
0209 
0210     spin_lock_irqsave (&ohci->lock, flags);
0211 
0212     /* don't submit to a dead HC */
0213     if (!HCD_HW_ACCESSIBLE(hcd)) {
0214         retval = -ENODEV;
0215         goto fail;
0216     }
0217     if (ohci->rh_state != OHCI_RH_RUNNING) {
0218         retval = -ENODEV;
0219         goto fail;
0220     }
0221     retval = usb_hcd_link_urb_to_ep(hcd, urb);
0222     if (retval)
0223         goto fail;
0224 
0225     /* schedule the ed if needed */
0226     if (ed->state == ED_IDLE) {
0227         retval = ed_schedule (ohci, ed);
0228         if (retval < 0) {
0229             usb_hcd_unlink_urb_from_ep(hcd, urb);
0230             goto fail;
0231         }
0232 
0233         /* Start up the I/O watchdog timer, if it's not running */
0234         if (ohci->prev_frame_no == IO_WATCHDOG_OFF &&
0235                 list_empty(&ohci->eds_in_use) &&
0236                 !(ohci->flags & OHCI_QUIRK_QEMU)) {
0237             ohci->prev_frame_no = ohci_frame_no(ohci);
0238             mod_timer(&ohci->io_watchdog,
0239                     jiffies + IO_WATCHDOG_DELAY);
0240         }
0241         list_add(&ed->in_use_list, &ohci->eds_in_use);
0242 
0243         if (ed->type == PIPE_ISOCHRONOUS) {
0244             u16 frame = ohci_frame_no(ohci);
0245 
0246             /* delay a few frames before the first TD */
0247             frame += max_t (u16, 8, ed->interval);
0248             frame &= ~(ed->interval - 1);
0249             frame |= ed->branch;
0250             urb->start_frame = frame;
0251             ed->last_iso = frame + ed->interval * (size - 1);
0252         }
0253     } else if (ed->type == PIPE_ISOCHRONOUS) {
0254         u16 next = ohci_frame_no(ohci) + 1;
0255         u16 frame = ed->last_iso + ed->interval;
0256         u16 length = ed->interval * (size - 1);
0257 
0258         /* Behind the scheduling threshold? */
0259         if (unlikely(tick_before(frame, next))) {
0260 
0261             /* URB_ISO_ASAP: Round up to the first available slot */
0262             if (urb->transfer_flags & URB_ISO_ASAP) {
0263                 frame += (next - frame + ed->interval - 1) &
0264                         -ed->interval;
0265 
0266             /*
0267              * Not ASAP: Use the next slot in the stream,
0268              * no matter what.
0269              */
0270             } else {
0271                 /*
0272                  * Some OHCI hardware doesn't handle late TDs
0273                  * correctly.  After retiring them it proceeds
0274                  * to the next ED instead of the next TD.
0275                  * Therefore we have to omit the late TDs
0276                  * entirely.
0277                  */
0278                 urb_priv->td_cnt = DIV_ROUND_UP(
0279                         (u16) (next - frame),
0280                         ed->interval);
0281                 if (urb_priv->td_cnt >= urb_priv->length) {
0282                     ++urb_priv->td_cnt; /* Mark it */
0283                     ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
0284                             urb, frame, length,
0285                             next);
0286                 }
0287             }
0288         }
0289         urb->start_frame = frame;
0290         ed->last_iso = frame + length;
0291     }
0292 
0293     /* fill the TDs and link them to the ed; and
0294      * enable that part of the schedule, if needed
0295      * and update count of queued periodic urbs
0296      */
0297     urb->hcpriv = urb_priv;
0298     td_submit_urb (ohci, urb);
0299 
0300 fail:
0301     if (retval)
0302         urb_free_priv (ohci, urb_priv);
0303     spin_unlock_irqrestore (&ohci->lock, flags);
0304     return retval;
0305 }
0306 
0307 /*
0308  * decouple the URB from the HC queues (TDs, urb_priv).
0309  * reporting is always done
0310  * asynchronously, and we might be dealing with an urb that's
0311  * partially transferred, or an ED with other urbs being unlinked.
0312  */
0313 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
0314 {
0315     struct ohci_hcd     *ohci = hcd_to_ohci (hcd);
0316     unsigned long       flags;
0317     int         rc;
0318     urb_priv_t      *urb_priv;
0319 
0320     spin_lock_irqsave (&ohci->lock, flags);
0321     rc = usb_hcd_check_unlink_urb(hcd, urb, status);
0322     if (rc == 0) {
0323 
0324         /* Unless an IRQ completed the unlink while it was being
0325          * handed to us, flag it for unlink and giveback, and force
0326          * some upcoming INTR_SF to call finish_unlinks()
0327          */
0328         urb_priv = urb->hcpriv;
0329         if (urb_priv->ed->state == ED_OPER)
0330             start_ed_unlink(ohci, urb_priv->ed);
0331 
0332         if (ohci->rh_state != OHCI_RH_RUNNING) {
0333             /* With HC dead, we can clean up right away */
0334             ohci_work(ohci);
0335         }
0336     }
0337     spin_unlock_irqrestore (&ohci->lock, flags);
0338     return rc;
0339 }
0340 
0341 /*-------------------------------------------------------------------------*/
0342 
0343 /* frees config/altsetting state for endpoints,
0344  * including ED memory, dummy TD, and bulk/intr data toggle
0345  */
0346 
0347 static void
0348 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
0349 {
0350     struct ohci_hcd     *ohci = hcd_to_ohci (hcd);
0351     unsigned long       flags;
0352     struct ed       *ed = ep->hcpriv;
0353     unsigned        limit = 1000;
0354 
0355     /* ASSERT:  any requests/urbs are being unlinked */
0356     /* ASSERT:  nobody can be submitting urbs for this any more */
0357 
0358     if (!ed)
0359         return;
0360 
0361 rescan:
0362     spin_lock_irqsave (&ohci->lock, flags);
0363 
0364     if (ohci->rh_state != OHCI_RH_RUNNING) {
0365 sanitize:
0366         ed->state = ED_IDLE;
0367         ohci_work(ohci);
0368     }
0369 
0370     switch (ed->state) {
0371     case ED_UNLINK:     /* wait for hw to finish? */
0372         /* major IRQ delivery trouble loses INTR_SF too... */
0373         if (limit-- == 0) {
0374             ohci_warn(ohci, "ED unlink timeout\n");
0375             goto sanitize;
0376         }
0377         spin_unlock_irqrestore (&ohci->lock, flags);
0378         schedule_timeout_uninterruptible(1);
0379         goto rescan;
0380     case ED_IDLE:       /* fully unlinked */
0381         if (list_empty (&ed->td_list)) {
0382             td_free (ohci, ed->dummy);
0383             ed_free (ohci, ed);
0384             break;
0385         }
0386         fallthrough;
0387     default:
0388         /* caller was supposed to have unlinked any requests;
0389          * that's not our job.  can't recover; must leak ed.
0390          */
0391         ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
0392             ed, ep->desc.bEndpointAddress, ed->state,
0393             list_empty (&ed->td_list) ? "" : " (has tds)");
0394         td_free (ohci, ed->dummy);
0395         break;
0396     }
0397     ep->hcpriv = NULL;
0398     spin_unlock_irqrestore (&ohci->lock, flags);
0399 }
0400 
0401 static int ohci_get_frame (struct usb_hcd *hcd)
0402 {
0403     struct ohci_hcd     *ohci = hcd_to_ohci (hcd);
0404 
0405     return ohci_frame_no(ohci);
0406 }
0407 
0408 static void ohci_usb_reset (struct ohci_hcd *ohci)
0409 {
0410     ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
0411     ohci->hc_control &= OHCI_CTRL_RWC;
0412     ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
0413     ohci->rh_state = OHCI_RH_HALTED;
0414 }
0415 
0416 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
0417  * other cases where the next software may expect clean state from the
0418  * "firmware".  this is bus-neutral, unlike shutdown() methods.
0419  */
0420 static void _ohci_shutdown(struct usb_hcd *hcd)
0421 {
0422     struct ohci_hcd *ohci;
0423 
0424     ohci = hcd_to_ohci (hcd);
0425     ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
0426 
0427     /* Software reset, after which the controller goes into SUSPEND */
0428     ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
0429     ohci_readl(ohci, &ohci->regs->cmdstatus);   /* flush the writes */
0430     udelay(10);
0431 
0432     ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
0433     ohci->rh_state = OHCI_RH_HALTED;
0434 }
0435 
0436 static void ohci_shutdown(struct usb_hcd *hcd)
0437 {
0438     struct ohci_hcd *ohci = hcd_to_ohci(hcd);
0439     unsigned long flags;
0440 
0441     spin_lock_irqsave(&ohci->lock, flags);
0442     _ohci_shutdown(hcd);
0443     spin_unlock_irqrestore(&ohci->lock, flags);
0444 }
0445 
0446 /*-------------------------------------------------------------------------*
0447  * HC functions
0448  *-------------------------------------------------------------------------*/
0449 
0450 /* init memory, and kick BIOS/SMM off */
0451 
0452 static int ohci_init (struct ohci_hcd *ohci)
0453 {
0454     int ret;
0455     struct usb_hcd *hcd = ohci_to_hcd(ohci);
0456 
0457     /* Accept arbitrarily long scatter-gather lists */
0458     if (!hcd->localmem_pool)
0459         hcd->self.sg_tablesize = ~0;
0460 
0461     if (distrust_firmware)
0462         ohci->flags |= OHCI_QUIRK_HUB_POWER;
0463 
0464     ohci->rh_state = OHCI_RH_HALTED;
0465     ohci->regs = hcd->regs;
0466 
0467     /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
0468      * was never needed for most non-PCI systems ... remove the code?
0469      */
0470 
0471 #ifndef IR_DISABLE
0472     /* SMM owns the HC?  not for long! */
0473     if (!no_handshake && ohci_readl (ohci,
0474                     &ohci->regs->control) & OHCI_CTRL_IR) {
0475         u32 temp;
0476 
0477         ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
0478 
0479         /* this timeout is arbitrary.  we make it long, so systems
0480          * depending on usb keyboards may be usable even if the
0481          * BIOS/SMM code seems pretty broken.
0482          */
0483         temp = 500; /* arbitrary: five seconds */
0484 
0485         ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
0486         ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
0487         while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
0488             msleep (10);
0489             if (--temp == 0) {
0490                 ohci_err (ohci, "USB HC takeover failed!"
0491                     "  (BIOS/SMM bug)\n");
0492                 return -EBUSY;
0493             }
0494         }
0495         ohci_usb_reset (ohci);
0496     }
0497 #endif
0498 
0499     /* Disable HC interrupts */
0500     ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
0501 
0502     /* flush the writes, and save key bits like RWC */
0503     if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
0504         ohci->hc_control |= OHCI_CTRL_RWC;
0505 
0506     /* Read the number of ports unless overridden */
0507     if (ohci->num_ports == 0)
0508         ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
0509 
0510     if (ohci->hcca)
0511         return 0;
0512 
0513     timer_setup(&ohci->io_watchdog, io_watchdog_func, 0);
0514     ohci->prev_frame_no = IO_WATCHDOG_OFF;
0515 
0516     if (hcd->localmem_pool)
0517         ohci->hcca = gen_pool_dma_alloc_align(hcd->localmem_pool,
0518                         sizeof(*ohci->hcca),
0519                         &ohci->hcca_dma, 256);
0520     else
0521         ohci->hcca = dma_alloc_coherent(hcd->self.controller,
0522                         sizeof(*ohci->hcca),
0523                         &ohci->hcca_dma,
0524                         GFP_KERNEL);
0525     if (!ohci->hcca)
0526         return -ENOMEM;
0527 
0528     if ((ret = ohci_mem_init (ohci)) < 0)
0529         ohci_stop (hcd);
0530     else {
0531         create_debug_files (ohci);
0532     }
0533 
0534     return ret;
0535 }
0536 
0537 /*-------------------------------------------------------------------------*/
0538 
0539 /* Start an OHCI controller, set the BUS operational
0540  * resets USB and controller
0541  * enable interrupts
0542  */
0543 static int ohci_run (struct ohci_hcd *ohci)
0544 {
0545     u32         mask, val;
0546     int         first = ohci->fminterval == 0;
0547     struct usb_hcd      *hcd = ohci_to_hcd(ohci);
0548 
0549     ohci->rh_state = OHCI_RH_HALTED;
0550 
0551     /* boot firmware should have set this up (5.1.1.3.1) */
0552     if (first) {
0553 
0554         val = ohci_readl (ohci, &ohci->regs->fminterval);
0555         ohci->fminterval = val & 0x3fff;
0556         if (ohci->fminterval != FI)
0557             ohci_dbg (ohci, "fminterval delta %d\n",
0558                 ohci->fminterval - FI);
0559         ohci->fminterval |= FSMP (ohci->fminterval) << 16;
0560         /* also: power/overcurrent flags in roothub.a */
0561     }
0562 
0563     /* Reset USB nearly "by the book".  RemoteWakeupConnected has
0564      * to be checked in case boot firmware (BIOS/SMM/...) has set up
0565      * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
0566      * If the bus glue detected wakeup capability then it should
0567      * already be enabled; if so we'll just enable it again.
0568      */
0569     if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
0570         device_set_wakeup_capable(hcd->self.controller, 1);
0571 
0572     switch (ohci->hc_control & OHCI_CTRL_HCFS) {
0573     case OHCI_USB_OPER:
0574         val = 0;
0575         break;
0576     case OHCI_USB_SUSPEND:
0577     case OHCI_USB_RESUME:
0578         ohci->hc_control &= OHCI_CTRL_RWC;
0579         ohci->hc_control |= OHCI_USB_RESUME;
0580         val = 10 /* msec wait */;
0581         break;
0582     // case OHCI_USB_RESET:
0583     default:
0584         ohci->hc_control &= OHCI_CTRL_RWC;
0585         ohci->hc_control |= OHCI_USB_RESET;
0586         val = 50 /* msec wait */;
0587         break;
0588     }
0589     ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
0590     // flush the writes
0591     (void) ohci_readl (ohci, &ohci->regs->control);
0592     msleep(val);
0593 
0594     memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
0595 
0596     /* 2msec timelimit here means no irqs/preempt */
0597     spin_lock_irq (&ohci->lock);
0598 
0599 retry:
0600     /* HC Reset requires max 10 us delay */
0601     ohci_writel (ohci, OHCI_HCR,  &ohci->regs->cmdstatus);
0602     val = 30;   /* ... allow extra time */
0603     while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
0604         if (--val == 0) {
0605             spin_unlock_irq (&ohci->lock);
0606             ohci_err (ohci, "USB HC reset timed out!\n");
0607             return -1;
0608         }
0609         udelay (1);
0610     }
0611 
0612     /* now we're in the SUSPEND state ... must go OPERATIONAL
0613      * within 2msec else HC enters RESUME
0614      *
0615      * ... but some hardware won't init fmInterval "by the book"
0616      * (SiS, OPTi ...), so reset again instead.  SiS doesn't need
0617      * this if we write fmInterval after we're OPERATIONAL.
0618      * Unclear about ALi, ServerWorks, and others ... this could
0619      * easily be a longstanding bug in chip init on Linux.
0620      */
0621     if (ohci->flags & OHCI_QUIRK_INITRESET) {
0622         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
0623         // flush those writes
0624         (void) ohci_readl (ohci, &ohci->regs->control);
0625     }
0626 
0627     /* Tell the controller where the control and bulk lists are
0628      * The lists are empty now. */
0629     ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
0630     ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
0631 
0632     /* a reset clears this */
0633     ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
0634 
0635     periodic_reinit (ohci);
0636 
0637     /* some OHCI implementations are finicky about how they init.
0638      * bogus values here mean not even enumeration could work.
0639      */
0640     if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
0641             || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
0642         if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
0643             ohci->flags |= OHCI_QUIRK_INITRESET;
0644             ohci_dbg (ohci, "enabling initreset quirk\n");
0645             goto retry;
0646         }
0647         spin_unlock_irq (&ohci->lock);
0648         ohci_err (ohci, "init err (%08x %04x)\n",
0649             ohci_readl (ohci, &ohci->regs->fminterval),
0650             ohci_readl (ohci, &ohci->regs->periodicstart));
0651         return -EOVERFLOW;
0652     }
0653 
0654     /* use rhsc irqs after hub_wq is allocated */
0655     set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
0656     hcd->uses_new_polling = 1;
0657 
0658     /* start controller operations */
0659     ohci->hc_control &= OHCI_CTRL_RWC;
0660     ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
0661     ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
0662     ohci->rh_state = OHCI_RH_RUNNING;
0663 
0664     /* wake on ConnectStatusChange, matching external hubs */
0665     ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
0666 
0667     /* Choose the interrupts we care about now, others later on demand */
0668     mask = OHCI_INTR_INIT;
0669     ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
0670     ohci_writel (ohci, mask, &ohci->regs->intrenable);
0671 
0672     /* handle root hub init quirks ... */
0673     val = roothub_a (ohci);
0674     /* Configure for per-port over-current protection by default */
0675     val &= ~RH_A_NOCP;
0676     val |= RH_A_OCPM;
0677     if (ohci->flags & OHCI_QUIRK_SUPERIO) {
0678         /* NSC 87560 and maybe others.
0679          * Ganged power switching, no over-current protection.
0680          */
0681         val |= RH_A_NOCP;
0682         val &= ~(RH_A_POTPGT | RH_A_NPS | RH_A_PSM | RH_A_OCPM);
0683     } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
0684             (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
0685         /* hub power always on; required for AMD-756 and some
0686          * Mac platforms.
0687          */
0688         val |= RH_A_NPS;
0689     }
0690     ohci_writel(ohci, val, &ohci->regs->roothub.a);
0691 
0692     ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
0693     ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
0694                         &ohci->regs->roothub.b);
0695     // flush those writes
0696     (void) ohci_readl (ohci, &ohci->regs->control);
0697 
0698     ohci->next_statechange = jiffies + STATECHANGE_DELAY;
0699     spin_unlock_irq (&ohci->lock);
0700 
0701     // POTPGT delay is bits 24-31, in 2 ms units.
0702     mdelay ((val >> 23) & 0x1fe);
0703 
0704     ohci_dump(ohci);
0705 
0706     return 0;
0707 }
0708 
0709 /* ohci_setup routine for generic controller initialization */
0710 
0711 int ohci_setup(struct usb_hcd *hcd)
0712 {
0713     struct ohci_hcd     *ohci = hcd_to_ohci(hcd);
0714 
0715     ohci_hcd_init(ohci);
0716     
0717     return ohci_init(ohci);
0718 }
0719 EXPORT_SYMBOL_GPL(ohci_setup);
0720 
0721 /* ohci_start routine for generic controller start of all OHCI bus glue */
0722 static int ohci_start(struct usb_hcd *hcd)
0723 {
0724     struct ohci_hcd     *ohci = hcd_to_ohci(hcd);
0725     int ret;
0726 
0727     ret = ohci_run(ohci);
0728     if (ret < 0) {
0729         ohci_err(ohci, "can't start\n");
0730         ohci_stop(hcd);
0731     }
0732     return ret;
0733 }
0734 
0735 /*-------------------------------------------------------------------------*/
0736 
0737 /*
0738  * Some OHCI controllers are known to lose track of completed TDs.  They
0739  * don't add the TDs to the hardware done queue, which means we never see
0740  * them as being completed.
0741  *
0742  * This watchdog routine checks for such problems.  Without some way to
0743  * tell when those TDs have completed, we would never take their EDs off
0744  * the unlink list.  As a result, URBs could never be dequeued and
0745  * endpoints could never be released.
0746  */
0747 static void io_watchdog_func(struct timer_list *t)
0748 {
0749     struct ohci_hcd *ohci = from_timer(ohci, t, io_watchdog);
0750     bool        takeback_all_pending = false;
0751     u32     status;
0752     u32     head;
0753     struct ed   *ed;
0754     struct td   *td, *td_start, *td_next;
0755     unsigned    frame_no, prev_frame_no = IO_WATCHDOG_OFF;
0756     unsigned long   flags;
0757 
0758     spin_lock_irqsave(&ohci->lock, flags);
0759 
0760     /*
0761      * One way to lose track of completed TDs is if the controller
0762      * never writes back the done queue head.  If it hasn't been
0763      * written back since the last time this function ran and if it
0764      * was non-empty at that time, something is badly wrong with the
0765      * hardware.
0766      */
0767     status = ohci_readl(ohci, &ohci->regs->intrstatus);
0768     if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) {
0769         if (ohci->prev_donehead) {
0770             ohci_err(ohci, "HcDoneHead not written back; disabled\n");
0771  died:
0772             usb_hc_died(ohci_to_hcd(ohci));
0773             ohci_dump(ohci);
0774             _ohci_shutdown(ohci_to_hcd(ohci));
0775             goto done;
0776         } else {
0777             /* No write back because the done queue was empty */
0778             takeback_all_pending = true;
0779         }
0780     }
0781 
0782     /* Check every ED which might have pending TDs */
0783     list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) {
0784         if (ed->pending_td) {
0785             if (takeback_all_pending ||
0786                     OKAY_TO_TAKEBACK(ohci, ed)) {
0787                 unsigned tmp = hc32_to_cpu(ohci, ed->hwINFO);
0788 
0789                 ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n",
0790                         0x007f & tmp,
0791                         (0x000f & (tmp >> 7)) +
0792                             ((tmp & ED_IN) >> 5));
0793                 add_to_done_list(ohci, ed->pending_td);
0794             }
0795         }
0796 
0797         /* Starting from the latest pending TD, */
0798         td = ed->pending_td;
0799 
0800         /* or the last TD on the done list, */
0801         if (!td) {
0802             list_for_each_entry(td_next, &ed->td_list, td_list) {
0803                 if (!td_next->next_dl_td)
0804                     break;
0805                 td = td_next;
0806             }
0807         }
0808 
0809         /* find the last TD processed by the controller. */
0810         head = hc32_to_cpu(ohci, READ_ONCE(ed->hwHeadP)) & TD_MASK;
0811         td_start = td;
0812         td_next = list_prepare_entry(td, &ed->td_list, td_list);
0813         list_for_each_entry_continue(td_next, &ed->td_list, td_list) {
0814             if (head == (u32) td_next->td_dma)
0815                 break;
0816             td = td_next;   /* head pointer has passed this TD */
0817         }
0818         if (td != td_start) {
0819             /*
0820              * In case a WDH cycle is in progress, we will wait
0821              * for the next two cycles to complete before assuming
0822              * this TD will never get on the done queue.
0823              */
0824             ed->takeback_wdh_cnt = ohci->wdh_cnt + 2;
0825             ed->pending_td = td;
0826         }
0827     }
0828 
0829     ohci_work(ohci);
0830 
0831     if (ohci->rh_state == OHCI_RH_RUNNING) {
0832 
0833         /*
0834          * Sometimes a controller just stops working.  We can tell
0835          * by checking that the frame counter has advanced since
0836          * the last time we ran.
0837          *
0838          * But be careful: Some controllers violate the spec by
0839          * stopping their frame counter when no ports are active.
0840          */
0841         frame_no = ohci_frame_no(ohci);
0842         if (frame_no == ohci->prev_frame_no) {
0843             int     active_cnt = 0;
0844             int     i;
0845             unsigned    tmp;
0846 
0847             for (i = 0; i < ohci->num_ports; ++i) {
0848                 tmp = roothub_portstatus(ohci, i);
0849                 /* Enabled and not suspended? */
0850                 if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS))
0851                     ++active_cnt;
0852             }
0853 
0854             if (active_cnt > 0) {
0855                 ohci_err(ohci, "frame counter not updating; disabled\n");
0856                 goto died;
0857             }
0858         }
0859         if (!list_empty(&ohci->eds_in_use)) {
0860             prev_frame_no = frame_no;
0861             ohci->prev_wdh_cnt = ohci->wdh_cnt;
0862             ohci->prev_donehead = ohci_readl(ohci,
0863                     &ohci->regs->donehead);
0864             mod_timer(&ohci->io_watchdog,
0865                     jiffies + IO_WATCHDOG_DELAY);
0866         }
0867     }
0868 
0869  done:
0870     ohci->prev_frame_no = prev_frame_no;
0871     spin_unlock_irqrestore(&ohci->lock, flags);
0872 }
0873 
0874 /* an interrupt happens */
0875 
0876 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
0877 {
0878     struct ohci_hcd     *ohci = hcd_to_ohci (hcd);
0879     struct ohci_regs __iomem *regs = ohci->regs;
0880     int         ints;
0881 
0882     /* Read interrupt status (and flush pending writes).  We ignore the
0883      * optimization of checking the LSB of hcca->done_head; it doesn't
0884      * work on all systems (edge triggering for OHCI can be a factor).
0885      */
0886     ints = ohci_readl(ohci, &regs->intrstatus);
0887 
0888     /* Check for an all 1's result which is a typical consequence
0889      * of dead, unclocked, or unplugged (CardBus...) devices
0890      */
0891     if (ints == ~(u32)0) {
0892         ohci->rh_state = OHCI_RH_HALTED;
0893         ohci_dbg (ohci, "device removed!\n");
0894         usb_hc_died(hcd);
0895         return IRQ_HANDLED;
0896     }
0897 
0898     /* We only care about interrupts that are enabled */
0899     ints &= ohci_readl(ohci, &regs->intrenable);
0900 
0901     /* interrupt for some other device? */
0902     if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
0903         return IRQ_NOTMINE;
0904 
0905     if (ints & OHCI_INTR_UE) {
0906         // e.g. due to PCI Master/Target Abort
0907         if (quirk_nec(ohci)) {
0908             /* Workaround for a silicon bug in some NEC chips used
0909              * in Apple's PowerBooks. Adapted from Darwin code.
0910              */
0911             ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
0912 
0913             ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
0914 
0915             schedule_work (&ohci->nec_work);
0916         } else {
0917             ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
0918             ohci->rh_state = OHCI_RH_HALTED;
0919             usb_hc_died(hcd);
0920         }
0921 
0922         ohci_dump(ohci);
0923         ohci_usb_reset (ohci);
0924     }
0925 
0926     if (ints & OHCI_INTR_RHSC) {
0927         ohci_dbg(ohci, "rhsc\n");
0928         ohci->next_statechange = jiffies + STATECHANGE_DELAY;
0929         ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
0930                 &regs->intrstatus);
0931 
0932         /* NOTE: Vendors didn't always make the same implementation
0933          * choices for RHSC.  Many followed the spec; RHSC triggers
0934          * on an edge, like setting and maybe clearing a port status
0935          * change bit.  With others it's level-triggered, active
0936          * until hub_wq clears all the port status change bits.  We'll
0937          * always disable it here and rely on polling until hub_wq
0938          * re-enables it.
0939          */
0940         ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
0941         usb_hcd_poll_rh_status(hcd);
0942     }
0943 
0944     /* For connect and disconnect events, we expect the controller
0945      * to turn on RHSC along with RD.  But for remote wakeup events
0946      * this might not happen.
0947      */
0948     else if (ints & OHCI_INTR_RD) {
0949         ohci_dbg(ohci, "resume detect\n");
0950         ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
0951         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
0952         if (ohci->autostop) {
0953             spin_lock (&ohci->lock);
0954             ohci_rh_resume (ohci);
0955             spin_unlock (&ohci->lock);
0956         } else
0957             usb_hcd_resume_root_hub(hcd);
0958     }
0959 
0960     spin_lock(&ohci->lock);
0961     if (ints & OHCI_INTR_WDH)
0962         update_done_list(ohci);
0963 
0964     /* could track INTR_SO to reduce available PCI/... bandwidth */
0965 
0966     /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
0967      * when there's still unlinking to be done (next frame).
0968      */
0969     ohci_work(ohci);
0970     if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
0971             && ohci->rh_state == OHCI_RH_RUNNING)
0972         ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
0973 
0974     if (ohci->rh_state == OHCI_RH_RUNNING) {
0975         ohci_writel (ohci, ints, &regs->intrstatus);
0976         if (ints & OHCI_INTR_WDH)
0977             ++ohci->wdh_cnt;
0978 
0979         ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
0980         // flush those writes
0981         (void) ohci_readl (ohci, &ohci->regs->control);
0982     }
0983     spin_unlock(&ohci->lock);
0984 
0985     return IRQ_HANDLED;
0986 }
0987 
0988 /*-------------------------------------------------------------------------*/
0989 
0990 static void ohci_stop (struct usb_hcd *hcd)
0991 {
0992     struct ohci_hcd     *ohci = hcd_to_ohci (hcd);
0993 
0994     ohci_dump(ohci);
0995 
0996     if (quirk_nec(ohci))
0997         flush_work(&ohci->nec_work);
0998     del_timer_sync(&ohci->io_watchdog);
0999     ohci->prev_frame_no = IO_WATCHDOG_OFF;
1000 
1001     ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1002     ohci_usb_reset(ohci);
1003     free_irq(hcd->irq, hcd);
1004     hcd->irq = 0;
1005 
1006     if (quirk_amdiso(ohci))
1007         usb_amd_dev_put();
1008 
1009     remove_debug_files (ohci);
1010     ohci_mem_cleanup (ohci);
1011     if (ohci->hcca) {
1012         if (hcd->localmem_pool)
1013             gen_pool_free(hcd->localmem_pool,
1014                       (unsigned long)ohci->hcca,
1015                       sizeof(*ohci->hcca));
1016         else
1017             dma_free_coherent(hcd->self.controller,
1018                       sizeof(*ohci->hcca),
1019                       ohci->hcca, ohci->hcca_dma);
1020         ohci->hcca = NULL;
1021         ohci->hcca_dma = 0;
1022     }
1023 }
1024 
1025 /*-------------------------------------------------------------------------*/
1026 
1027 #if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
1028 
1029 /* must not be called from interrupt context */
1030 int ohci_restart(struct ohci_hcd *ohci)
1031 {
1032     int temp;
1033     int i;
1034     struct urb_priv *priv;
1035 
1036     ohci_init(ohci);
1037     spin_lock_irq(&ohci->lock);
1038     ohci->rh_state = OHCI_RH_HALTED;
1039 
1040     /* Recycle any "live" eds/tds (and urbs). */
1041     if (!list_empty (&ohci->pending))
1042         ohci_dbg(ohci, "abort schedule...\n");
1043     list_for_each_entry (priv, &ohci->pending, pending) {
1044         struct urb  *urb = priv->td[0]->urb;
1045         struct ed   *ed = priv->ed;
1046 
1047         switch (ed->state) {
1048         case ED_OPER:
1049             ed->state = ED_UNLINK;
1050             ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
1051             ed_deschedule (ohci, ed);
1052 
1053             ed->ed_next = ohci->ed_rm_list;
1054             ed->ed_prev = NULL;
1055             ohci->ed_rm_list = ed;
1056             fallthrough;
1057         case ED_UNLINK:
1058             break;
1059         default:
1060             ohci_dbg(ohci, "bogus ed %p state %d\n",
1061                     ed, ed->state);
1062         }
1063 
1064         if (!urb->unlinked)
1065             urb->unlinked = -ESHUTDOWN;
1066     }
1067     ohci_work(ohci);
1068     spin_unlock_irq(&ohci->lock);
1069 
1070     /* paranoia, in case that didn't work: */
1071 
1072     /* empty the interrupt branches */
1073     for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1074     for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1075 
1076     /* no EDs to remove */
1077     ohci->ed_rm_list = NULL;
1078 
1079     /* empty control and bulk lists */
1080     ohci->ed_controltail = NULL;
1081     ohci->ed_bulktail    = NULL;
1082 
1083     if ((temp = ohci_run (ohci)) < 0) {
1084         ohci_err (ohci, "can't restart, %d\n", temp);
1085         return temp;
1086     }
1087     ohci_dbg(ohci, "restart complete\n");
1088     return 0;
1089 }
1090 EXPORT_SYMBOL_GPL(ohci_restart);
1091 
1092 #endif
1093 
1094 #ifdef CONFIG_PM
1095 
1096 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1097 {
1098     struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1099     unsigned long   flags;
1100     int     rc = 0;
1101 
1102     /* Disable irq emission and mark HW unaccessible. Use
1103      * the spinlock to properly synchronize with possible pending
1104      * RH suspend or resume activity.
1105      */
1106     spin_lock_irqsave (&ohci->lock, flags);
1107     ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1108     (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1109 
1110     clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1111     spin_unlock_irqrestore (&ohci->lock, flags);
1112 
1113     synchronize_irq(hcd->irq);
1114 
1115     if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1116         ohci_resume(hcd, false);
1117         rc = -EBUSY;
1118     }
1119     return rc;
1120 }
1121 EXPORT_SYMBOL_GPL(ohci_suspend);
1122 
1123 
1124 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1125 {
1126     struct ohci_hcd     *ohci = hcd_to_ohci(hcd);
1127     int         port;
1128     bool            need_reinit = false;
1129 
1130     set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1131 
1132     /* Make sure resume from hibernation re-enumerates everything */
1133     if (hibernated)
1134         ohci_usb_reset(ohci);
1135 
1136     /* See if the controller is already running or has been reset */
1137     ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1138     if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1139         need_reinit = true;
1140     } else {
1141         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1142         case OHCI_USB_OPER:
1143         case OHCI_USB_RESET:
1144             need_reinit = true;
1145         }
1146     }
1147 
1148     /* If needed, reinitialize and suspend the root hub */
1149     if (need_reinit) {
1150         spin_lock_irq(&ohci->lock);
1151         ohci_rh_resume(ohci);
1152         ohci_rh_suspend(ohci, 0);
1153         spin_unlock_irq(&ohci->lock);
1154     }
1155 
1156     /* Normally just turn on port power and enable interrupts */
1157     else {
1158         ohci_dbg(ohci, "powerup ports\n");
1159         for (port = 0; port < ohci->num_ports; port++)
1160             ohci_writel(ohci, RH_PS_PPS,
1161                     &ohci->regs->roothub.portstatus[port]);
1162 
1163         ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1164         ohci_readl(ohci, &ohci->regs->intrenable);
1165         msleep(20);
1166     }
1167 
1168     usb_hcd_resume_root_hub(hcd);
1169 
1170     return 0;
1171 }
1172 EXPORT_SYMBOL_GPL(ohci_resume);
1173 
1174 #endif
1175 
1176 /*-------------------------------------------------------------------------*/
1177 
1178 /*
1179  * Generic structure: This gets copied for platform drivers so that
1180  * individual entries can be overridden as needed.
1181  */
1182 
1183 static const struct hc_driver ohci_hc_driver = {
1184     .description =          hcd_name,
1185     .product_desc =         "OHCI Host Controller",
1186     .hcd_priv_size =        sizeof(struct ohci_hcd),
1187 
1188     /*
1189      * generic hardware linkage
1190     */
1191     .irq =                  ohci_irq,
1192     .flags =                HCD_MEMORY | HCD_DMA | HCD_USB11,
1193 
1194     /*
1195     * basic lifecycle operations
1196     */
1197     .reset =                ohci_setup,
1198     .start =                ohci_start,
1199     .stop =                 ohci_stop,
1200     .shutdown =             ohci_shutdown,
1201 
1202     /*
1203      * managing i/o requests and associated device resources
1204     */
1205     .urb_enqueue =          ohci_urb_enqueue,
1206     .urb_dequeue =          ohci_urb_dequeue,
1207     .endpoint_disable =     ohci_endpoint_disable,
1208 
1209     /*
1210     * scheduling support
1211     */
1212     .get_frame_number =     ohci_get_frame,
1213 
1214     /*
1215     * root hub support
1216     */
1217     .hub_status_data =      ohci_hub_status_data,
1218     .hub_control =          ohci_hub_control,
1219 #ifdef CONFIG_PM
1220     .bus_suspend =          ohci_bus_suspend,
1221     .bus_resume =           ohci_bus_resume,
1222 #endif
1223     .start_port_reset = ohci_start_port_reset,
1224 };
1225 
1226 void ohci_init_driver(struct hc_driver *drv,
1227         const struct ohci_driver_overrides *over)
1228 {
1229     /* Copy the generic table to drv and then apply the overrides */
1230     *drv = ohci_hc_driver;
1231 
1232     if (over) {
1233         drv->product_desc = over->product_desc;
1234         drv->hcd_priv_size += over->extra_priv_size;
1235         if (over->reset)
1236             drv->reset = over->reset;
1237     }
1238 }
1239 EXPORT_SYMBOL_GPL(ohci_init_driver);
1240 
1241 /*-------------------------------------------------------------------------*/
1242 
1243 MODULE_AUTHOR (DRIVER_AUTHOR);
1244 MODULE_DESCRIPTION(DRIVER_DESC);
1245 MODULE_LICENSE ("GPL");
1246 
1247 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1248 #include "ohci-sa1111.c"
1249 #define SA1111_DRIVER       ohci_hcd_sa1111_driver
1250 #endif
1251 
1252 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1253 #include "ohci-ppc-of.c"
1254 #define OF_PLATFORM_DRIVER  ohci_hcd_ppc_of_driver
1255 #endif
1256 
1257 #ifdef CONFIG_PPC_PS3
1258 #include "ohci-ps3.c"
1259 #define PS3_SYSTEM_BUS_DRIVER   ps3_ohci_driver
1260 #endif
1261 
1262 #ifdef CONFIG_MFD_SM501
1263 #include "ohci-sm501.c"
1264 #define SM501_OHCI_DRIVER   ohci_hcd_sm501_driver
1265 #endif
1266 
1267 #ifdef CONFIG_MFD_TC6393XB
1268 #include "ohci-tmio.c"
1269 #define TMIO_OHCI_DRIVER    ohci_hcd_tmio_driver
1270 #endif
1271 
1272 static int __init ohci_hcd_mod_init(void)
1273 {
1274     int retval = 0;
1275 
1276     if (usb_disabled())
1277         return -ENODEV;
1278 
1279     printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1280     pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name,
1281         sizeof (struct ed), sizeof (struct td));
1282     set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1283 
1284     ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1285 
1286 #ifdef PS3_SYSTEM_BUS_DRIVER
1287     retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1288     if (retval < 0)
1289         goto error_ps3;
1290 #endif
1291 
1292 #ifdef OF_PLATFORM_DRIVER
1293     retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1294     if (retval < 0)
1295         goto error_of_platform;
1296 #endif
1297 
1298 #ifdef SA1111_DRIVER
1299     retval = sa1111_driver_register(&SA1111_DRIVER);
1300     if (retval < 0)
1301         goto error_sa1111;
1302 #endif
1303 
1304 #ifdef SM501_OHCI_DRIVER
1305     retval = platform_driver_register(&SM501_OHCI_DRIVER);
1306     if (retval < 0)
1307         goto error_sm501;
1308 #endif
1309 
1310 #ifdef TMIO_OHCI_DRIVER
1311     retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1312     if (retval < 0)
1313         goto error_tmio;
1314 #endif
1315 
1316     return retval;
1317 
1318     /* Error path */
1319 #ifdef TMIO_OHCI_DRIVER
1320     platform_driver_unregister(&TMIO_OHCI_DRIVER);
1321  error_tmio:
1322 #endif
1323 #ifdef SM501_OHCI_DRIVER
1324     platform_driver_unregister(&SM501_OHCI_DRIVER);
1325  error_sm501:
1326 #endif
1327 #ifdef SA1111_DRIVER
1328     sa1111_driver_unregister(&SA1111_DRIVER);
1329  error_sa1111:
1330 #endif
1331 #ifdef OF_PLATFORM_DRIVER
1332     platform_driver_unregister(&OF_PLATFORM_DRIVER);
1333  error_of_platform:
1334 #endif
1335 #ifdef PS3_SYSTEM_BUS_DRIVER
1336     ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1337  error_ps3:
1338 #endif
1339     debugfs_remove(ohci_debug_root);
1340     ohci_debug_root = NULL;
1341 
1342     clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1343     return retval;
1344 }
1345 module_init(ohci_hcd_mod_init);
1346 
1347 static void __exit ohci_hcd_mod_exit(void)
1348 {
1349 #ifdef TMIO_OHCI_DRIVER
1350     platform_driver_unregister(&TMIO_OHCI_DRIVER);
1351 #endif
1352 #ifdef SM501_OHCI_DRIVER
1353     platform_driver_unregister(&SM501_OHCI_DRIVER);
1354 #endif
1355 #ifdef SA1111_DRIVER
1356     sa1111_driver_unregister(&SA1111_DRIVER);
1357 #endif
1358 #ifdef OF_PLATFORM_DRIVER
1359     platform_driver_unregister(&OF_PLATFORM_DRIVER);
1360 #endif
1361 #ifdef PS3_SYSTEM_BUS_DRIVER
1362     ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1363 #endif
1364     debugfs_remove(ohci_debug_root);
1365     clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1366 }
1367 module_exit(ohci_hcd_mod_exit);
1368
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