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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * ISP1362 HCD (Host Controller Driver) for USB.
0004  *
0005  * COPYRIGHT (C) by L. Wassmann <LW@KARO-electronics.de>
0006  */
0007 
0008 /* ------------------------------------------------------------------------- */
0009 
0010 #define MAX_ROOT_PORTS      2
0011 
0012 #define USE_32BIT       0
0013 
0014 /* These options are mutually exclusive */
0015 #define USE_PLATFORM_DELAY  0
0016 #define USE_NDELAY      0
0017 
0018 #define DUMMY_DELAY_ACCESS do {} while (0)
0019 
0020 /* ------------------------------------------------------------------------- */
0021 
0022 #define USB_RESET_WIDTH         50
0023 #define MAX_XFER_SIZE           1023
0024 
0025 /* Buffer sizes */
0026 #define ISP1362_BUF_SIZE        4096
0027 #define ISP1362_ISTL_BUFSIZE        512
0028 #define ISP1362_INTL_BLKSIZE        64
0029 #define ISP1362_INTL_BUFFERS        16
0030 #define ISP1362_ATL_BLKSIZE     64
0031 
0032 #define ISP1362_REG_WRITE_OFFSET    0x80
0033 
0034 #define REG_WIDTH_16            0x000
0035 #define REG_WIDTH_32            0x100
0036 #define REG_WIDTH_MASK          0x100
0037 #define REG_NO_MASK         0x0ff
0038 
0039 #ifdef ISP1362_DEBUG
0040 typedef const unsigned int isp1362_reg_t;
0041 
0042 #define REG_ACCESS_R            0x200
0043 #define REG_ACCESS_W            0x400
0044 #define REG_ACCESS_RW           0x600
0045 #define REG_ACCESS_MASK         0x600
0046 
0047 #define ISP1362_REG_NO(r)       ((r) & REG_NO_MASK)
0048 
0049 #define ISP1362_REG(name, addr, width, rw) \
0050 static isp1362_reg_t ISP1362_REG_##name = ((addr) | (width) | (rw))
0051 
0052 #define REG_ACCESS_TEST(r)   BUG_ON(((r) & ISP1362_REG_WRITE_OFFSET) && !((r) & REG_ACCESS_W))
0053 #define REG_WIDTH_TEST(r, w) BUG_ON(((r) & REG_WIDTH_MASK) != (w))
0054 #else
0055 typedef const unsigned char isp1362_reg_t;
0056 #define ISP1362_REG_NO(r)       (r)
0057 
0058 #define ISP1362_REG(name, addr, width, rw) \
0059 static isp1362_reg_t __maybe_unused ISP1362_REG_##name = addr
0060 
0061 #define REG_ACCESS_TEST(r)      do {} while (0)
0062 #define REG_WIDTH_TEST(r, w)        do {} while (0)
0063 #endif
0064 
0065 /* OHCI compatible registers */
0066 /*
0067  * Note: Some of the ISP1362 'OHCI' registers implement only
0068  * a subset of the bits defined in the OHCI spec.
0069  *
0070  * Bitmasks for the individual bits of these registers are defined in "ohci.h"
0071  */
0072 ISP1362_REG(HCREVISION, 0x00,   REG_WIDTH_32,   REG_ACCESS_R);
0073 ISP1362_REG(HCCONTROL,  0x01,   REG_WIDTH_32,   REG_ACCESS_RW);
0074 ISP1362_REG(HCCMDSTAT,  0x02,   REG_WIDTH_32,   REG_ACCESS_RW);
0075 ISP1362_REG(HCINTSTAT,  0x03,   REG_WIDTH_32,   REG_ACCESS_RW);
0076 ISP1362_REG(HCINTENB,   0x04,   REG_WIDTH_32,   REG_ACCESS_RW);
0077 ISP1362_REG(HCINTDIS,   0x05,   REG_WIDTH_32,   REG_ACCESS_RW);
0078 ISP1362_REG(HCFMINTVL,  0x0d,   REG_WIDTH_32,   REG_ACCESS_RW);
0079 ISP1362_REG(HCFMREM,    0x0e,   REG_WIDTH_32,   REG_ACCESS_RW);
0080 ISP1362_REG(HCFMNUM,    0x0f,   REG_WIDTH_32,   REG_ACCESS_RW);
0081 ISP1362_REG(HCLSTHRESH, 0x11,   REG_WIDTH_32,   REG_ACCESS_RW);
0082 ISP1362_REG(HCRHDESCA,  0x12,   REG_WIDTH_32,   REG_ACCESS_RW);
0083 ISP1362_REG(HCRHDESCB,  0x13,   REG_WIDTH_32,   REG_ACCESS_RW);
0084 ISP1362_REG(HCRHSTATUS, 0x14,   REG_WIDTH_32,   REG_ACCESS_RW);
0085 ISP1362_REG(HCRHPORT1,  0x15,   REG_WIDTH_32,   REG_ACCESS_RW);
0086 ISP1362_REG(HCRHPORT2,  0x16,   REG_WIDTH_32,   REG_ACCESS_RW);
0087 
0088 /* Philips ISP1362 specific registers */
0089 ISP1362_REG(HCHWCFG,    0x20,   REG_WIDTH_16,   REG_ACCESS_RW);
0090 #define HCHWCFG_DISABLE_SUSPEND (1 << 15)
0091 #define HCHWCFG_GLOBAL_PWRDOWN  (1 << 14)
0092 #define HCHWCFG_PULLDOWN_DS2    (1 << 13)
0093 #define HCHWCFG_PULLDOWN_DS1    (1 << 12)
0094 #define HCHWCFG_CLKNOTSTOP  (1 << 11)
0095 #define HCHWCFG_ANALOG_OC   (1 << 10)
0096 #define HCHWCFG_ONEINT      (1 << 9)
0097 #define HCHWCFG_DACK_MODE   (1 << 8)
0098 #define HCHWCFG_ONEDMA      (1 << 7)
0099 #define HCHWCFG_DACK_POL    (1 << 6)
0100 #define HCHWCFG_DREQ_POL    (1 << 5)
0101 #define HCHWCFG_DBWIDTH_MASK    (0x03 << 3)
0102 #define HCHWCFG_DBWIDTH(n)  (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
0103 #define HCHWCFG_INT_POL     (1 << 2)
0104 #define HCHWCFG_INT_TRIGGER (1 << 1)
0105 #define HCHWCFG_INT_ENABLE  (1 << 0)
0106 
0107 ISP1362_REG(HCDMACFG,   0x21,   REG_WIDTH_16,   REG_ACCESS_RW);
0108 #define HCDMACFG_CTR_ENABLE (1 << 7)
0109 #define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
0110 #define HCDMACFG_BURST_LEN(n)   (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
0111 #define HCDMACFG_BURST_LEN_1    HCDMACFG_BURST_LEN(0)
0112 #define HCDMACFG_BURST_LEN_4    HCDMACFG_BURST_LEN(1)
0113 #define HCDMACFG_BURST_LEN_8    HCDMACFG_BURST_LEN(2)
0114 #define HCDMACFG_DMA_ENABLE (1 << 4)
0115 #define HCDMACFG_BUF_TYPE_MASK  (0x07 << 1)
0116 #define HCDMACFG_BUF_TYPE(n)    (((n) << 1) & HCDMACFG_BUF_TYPE_MASK)
0117 #define HCDMACFG_BUF_ISTL0  HCDMACFG_BUF_TYPE(0)
0118 #define HCDMACFG_BUF_ISTL1  HCDMACFG_BUF_TYPE(1)
0119 #define HCDMACFG_BUF_INTL   HCDMACFG_BUF_TYPE(2)
0120 #define HCDMACFG_BUF_ATL    HCDMACFG_BUF_TYPE(3)
0121 #define HCDMACFG_BUF_DIRECT HCDMACFG_BUF_TYPE(4)
0122 #define HCDMACFG_DMA_RW_SELECT  (1 << 0)
0123 
0124 ISP1362_REG(HCXFERCTR,  0x22,   REG_WIDTH_16,   REG_ACCESS_RW);
0125 
0126 ISP1362_REG(HCuPINT,    0x24,   REG_WIDTH_16,   REG_ACCESS_RW);
0127 #define HCuPINT_SOF     (1 << 0)
0128 #define HCuPINT_ISTL0       (1 << 1)
0129 #define HCuPINT_ISTL1       (1 << 2)
0130 #define HCuPINT_EOT     (1 << 3)
0131 #define HCuPINT_OPR     (1 << 4)
0132 #define HCuPINT_SUSP        (1 << 5)
0133 #define HCuPINT_CLKRDY      (1 << 6)
0134 #define HCuPINT_INTL        (1 << 7)
0135 #define HCuPINT_ATL     (1 << 8)
0136 #define HCuPINT_OTG     (1 << 9)
0137 
0138 ISP1362_REG(HCuPINTENB, 0x25,   REG_WIDTH_16,   REG_ACCESS_RW);
0139 /* same bit definitions apply as for HCuPINT */
0140 
0141 ISP1362_REG(HCCHIPID,   0x27,   REG_WIDTH_16,   REG_ACCESS_R);
0142 #define HCCHIPID_MASK       0xff00
0143 #define HCCHIPID_MAGIC      0x3600
0144 
0145 ISP1362_REG(HCSCRATCH,  0x28,   REG_WIDTH_16,   REG_ACCESS_RW);
0146 
0147 ISP1362_REG(HCSWRES,    0x29,   REG_WIDTH_16,   REG_ACCESS_W);
0148 #define HCSWRES_MAGIC       0x00f6
0149 
0150 ISP1362_REG(HCBUFSTAT,  0x2c,   REG_WIDTH_16,   REG_ACCESS_RW);
0151 #define HCBUFSTAT_ISTL0_FULL    (1 << 0)
0152 #define HCBUFSTAT_ISTL1_FULL    (1 << 1)
0153 #define HCBUFSTAT_INTL_ACTIVE   (1 << 2)
0154 #define HCBUFSTAT_ATL_ACTIVE    (1 << 3)
0155 #define HCBUFSTAT_RESET_HWPP    (1 << 4)
0156 #define HCBUFSTAT_ISTL0_ACTIVE  (1 << 5)
0157 #define HCBUFSTAT_ISTL1_ACTIVE  (1 << 6)
0158 #define HCBUFSTAT_ISTL0_DONE    (1 << 8)
0159 #define HCBUFSTAT_ISTL1_DONE    (1 << 9)
0160 #define HCBUFSTAT_PAIRED_PTDPP  (1 << 10)
0161 
0162 ISP1362_REG(HCDIRADDR,  0x32,   REG_WIDTH_32,   REG_ACCESS_RW);
0163 #define HCDIRADDR_ADDR_MASK 0x0000ffff
0164 #define HCDIRADDR_ADDR(n)   (((n) << 0) & HCDIRADDR_ADDR_MASK)
0165 #define HCDIRADDR_COUNT_MASK    0xffff0000
0166 #define HCDIRADDR_COUNT(n)  (((n) << 16) & HCDIRADDR_COUNT_MASK)
0167 ISP1362_REG(HCDIRDATA,  0x45,   REG_WIDTH_16,   REG_ACCESS_RW);
0168 
0169 ISP1362_REG(HCISTLBUFSZ, 0x30,  REG_WIDTH_16,   REG_ACCESS_RW);
0170 ISP1362_REG(HCISTL0PORT, 0x40,  REG_WIDTH_16,   REG_ACCESS_RW);
0171 ISP1362_REG(HCISTL1PORT, 0x42,  REG_WIDTH_16,   REG_ACCESS_RW);
0172 ISP1362_REG(HCISTLRATE, 0x47,   REG_WIDTH_16,   REG_ACCESS_RW);
0173 
0174 ISP1362_REG(HCINTLBUFSZ, 0x33,  REG_WIDTH_16,   REG_ACCESS_RW);
0175 ISP1362_REG(HCINTLPORT, 0x43,   REG_WIDTH_16,   REG_ACCESS_RW);
0176 ISP1362_REG(HCINTLBLKSZ, 0x53,  REG_WIDTH_16,   REG_ACCESS_RW);
0177 ISP1362_REG(HCINTLDONE, 0x17,   REG_WIDTH_32,   REG_ACCESS_R);
0178 ISP1362_REG(HCINTLSKIP, 0x18,   REG_WIDTH_32,   REG_ACCESS_RW);
0179 ISP1362_REG(HCINTLLAST, 0x19,   REG_WIDTH_32,   REG_ACCESS_RW);
0180 ISP1362_REG(HCINTLCURR, 0x1a,   REG_WIDTH_16,   REG_ACCESS_R);
0181 
0182 ISP1362_REG(HCATLBUFSZ, 0x34,   REG_WIDTH_16,   REG_ACCESS_RW);
0183 ISP1362_REG(HCATLPORT,  0x44,   REG_WIDTH_16,   REG_ACCESS_RW);
0184 ISP1362_REG(HCATLBLKSZ, 0x54,   REG_WIDTH_16,   REG_ACCESS_RW);
0185 ISP1362_REG(HCATLDONE,  0x1b,   REG_WIDTH_32,   REG_ACCESS_R);
0186 ISP1362_REG(HCATLSKIP,  0x1c,   REG_WIDTH_32,   REG_ACCESS_RW);
0187 ISP1362_REG(HCATLLAST,  0x1d,   REG_WIDTH_32,   REG_ACCESS_RW);
0188 ISP1362_REG(HCATLCURR,  0x1e,   REG_WIDTH_16,   REG_ACCESS_R);
0189 
0190 ISP1362_REG(HCATLDTC,   0x51,   REG_WIDTH_16,   REG_ACCESS_RW);
0191 ISP1362_REG(HCATLDTCTO, 0x52,   REG_WIDTH_16,   REG_ACCESS_RW);
0192 
0193 
0194 ISP1362_REG(OTGCONTROL, 0x62,   REG_WIDTH_16,   REG_ACCESS_RW);
0195 ISP1362_REG(OTGSTATUS,  0x67,   REG_WIDTH_16,   REG_ACCESS_R);
0196 ISP1362_REG(OTGINT, 0x68,   REG_WIDTH_16,   REG_ACCESS_RW);
0197 ISP1362_REG(OTGINTENB,  0x69,   REG_WIDTH_16,   REG_ACCESS_RW);
0198 ISP1362_REG(OTGTIMER,   0x6A,   REG_WIDTH_16,   REG_ACCESS_RW);
0199 ISP1362_REG(OTGALTTMR,  0x6C,   REG_WIDTH_16,   REG_ACCESS_RW);
0200 
0201 /* Philips transfer descriptor, cpu-endian */
0202 struct ptd {
0203     u16 count;
0204 #define PTD_COUNT_MSK   (0x3ff << 0)
0205 #define PTD_TOGGLE_MSK  (1 << 10)
0206 #define PTD_ACTIVE_MSK  (1 << 11)
0207 #define PTD_CC_MSK  (0xf << 12)
0208     u16 mps;
0209 #define PTD_MPS_MSK (0x3ff << 0)
0210 #define PTD_SPD_MSK (1 << 10)
0211 #define PTD_LAST_MSK    (1 << 11)
0212 #define PTD_EP_MSK  (0xf << 12)
0213     u16 len;
0214 #define PTD_LEN_MSK (0x3ff << 0)
0215 #define PTD_DIR_MSK (3 << 10)
0216 #define PTD_DIR_SETUP   (0)
0217 #define PTD_DIR_OUT (1)
0218 #define PTD_DIR_IN  (2)
0219     u16 faddr;
0220 #define PTD_FA_MSK  (0x7f << 0)
0221 /* PTD Byte 7: [StartingFrame (if ISO PTD) | StartingFrame[0..4], PollingRate[0..2] (if INT PTD)] */
0222 #define PTD_SF_ISO_MSK  (0xff << 8)
0223 #define PTD_SF_INT_MSK  (0x1f << 8)
0224 #define PTD_PR_MSK  (0x07 << 13)
0225 } __attribute__ ((packed, aligned(2)));
0226 #define PTD_HEADER_SIZE sizeof(struct ptd)
0227 
0228 /* ------------------------------------------------------------------------- */
0229 /* Copied from ohci.h: */
0230 /*
0231  * Hardware transfer status codes -- CC from PTD
0232  */
0233 #define PTD_CC_NOERROR      0x00
0234 #define PTD_CC_CRC          0x01
0235 #define PTD_CC_BITSTUFFING  0x02
0236 #define PTD_CC_DATATOGGLEM  0x03
0237 #define PTD_CC_STALL        0x04
0238 #define PTD_DEVNOTRESP      0x05
0239 #define PTD_PIDCHECKFAIL    0x06
0240 #define PTD_UNEXPECTEDPID   0x07
0241 #define PTD_DATAOVERRUN     0x08
0242 #define PTD_DATAUNDERRUN    0x09
0243     /* 0x0A, 0x0B reserved for hardware */
0244 #define PTD_BUFFEROVERRUN   0x0C
0245 #define PTD_BUFFERUNDERRUN  0x0D
0246     /* 0x0E, 0x0F reserved for HCD */
0247 #define PTD_NOTACCESSED     0x0F
0248 
0249 
0250 /* map OHCI TD status codes (CC) to errno values */
0251 static const int cc_to_error[16] = {
0252     /* No  Error  */               0,
0253     /* CRC Error  */               -EILSEQ,
0254     /* Bit Stuff  */               -EPROTO,
0255     /* Data Togg  */               -EILSEQ,
0256     /* Stall      */               -EPIPE,
0257     /* DevNotResp */               -ETIMEDOUT,
0258     /* PIDCheck   */               -EPROTO,
0259     /* UnExpPID   */               -EPROTO,
0260     /* DataOver   */               -EOVERFLOW,
0261     /* DataUnder  */               -EREMOTEIO,
0262     /* (for hw)   */               -EIO,
0263     /* (for hw)   */               -EIO,
0264     /* BufferOver */               -ECOMM,
0265     /* BuffUnder  */               -ENOSR,
0266     /* (for HCD)  */               -EALREADY,
0267     /* (for HCD)  */               -EALREADY
0268 };
0269 
0270 
0271 /*
0272  * HcControl (control) register masks
0273  */
0274 #define OHCI_CTRL_HCFS  (3 << 6)    /* host controller functional state */
0275 #define OHCI_CTRL_RWC   (1 << 9)    /* remote wakeup connected */
0276 #define OHCI_CTRL_RWE   (1 << 10)   /* remote wakeup enable */
0277 
0278 /* pre-shifted values for HCFS */
0279 #   define OHCI_USB_RESET   (0 << 6)
0280 #   define OHCI_USB_RESUME  (1 << 6)
0281 #   define OHCI_USB_OPER    (2 << 6)
0282 #   define OHCI_USB_SUSPEND (3 << 6)
0283 
0284 /*
0285  * HcCommandStatus (cmdstatus) register masks
0286  */
0287 #define OHCI_HCR    (1 << 0)    /* host controller reset */
0288 #define OHCI_SOC    (3 << 16)   /* scheduling overrun count */
0289 
0290 /*
0291  * masks used with interrupt registers:
0292  * HcInterruptStatus (intrstatus)
0293  * HcInterruptEnable (intrenable)
0294  * HcInterruptDisable (intrdisable)
0295  */
0296 #define OHCI_INTR_SO    (1 << 0)    /* scheduling overrun */
0297 #define OHCI_INTR_WDH   (1 << 1)    /* writeback of done_head */
0298 #define OHCI_INTR_SF    (1 << 2)    /* start frame */
0299 #define OHCI_INTR_RD    (1 << 3)    /* resume detect */
0300 #define OHCI_INTR_UE    (1 << 4)    /* unrecoverable error */
0301 #define OHCI_INTR_FNO   (1 << 5)    /* frame number overflow */
0302 #define OHCI_INTR_RHSC  (1 << 6)    /* root hub status change */
0303 #define OHCI_INTR_OC    (1 << 30)   /* ownership change */
0304 #define OHCI_INTR_MIE   (1 << 31)   /* master interrupt enable */
0305 
0306 /* roothub.portstatus [i] bits */
0307 #define RH_PS_CCS            0x00000001     /* current connect status */
0308 #define RH_PS_PES            0x00000002     /* port enable status*/
0309 #define RH_PS_PSS            0x00000004     /* port suspend status */
0310 #define RH_PS_POCI           0x00000008     /* port over current indicator */
0311 #define RH_PS_PRS            0x00000010     /* port reset status */
0312 #define RH_PS_PPS            0x00000100     /* port power status */
0313 #define RH_PS_LSDA           0x00000200     /* low speed device attached */
0314 #define RH_PS_CSC            0x00010000     /* connect status change */
0315 #define RH_PS_PESC           0x00020000     /* port enable status change */
0316 #define RH_PS_PSSC           0x00040000     /* port suspend status change */
0317 #define RH_PS_OCIC           0x00080000     /* over current indicator change */
0318 #define RH_PS_PRSC           0x00100000     /* port reset status change */
0319 
0320 /* roothub.status bits */
0321 #define RH_HS_LPS        0x00000001     /* local power status */
0322 #define RH_HS_OCI        0x00000002     /* over current indicator */
0323 #define RH_HS_DRWE       0x00008000     /* device remote wakeup enable */
0324 #define RH_HS_LPSC       0x00010000     /* local power status change */
0325 #define RH_HS_OCIC       0x00020000     /* over current indicator change */
0326 #define RH_HS_CRWE       0x80000000     /* clear remote wakeup enable */
0327 
0328 /* roothub.b masks */
0329 #define RH_B_DR     0x0000ffff      /* device removable flags */
0330 #define RH_B_PPCM   0xffff0000      /* port power control mask */
0331 
0332 /* roothub.a masks */
0333 #define RH_A_NDP    (0xff << 0)     /* number of downstream ports */
0334 #define RH_A_PSM    (1 << 8)        /* power switching mode */
0335 #define RH_A_NPS    (1 << 9)        /* no power switching */
0336 #define RH_A_DT     (1 << 10)       /* device type (mbz) */
0337 #define RH_A_OCPM   (1 << 11)       /* over current protection mode */
0338 #define RH_A_NOCP   (1 << 12)       /* no over current protection */
0339 #define RH_A_POTPGT (0xff << 24)        /* power on to power good time */
0340 
0341 #define FI          0x2edf      /* 12000 bits per frame (-1) */
0342 #define FSMP(fi)        (0x7fff & ((6 * ((fi) - 210)) / 7))
0343 #define LSTHRESH        0x628       /* lowspeed bit threshold */
0344 
0345 /* ------------------------------------------------------------------------- */
0346 
0347 /* PTD accessor macros. */
0348 #define PTD_GET_COUNT(p)    (((p)->count & PTD_COUNT_MSK) >> 0)
0349 #define PTD_COUNT(v)        (((v) << 0) & PTD_COUNT_MSK)
0350 #define PTD_GET_TOGGLE(p)   (((p)->count & PTD_TOGGLE_MSK) >> 10)
0351 #define PTD_TOGGLE(v)       (((v) << 10) & PTD_TOGGLE_MSK)
0352 #define PTD_GET_ACTIVE(p)   (((p)->count & PTD_ACTIVE_MSK) >> 11)
0353 #define PTD_ACTIVE(v)       (((v) << 11) & PTD_ACTIVE_MSK)
0354 #define PTD_GET_CC(p)       (((p)->count & PTD_CC_MSK) >> 12)
0355 #define PTD_CC(v)       (((v) << 12) & PTD_CC_MSK)
0356 #define PTD_GET_MPS(p)      (((p)->mps & PTD_MPS_MSK) >> 0)
0357 #define PTD_MPS(v)      (((v) << 0) & PTD_MPS_MSK)
0358 #define PTD_GET_SPD(p)      (((p)->mps & PTD_SPD_MSK) >> 10)
0359 #define PTD_SPD(v)      (((v) << 10) & PTD_SPD_MSK)
0360 #define PTD_GET_LAST(p)     (((p)->mps & PTD_LAST_MSK) >> 11)
0361 #define PTD_LAST(v)     (((v) << 11) & PTD_LAST_MSK)
0362 #define PTD_GET_EP(p)       (((p)->mps & PTD_EP_MSK) >> 12)
0363 #define PTD_EP(v)       (((v) << 12) & PTD_EP_MSK)
0364 #define PTD_GET_LEN(p)      (((p)->len & PTD_LEN_MSK) >> 0)
0365 #define PTD_LEN(v)      (((v) << 0) & PTD_LEN_MSK)
0366 #define PTD_GET_DIR(p)      (((p)->len & PTD_DIR_MSK) >> 10)
0367 #define PTD_DIR(v)      (((v) << 10) & PTD_DIR_MSK)
0368 #define PTD_GET_FA(p)       (((p)->faddr & PTD_FA_MSK) >> 0)
0369 #define PTD_FA(v)       (((v) << 0) & PTD_FA_MSK)
0370 #define PTD_GET_SF_INT(p)   (((p)->faddr & PTD_SF_INT_MSK) >> 8)
0371 #define PTD_SF_INT(v)       (((v) << 8) & PTD_SF_INT_MSK)
0372 #define PTD_GET_SF_ISO(p)   (((p)->faddr & PTD_SF_ISO_MSK) >> 8)
0373 #define PTD_SF_ISO(v)       (((v) << 8) & PTD_SF_ISO_MSK)
0374 #define PTD_GET_PR(p)       (((p)->faddr & PTD_PR_MSK) >> 13)
0375 #define PTD_PR(v)       (((v) << 13) & PTD_PR_MSK)
0376 
0377 #define LOG2_PERIODIC_SIZE  5   /* arbitrary; this matches OHCI */
0378 #define PERIODIC_SIZE       (1 << LOG2_PERIODIC_SIZE)
0379 
0380 struct isp1362_ep {
0381     struct usb_host_endpoint *hep;
0382     struct usb_device   *udev;
0383 
0384     /* philips transfer descriptor */
0385     struct ptd      ptd;
0386 
0387     u8          maxpacket;
0388     u8          epnum;
0389     u8          nextpid;
0390     u16         error_count;
0391     u16         length;     /* of current packet */
0392     s16         ptd_offset; /* buffer offset in ISP1362 where
0393                            PTD has been stored
0394                            (for access thru HCDIRDATA) */
0395     int         ptd_index;
0396     int num_ptds;
0397     void            *data;      /* to databuf */
0398     /* queue of active EPs (the ones transmitted to the chip) */
0399     struct list_head    active;
0400 
0401     /* periodic schedule */
0402     u8          branch;
0403     u16         interval;
0404     u16         load;
0405     u16         last_iso;
0406 
0407     /* async schedule */
0408     struct list_head    schedule;   /* list of all EPs that need processing */
0409     struct list_head    remove_list;
0410     int         num_req;
0411 };
0412 
0413 struct isp1362_ep_queue {
0414     struct list_head    active;     /* list of PTDs currently processed by HC */
0415     atomic_t        finishing;
0416     unsigned long       buf_map;
0417     unsigned long       skip_map;
0418     int         free_ptd;
0419     u16         buf_start;
0420     u16         buf_size;
0421     u16         blk_size;   /* PTD buffer block size for ATL and INTL */
0422     u8          buf_count;
0423     u8          buf_avail;
0424     char            name[16];
0425 
0426     /* for statistical tracking */
0427     u8          stat_maxptds;   /* Max # of ptds seen simultaneously in fifo */
0428     u8          ptd_count;  /* number of ptds submitted to this queue */
0429 };
0430 
0431 struct isp1362_hcd {
0432     spinlock_t      lock;
0433     void __iomem        *addr_reg;
0434     void __iomem        *data_reg;
0435 
0436     struct isp1362_platform_data *board;
0437 
0438     unsigned long       stat1, stat2, stat4, stat8, stat16;
0439 
0440     /* HC registers */
0441     u32         intenb;     /* "OHCI" interrupts */
0442     u16         irqenb;     /* uP interrupts */
0443 
0444     /* Root hub registers */
0445     u32         rhdesca;
0446     u32         rhdescb;
0447     u32         rhstatus;
0448     u32         rhport[MAX_ROOT_PORTS];
0449     unsigned long       next_statechange;
0450 
0451     /* HC control reg shadow copy */
0452     u32         hc_control;
0453 
0454     /* async schedule: control, bulk */
0455     struct list_head    async;
0456 
0457     /* periodic schedule: int */
0458     u16         load[PERIODIC_SIZE];
0459     struct list_head    periodic;
0460     u16         fmindex;
0461 
0462     /* periodic schedule: isochronous */
0463     struct list_head    isoc;
0464     unsigned int        istl_flip:1;
0465     unsigned int        irq_active:1;
0466 
0467     /* Schedules for the current frame */
0468     struct isp1362_ep_queue atl_queue;
0469     struct isp1362_ep_queue intl_queue;
0470     struct isp1362_ep_queue istl_queue[2];
0471 
0472     /* list of PTDs retrieved from HC */
0473     struct list_head    remove_list;
0474     enum {
0475         ISP1362_INT_SOF,
0476         ISP1362_INT_ISTL0,
0477         ISP1362_INT_ISTL1,
0478         ISP1362_INT_EOT,
0479         ISP1362_INT_OPR,
0480         ISP1362_INT_SUSP,
0481         ISP1362_INT_CLKRDY,
0482         ISP1362_INT_INTL,
0483         ISP1362_INT_ATL,
0484         ISP1362_INT_OTG,
0485         NUM_ISP1362_IRQS
0486     } IRQ_NAMES;
0487     unsigned int        irq_stat[NUM_ISP1362_IRQS];
0488     int         req_serial;
0489 };
0490 
0491 static inline const char *ISP1362_INT_NAME(int n)
0492 {
0493     switch (n) {
0494     case ISP1362_INT_SOF:    return "SOF";
0495     case ISP1362_INT_ISTL0:  return "ISTL0";
0496     case ISP1362_INT_ISTL1:  return "ISTL1";
0497     case ISP1362_INT_EOT:    return "EOT";
0498     case ISP1362_INT_OPR:    return "OPR";
0499     case ISP1362_INT_SUSP:   return "SUSP";
0500     case ISP1362_INT_CLKRDY: return "CLKRDY";
0501     case ISP1362_INT_INTL:   return "INTL";
0502     case ISP1362_INT_ATL:    return "ATL";
0503     case ISP1362_INT_OTG:    return "OTG";
0504     default:                 return "unknown";
0505     }
0506 }
0507 
0508 static inline void ALIGNSTAT(struct isp1362_hcd *isp1362_hcd, void *ptr)
0509 {
0510     unsigned long p = (unsigned long)ptr;
0511     if (!(p & 0xf))
0512         isp1362_hcd->stat16++;
0513     else if (!(p & 0x7))
0514         isp1362_hcd->stat8++;
0515     else if (!(p & 0x3))
0516         isp1362_hcd->stat4++;
0517     else if (!(p & 0x1))
0518         isp1362_hcd->stat2++;
0519     else
0520         isp1362_hcd->stat1++;
0521 }
0522 
0523 static inline struct isp1362_hcd *hcd_to_isp1362_hcd(struct usb_hcd *hcd)
0524 {
0525     return (struct isp1362_hcd *) (hcd->hcd_priv);
0526 }
0527 
0528 static inline struct usb_hcd *isp1362_hcd_to_hcd(struct isp1362_hcd *isp1362_hcd)
0529 {
0530     return container_of((void *)isp1362_hcd, struct usb_hcd, hcd_priv);
0531 }
0532 
0533 #define frame_before(f1, f2)    ((s16)((u16)f1 - (u16)f2) < 0)
0534 
0535 /*
0536  * ISP1362 HW Interface
0537  */
0538 
0539 #define DBG(level, fmt...) \
0540     do { \
0541         if (dbg_level > level) \
0542             pr_debug(fmt); \
0543     } while (0)
0544 
0545 #ifdef VERBOSE
0546 #    define VDBG(fmt...)    DBG(3, fmt)
0547 #else
0548 #    define VDBG(fmt...)    do {} while (0)
0549 #endif
0550 
0551 #ifdef REGISTERS
0552 #    define RDBG(fmt...)    DBG(1, fmt)
0553 #else
0554 #    define RDBG(fmt...)    do {} while (0)
0555 #endif
0556 
0557 #ifdef URB_TRACE
0558 #define URB_DBG(fmt...)     DBG(0, fmt)
0559 #else
0560 #define URB_DBG(fmt...)     do {} while (0)
0561 #endif
0562 
0563 
0564 #if USE_PLATFORM_DELAY
0565 #if USE_NDELAY
0566 #error USE_PLATFORM_DELAY and USE_NDELAY defined simultaneously.
0567 #endif
0568 #define isp1362_delay(h, d) (h)->board->delay(isp1362_hcd_to_hcd(h)->self.controller, d)
0569 #elif USE_NDELAY
0570 #define isp1362_delay(h, d) ndelay(d)
0571 #else
0572 #define isp1362_delay(h, d) do {} while (0)
0573 #endif
0574 
0575 #define get_urb(ep) ({                          \
0576     BUG_ON(list_empty(&ep->hep->urb_list));             \
0577     container_of(ep->hep->urb_list.next, struct urb, urb_list); \
0578 })
0579 
0580 /* basic access functions for ISP1362 chip registers */
0581 /* NOTE: The contents of the address pointer register cannot be read back! The driver must ensure,
0582  * that all register accesses are performed with interrupts disabled, since the interrupt
0583  * handler has no way of restoring the previous state.
0584  */
0585 static void isp1362_write_addr(struct isp1362_hcd *isp1362_hcd, isp1362_reg_t reg)
0586 {
0587     REG_ACCESS_TEST(reg);
0588     DUMMY_DELAY_ACCESS;
0589     writew(ISP1362_REG_NO(reg), isp1362_hcd->addr_reg);
0590     DUMMY_DELAY_ACCESS;
0591     isp1362_delay(isp1362_hcd, 1);
0592 }
0593 
0594 static void isp1362_write_data16(struct isp1362_hcd *isp1362_hcd, u16 val)
0595 {
0596     DUMMY_DELAY_ACCESS;
0597     writew(val, isp1362_hcd->data_reg);
0598 }
0599 
0600 static u16 isp1362_read_data16(struct isp1362_hcd *isp1362_hcd)
0601 {
0602     u16 val;
0603 
0604     DUMMY_DELAY_ACCESS;
0605     val = readw(isp1362_hcd->data_reg);
0606 
0607     return val;
0608 }
0609 
0610 static void isp1362_write_data32(struct isp1362_hcd *isp1362_hcd, u32 val)
0611 {
0612 #if USE_32BIT
0613     DUMMY_DELAY_ACCESS;
0614     writel(val, isp1362_hcd->data_reg);
0615 #else
0616     DUMMY_DELAY_ACCESS;
0617     writew((u16)val, isp1362_hcd->data_reg);
0618     DUMMY_DELAY_ACCESS;
0619     writew(val >> 16, isp1362_hcd->data_reg);
0620 #endif
0621 }
0622 
0623 static u32 isp1362_read_data32(struct isp1362_hcd *isp1362_hcd)
0624 {
0625     u32 val;
0626 
0627 #if USE_32BIT
0628     DUMMY_DELAY_ACCESS;
0629     val = readl(isp1362_hcd->data_reg);
0630 #else
0631     DUMMY_DELAY_ACCESS;
0632     val = (u32)readw(isp1362_hcd->data_reg);
0633     DUMMY_DELAY_ACCESS;
0634     val |= (u32)readw(isp1362_hcd->data_reg) << 16;
0635 #endif
0636     return val;
0637 }
0638 
0639 /* use readsw/writesw to access the fifo whenever possible */
0640 /* assume HCDIRDATA or XFERCTR & addr_reg have been set up */
0641 static void isp1362_read_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len)
0642 {
0643     u8 *dp = buf;
0644     u16 data;
0645 
0646     if (!len)
0647         return;
0648 
0649     RDBG("%s: Reading %d byte from fifo to mem @ %p\n", __func__, len, buf);
0650 #if USE_32BIT
0651     if (len >= 4) {
0652         RDBG("%s: Using readsl for %d dwords\n", __func__, len >> 2);
0653         readsl(isp1362_hcd->data_reg, dp, len >> 2);
0654         dp += len & ~3;
0655         len &= 3;
0656     }
0657 #endif
0658     if (len >= 2) {
0659         RDBG("%s: Using readsw for %d words\n", __func__, len >> 1);
0660         insw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1);
0661         dp += len & ~1;
0662         len &= 1;
0663     }
0664 
0665     BUG_ON(len & ~1);
0666     if (len > 0) {
0667         data = isp1362_read_data16(isp1362_hcd);
0668         RDBG("%s: Reading trailing byte %02x to mem @ %08x\n", __func__,
0669              (u8)data, (u32)dp);
0670         *dp = (u8)data;
0671     }
0672 }
0673 
0674 static void isp1362_write_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len)
0675 {
0676     u8 *dp = buf;
0677     u16 data;
0678 
0679     if (!len)
0680         return;
0681 
0682     if ((unsigned long)dp & 0x1) {
0683         /* not aligned */
0684         for (; len > 1; len -= 2) {
0685             data = *dp++;
0686             data |= *dp++ << 8;
0687             isp1362_write_data16(isp1362_hcd, data);
0688         }
0689         if (len)
0690             isp1362_write_data16(isp1362_hcd, *dp);
0691         return;
0692     }
0693 
0694     RDBG("%s: Writing %d byte to fifo from memory @%p\n", __func__, len, buf);
0695 #if USE_32BIT
0696     if (len >= 4) {
0697         RDBG("%s: Using writesl for %d dwords\n", __func__, len >> 2);
0698         writesl(isp1362_hcd->data_reg, dp, len >> 2);
0699         dp += len & ~3;
0700         len &= 3;
0701     }
0702 #endif
0703     if (len >= 2) {
0704         RDBG("%s: Using writesw for %d words\n", __func__, len >> 1);
0705         outsw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1);
0706         dp += len & ~1;
0707         len &= 1;
0708     }
0709 
0710     BUG_ON(len & ~1);
0711     if (len > 0) {
0712         /* finally write any trailing byte; we don't need to care
0713          * about the high byte of the last word written
0714          */
0715         data = (u16)*dp;
0716         RDBG("%s: Sending trailing byte %02x from mem @ %08x\n", __func__,
0717             data, (u32)dp);
0718         isp1362_write_data16(isp1362_hcd, data);
0719     }
0720 }
0721 
0722 #define isp1362_read_reg16(d, r)        ({          \
0723     u16 __v;                            \
0724     REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16);          \
0725     isp1362_write_addr(d, ISP1362_REG_##r);             \
0726     __v = isp1362_read_data16(d);                   \
0727     RDBG("%s: Read %04x from %s[%02x]\n", __func__, __v, #r,    \
0728          ISP1362_REG_NO(ISP1362_REG_##r));              \
0729     __v;                                \
0730 })
0731 
0732 #define isp1362_read_reg32(d, r)        ({          \
0733     u32 __v;                            \
0734     REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32);          \
0735     isp1362_write_addr(d, ISP1362_REG_##r);             \
0736     __v = isp1362_read_data32(d);                   \
0737     RDBG("%s: Read %08x from %s[%02x]\n", __func__, __v, #r,    \
0738          ISP1362_REG_NO(ISP1362_REG_##r));              \
0739     __v;                                \
0740 })
0741 
0742 #define isp1362_write_reg16(d, r, v)    {                   \
0743     REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16);              \
0744     isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET);    \
0745     isp1362_write_data16(d, (u16)(v));                  \
0746     RDBG("%s: Wrote %04x to %s[%02x]\n", __func__, (u16)(v), #r,    \
0747          ISP1362_REG_NO(ISP1362_REG_##r));                  \
0748 }
0749 
0750 #define isp1362_write_reg32(d, r, v)    {                   \
0751     REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32);              \
0752     isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET);    \
0753     isp1362_write_data32(d, (u32)(v));                  \
0754     RDBG("%s: Wrote %08x to %s[%02x]\n", __func__, (u32)(v), #r,    \
0755          ISP1362_REG_NO(ISP1362_REG_##r));                  \
0756 }
0757 
0758 #define isp1362_set_mask16(d, r, m) {           \
0759     u16 __v;                    \
0760     __v = isp1362_read_reg16(d, r);         \
0761     if ((__v | m) != __v)               \
0762         isp1362_write_reg16(d, r, __v | m); \
0763 }
0764 
0765 #define isp1362_clr_mask16(d, r, m) {           \
0766     u16 __v;                    \
0767     __v = isp1362_read_reg16(d, r);         \
0768     if ((__v & ~m) != __v)          \
0769         isp1362_write_reg16(d, r, __v & ~m);    \
0770 }
0771 
0772 #define isp1362_set_mask32(d, r, m) {           \
0773     u32 __v;                    \
0774     __v = isp1362_read_reg32(d, r);         \
0775     if ((__v | m) != __v)               \
0776         isp1362_write_reg32(d, r, __v | m); \
0777 }
0778 
0779 #define isp1362_clr_mask32(d, r, m) {           \
0780     u32 __v;                    \
0781     __v = isp1362_read_reg32(d, r);         \
0782     if ((__v & ~m) != __v)          \
0783         isp1362_write_reg32(d, r, __v & ~m);    \
0784 }
0785 
0786 #define isp1362_show_reg(d, r) {                                \
0787     if ((ISP1362_REG_##r & REG_WIDTH_MASK) == REG_WIDTH_32)         \
0788         DBG(0, "%-12s[%02x]: %08x\n", #r,                   \
0789             ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg32(d, r)); \
0790     else                                    \
0791         DBG(0, "%-12s[%02x]:     %04x\n", #r,                   \
0792             ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg16(d, r)); \
0793 }
0794 
0795 static void isp1362_write_diraddr(struct isp1362_hcd *isp1362_hcd, u16 offset, u16 len)
0796 {
0797     len = (len + 1) & ~1;
0798 
0799     isp1362_clr_mask16(isp1362_hcd, HCDMACFG, HCDMACFG_CTR_ENABLE);
0800     isp1362_write_reg32(isp1362_hcd, HCDIRADDR,
0801                 HCDIRADDR_ADDR(offset) | HCDIRADDR_COUNT(len));
0802 }
0803 
0804 static void isp1362_read_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len)
0805 {
0806     isp1362_write_diraddr(isp1362_hcd, offset, len);
0807 
0808     DBG(3, "%s: Reading %d byte from buffer @%04x to memory @ %p\n",
0809         __func__, len, offset, buf);
0810 
0811     isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
0812 
0813     isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA);
0814 
0815     isp1362_read_fifo(isp1362_hcd, buf, len);
0816     isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
0817 }
0818 
0819 static void isp1362_write_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len)
0820 {
0821     isp1362_write_diraddr(isp1362_hcd, offset, len);
0822 
0823     DBG(3, "%s: Writing %d byte to buffer @%04x from memory @ %p\n",
0824         __func__, len, offset, buf);
0825 
0826     isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
0827 
0828     isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA | ISP1362_REG_WRITE_OFFSET);
0829     isp1362_write_fifo(isp1362_hcd, buf, len);
0830 
0831     isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
0832 }
0833 
0834 static void __attribute__((unused)) dump_data(char *buf, int len)
0835 {
0836     if (dbg_level > 0) {
0837         int k;
0838         int lf = 0;
0839 
0840         for (k = 0; k < len; ++k) {
0841             if (!lf)
0842                 DBG(0, "%04x:", k);
0843             printk(" %02x", ((u8 *) buf)[k]);
0844             lf = 1;
0845             if (!k)
0846                 continue;
0847             if (k % 16 == 15) {
0848                 printk("\n");
0849                 lf = 0;
0850                 continue;
0851             }
0852             if (k % 8 == 7)
0853                 printk(" ");
0854             if (k % 4 == 3)
0855                 printk(" ");
0856         }
0857         if (lf)
0858             printk("\n");
0859     }
0860 }
0861 
0862 #if defined(PTD_TRACE)
0863 
0864 static void dump_ptd(struct ptd *ptd)
0865 {
0866     DBG(0, "EP %p: CC=%x EP=%d DIR=%x CNT=%d LEN=%d MPS=%d TGL=%x ACT=%x FA=%d SPD=%x SF=%x PR=%x LST=%x\n",
0867         container_of(ptd, struct isp1362_ep, ptd),
0868         PTD_GET_CC(ptd), PTD_GET_EP(ptd), PTD_GET_DIR(ptd),
0869         PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
0870         PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd), PTD_GET_FA(ptd),
0871         PTD_GET_SPD(ptd), PTD_GET_SF_INT(ptd), PTD_GET_PR(ptd), PTD_GET_LAST(ptd));
0872     DBG(0, "  %04x %04x %04x %04x\n", ptd->count, ptd->mps, ptd->len, ptd->faddr);
0873 }
0874 
0875 static void dump_ptd_out_data(struct ptd *ptd, u8 *buf)
0876 {
0877     if (dbg_level > 0) {
0878         if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) {
0879             DBG(0, "--out->\n");
0880             dump_data(buf, PTD_GET_LEN(ptd));
0881         }
0882     }
0883 }
0884 
0885 static void dump_ptd_in_data(struct ptd *ptd, u8 *buf)
0886 {
0887     if (dbg_level > 0) {
0888         if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) {
0889             DBG(0, "<--in--\n");
0890             dump_data(buf, PTD_GET_COUNT(ptd));
0891         }
0892         DBG(0, "-----\n");
0893     }
0894 }
0895 
0896 static void dump_ptd_queue(struct isp1362_ep_queue *epq)
0897 {
0898     struct isp1362_ep *ep;
0899     int dbg = dbg_level;
0900 
0901     dbg_level = 1;
0902     list_for_each_entry(ep, &epq->active, active) {
0903         dump_ptd(&ep->ptd);
0904         dump_data(ep->data, ep->length);
0905     }
0906     dbg_level = dbg;
0907 }
0908 #else
0909 #define dump_ptd(ptd)           do {} while (0)
0910 #define dump_ptd_in_data(ptd, buf)  do {} while (0)
0911 #define dump_ptd_out_data(ptd, buf) do {} while (0)
0912 #define dump_ptd_data(ptd, buf)     do {} while (0)
0913 #define dump_ptd_queue(epq)     do {} while (0)
0914 #endif
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