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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * ISP116x register declarations and HCD data structures
0004  *
0005  * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
0006  * Portions:
0007  * Copyright (C) 2004 Lothar Wassmann
0008  * Copyright (C) 2004 Psion Teklogix
0009  * Copyright (C) 2004 David Brownell
0010  */
0011 
0012 /* us of 1ms frame */
0013 #define  MAX_LOAD_LIMIT     850
0014 
0015 /* Full speed: max # of bytes to transfer for a single urb
0016    at a time must be < 1024 && must be multiple of 64.
0017    832 allows transferring 4kiB within 5 frames. */
0018 #define MAX_TRANSFER_SIZE_FULLSPEED 832
0019 
0020 /* Low speed: there is no reason to schedule in very big
0021    chunks; often the requested long transfers are for
0022    string descriptors containing short strings. */
0023 #define MAX_TRANSFER_SIZE_LOWSPEED  64
0024 
0025 /* Bytetime (us), a rough indication of how much time it
0026    would take to transfer a byte of useful data over USB */
0027 #define BYTE_TIME_FULLSPEED 1
0028 #define BYTE_TIME_LOWSPEED  20
0029 
0030 /* Buffer sizes */
0031 #define ISP116x_BUF_SIZE    4096
0032 #define ISP116x_ITL_BUFSIZE 0
0033 #define ISP116x_ATL_BUFSIZE ((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
0034 
0035 #define ISP116x_WRITE_OFFSET    0x80
0036 
0037 /*------------ ISP116x registers/bits ------------*/
0038 #define HCREVISION  0x00
0039 #define HCCONTROL   0x01
0040 #define     HCCONTROL_HCFS  (3 << 6)    /* host controller
0041                            functional state */
0042 #define     HCCONTROL_USB_RESET (0 << 6)
0043 #define     HCCONTROL_USB_RESUME    (1 << 6)
0044 #define     HCCONTROL_USB_OPER  (2 << 6)
0045 #define     HCCONTROL_USB_SUSPEND   (3 << 6)
0046 #define     HCCONTROL_RWC   (1 << 9)    /* remote wakeup connected */
0047 #define     HCCONTROL_RWE   (1 << 10)   /* remote wakeup enable */
0048 #define HCCMDSTAT   0x02
0049 #define     HCCMDSTAT_HCR   (1 << 0)    /* host controller reset */
0050 #define     HCCMDSTAT_SOC   (3 << 16)   /* scheduling overrun count */
0051 #define HCINTSTAT   0x03
0052 #define     HCINT_SO    (1 << 0)    /* scheduling overrun */
0053 #define     HCINT_WDH   (1 << 1)    /* writeback of done_head */
0054 #define     HCINT_SF    (1 << 2)    /* start frame */
0055 #define     HCINT_RD    (1 << 3)    /* resume detect */
0056 #define     HCINT_UE    (1 << 4)    /* unrecoverable error */
0057 #define     HCINT_FNO   (1 << 5)    /* frame number overflow */
0058 #define     HCINT_RHSC  (1 << 6)    /* root hub status change */
0059 #define     HCINT_OC    (1 << 30)   /* ownership change */
0060 #define     HCINT_MIE   (1 << 31)   /* master interrupt enable */
0061 #define HCINTENB    0x04
0062 #define HCINTDIS    0x05
0063 #define HCFMINTVL   0x0d
0064 #define HCFMREM     0x0e
0065 #define HCFMNUM     0x0f
0066 #define HCLSTHRESH  0x11
0067 #define HCRHDESCA   0x12
0068 #define     RH_A_NDP    (0x3 << 0)  /* # downstream ports */
0069 #define     RH_A_PSM    (1 << 8)    /* power switching mode */
0070 #define     RH_A_NPS    (1 << 9)    /* no power switching */
0071 #define     RH_A_DT     (1 << 10)   /* device type (mbz) */
0072 #define     RH_A_OCPM   (1 << 11)   /* overcurrent protection
0073                            mode */
0074 #define     RH_A_NOCP   (1 << 12)   /* no overcurrent protection */
0075 #define     RH_A_POTPGT (0xff << 24)    /* power on -> power good
0076                            time */
0077 #define HCRHDESCB   0x13
0078 #define     RH_B_DR     (0xffff << 0)   /* device removable flags */
0079 #define     RH_B_PPCM   (0xffff << 16)  /* port power control mask */
0080 #define HCRHSTATUS  0x14
0081 #define     RH_HS_LPS   (1 << 0)    /* local power status */
0082 #define     RH_HS_OCI   (1 << 1)    /* over current indicator */
0083 #define     RH_HS_DRWE  (1 << 15)   /* device remote wakeup
0084                            enable */
0085 #define     RH_HS_LPSC  (1 << 16)   /* local power status change */
0086 #define     RH_HS_OCIC  (1 << 17)   /* over current indicator
0087                            change */
0088 #define     RH_HS_CRWE  (1 << 31)   /* clear remote wakeup
0089                            enable */
0090 #define HCRHPORT1   0x15
0091 #define     RH_PS_CCS   (1 << 0)    /* current connect status */
0092 #define     RH_PS_PES   (1 << 1)    /* port enable status */
0093 #define     RH_PS_PSS   (1 << 2)    /* port suspend status */
0094 #define     RH_PS_POCI  (1 << 3)    /* port over current
0095                            indicator */
0096 #define     RH_PS_PRS   (1 << 4)    /* port reset status */
0097 #define     RH_PS_PPS   (1 << 8)    /* port power status */
0098 #define     RH_PS_LSDA  (1 << 9)    /* low speed device attached */
0099 #define     RH_PS_CSC   (1 << 16)   /* connect status change */
0100 #define     RH_PS_PESC  (1 << 17)   /* port enable status change */
0101 #define     RH_PS_PSSC  (1 << 18)   /* port suspend status
0102                            change */
0103 #define     RH_PS_OCIC  (1 << 19)   /* over current indicator
0104                            change */
0105 #define     RH_PS_PRSC  (1 << 20)   /* port reset status change */
0106 #define     HCRHPORT_CLRMASK    (0x1f << 16)
0107 #define HCRHPORT2   0x16
0108 #define HCHWCFG     0x20
0109 #define     HCHWCFG_15KRSEL     (1 << 12)
0110 #define     HCHWCFG_CLKNOTSTOP  (1 << 11)
0111 #define     HCHWCFG_ANALOG_OC   (1 << 10)
0112 #define     HCHWCFG_DACK_MODE   (1 << 8)
0113 #define     HCHWCFG_EOT_POL     (1 << 7)
0114 #define     HCHWCFG_DACK_POL    (1 << 6)
0115 #define     HCHWCFG_DREQ_POL    (1 << 5)
0116 #define     HCHWCFG_DBWIDTH_MASK    (0x03 << 3)
0117 #define     HCHWCFG_DBWIDTH(n)  (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
0118 #define     HCHWCFG_INT_POL     (1 << 2)
0119 #define     HCHWCFG_INT_TRIGGER (1 << 1)
0120 #define     HCHWCFG_INT_ENABLE  (1 << 0)
0121 #define HCDMACFG    0x21
0122 #define     HCDMACFG_BURST_LEN_MASK (0x03 << 5)
0123 #define     HCDMACFG_BURST_LEN(n)   (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
0124 #define     HCDMACFG_BURST_LEN_1    HCDMACFG_BURST_LEN(0)
0125 #define     HCDMACFG_BURST_LEN_4    HCDMACFG_BURST_LEN(1)
0126 #define     HCDMACFG_BURST_LEN_8    HCDMACFG_BURST_LEN(2)
0127 #define     HCDMACFG_DMA_ENABLE (1 << 4)
0128 #define     HCDMACFG_BUF_TYPE_MASK  (0x07 << 1)
0129 #define     HCDMACFG_CTR_SEL    (1 << 2)
0130 #define     HCDMACFG_ITLATL_SEL (1 << 1)
0131 #define     HCDMACFG_DMA_RW_SELECT  (1 << 0)
0132 #define HCXFERCTR   0x22
0133 #define HCuPINT     0x24
0134 #define     HCuPINT_SOF     (1 << 0)
0135 #define     HCuPINT_ATL     (1 << 1)
0136 #define     HCuPINT_AIIEOT      (1 << 2)
0137 #define     HCuPINT_OPR     (1 << 4)
0138 #define     HCuPINT_SUSP        (1 << 5)
0139 #define     HCuPINT_CLKRDY      (1 << 6)
0140 #define HCuPINTENB  0x25
0141 #define HCCHIPID    0x27
0142 #define     HCCHIPID_MASK       0xff00
0143 #define     HCCHIPID_MAGIC      0x6100
0144 #define HCSCRATCH   0x28
0145 #define HCSWRES     0x29
0146 #define     HCSWRES_MAGIC       0x00f6
0147 #define HCITLBUFLEN 0x2a
0148 #define HCATLBUFLEN 0x2b
0149 #define HCBUFSTAT   0x2c
0150 #define     HCBUFSTAT_ITL0_FULL (1 << 0)
0151 #define     HCBUFSTAT_ITL1_FULL (1 << 1)
0152 #define     HCBUFSTAT_ATL_FULL  (1 << 2)
0153 #define     HCBUFSTAT_ITL0_DONE (1 << 3)
0154 #define     HCBUFSTAT_ITL1_DONE (1 << 4)
0155 #define     HCBUFSTAT_ATL_DONE  (1 << 5)
0156 #define HCRDITL0LEN 0x2d
0157 #define HCRDITL1LEN 0x2e
0158 #define HCITLPORT   0x40
0159 #define HCATLPORT   0x41
0160 
0161 /* Philips transfer descriptor */
0162 struct ptd {
0163     u16 count;
0164 #define PTD_COUNT_MSK   (0x3ff << 0)
0165 #define PTD_TOGGLE_MSK  (1 << 10)
0166 #define PTD_ACTIVE_MSK  (1 << 11)
0167 #define PTD_CC_MSK  (0xf << 12)
0168     u16 mps;
0169 #define PTD_MPS_MSK (0x3ff << 0)
0170 #define PTD_SPD_MSK (1 << 10)
0171 #define PTD_LAST_MSK    (1 << 11)
0172 #define PTD_EP_MSK  (0xf << 12)
0173     u16 len;
0174 #define PTD_LEN_MSK (0x3ff << 0)
0175 #define PTD_DIR_MSK (3 << 10)
0176 #define PTD_DIR_SETUP   (0)
0177 #define PTD_DIR_OUT (1)
0178 #define PTD_DIR_IN  (2)
0179 #define PTD_B5_5_MSK    (1 << 13)
0180     u16 faddr;
0181 #define PTD_FA_MSK  (0x7f << 0)
0182 #define PTD_FMT_MSK (1 << 7)
0183 } __attribute__ ((packed, aligned(2)));
0184 
0185 /* PTD accessor macros. */
0186 #define PTD_GET_COUNT(p)    (((p)->count & PTD_COUNT_MSK) >> 0)
0187 #define PTD_COUNT(v)        (((v) << 0) & PTD_COUNT_MSK)
0188 #define PTD_GET_TOGGLE(p)   (((p)->count & PTD_TOGGLE_MSK) >> 10)
0189 #define PTD_TOGGLE(v)       (((v) << 10) & PTD_TOGGLE_MSK)
0190 #define PTD_GET_ACTIVE(p)   (((p)->count & PTD_ACTIVE_MSK) >> 11)
0191 #define PTD_ACTIVE(v)       (((v) << 11) & PTD_ACTIVE_MSK)
0192 #define PTD_GET_CC(p)       (((p)->count & PTD_CC_MSK) >> 12)
0193 #define PTD_CC(v)       (((v) << 12) & PTD_CC_MSK)
0194 #define PTD_GET_MPS(p)      (((p)->mps & PTD_MPS_MSK) >> 0)
0195 #define PTD_MPS(v)      (((v) << 0) & PTD_MPS_MSK)
0196 #define PTD_GET_SPD(p)      (((p)->mps & PTD_SPD_MSK) >> 10)
0197 #define PTD_SPD(v)      (((v) << 10) & PTD_SPD_MSK)
0198 #define PTD_GET_LAST(p)     (((p)->mps & PTD_LAST_MSK) >> 11)
0199 #define PTD_LAST(v)     (((v) << 11) & PTD_LAST_MSK)
0200 #define PTD_GET_EP(p)       (((p)->mps & PTD_EP_MSK) >> 12)
0201 #define PTD_EP(v)       (((v) << 12) & PTD_EP_MSK)
0202 #define PTD_GET_LEN(p)      (((p)->len & PTD_LEN_MSK) >> 0)
0203 #define PTD_LEN(v)      (((v) << 0) & PTD_LEN_MSK)
0204 #define PTD_GET_DIR(p)      (((p)->len & PTD_DIR_MSK) >> 10)
0205 #define PTD_DIR(v)      (((v) << 10) & PTD_DIR_MSK)
0206 #define PTD_GET_B5_5(p)     (((p)->len & PTD_B5_5_MSK) >> 13)
0207 #define PTD_B5_5(v)     (((v) << 13) & PTD_B5_5_MSK)
0208 #define PTD_GET_FA(p)       (((p)->faddr & PTD_FA_MSK) >> 0)
0209 #define PTD_FA(v)       (((v) << 0) & PTD_FA_MSK)
0210 #define PTD_GET_FMT(p)      (((p)->faddr & PTD_FMT_MSK) >> 7)
0211 #define PTD_FMT(v)      (((v) << 7) & PTD_FMT_MSK)
0212 
0213 /*  Hardware transfer status codes -- CC from ptd->count */
0214 #define TD_CC_NOERROR      0x00
0215 #define TD_CC_CRC          0x01
0216 #define TD_CC_BITSTUFFING  0x02
0217 #define TD_CC_DATATOGGLEM  0x03
0218 #define TD_CC_STALL        0x04
0219 #define TD_DEVNOTRESP      0x05
0220 #define TD_PIDCHECKFAIL    0x06
0221 #define TD_UNEXPECTEDPID   0x07
0222 #define TD_DATAOVERRUN     0x08
0223 #define TD_DATAUNDERRUN    0x09
0224     /* 0x0A, 0x0B reserved for hardware */
0225 #define TD_BUFFEROVERRUN   0x0C
0226 #define TD_BUFFERUNDERRUN  0x0D
0227     /* 0x0E, 0x0F reserved for HCD */
0228 #define TD_NOTACCESSED     0x0F
0229 
0230 /* map PTD status codes (CC) to errno values */
0231 static const int cc_to_error[16] = {
0232     /* No  Error  */ 0,
0233     /* CRC Error  */ -EILSEQ,
0234     /* Bit Stuff  */ -EPROTO,
0235     /* Data Togg  */ -EILSEQ,
0236     /* Stall      */ -EPIPE,
0237     /* DevNotResp */ -ETIME,
0238     /* PIDCheck   */ -EPROTO,
0239     /* UnExpPID   */ -EPROTO,
0240     /* DataOver   */ -EOVERFLOW,
0241     /* DataUnder  */ -EREMOTEIO,
0242     /* (for hw)   */ -EIO,
0243     /* (for hw)   */ -EIO,
0244     /* BufferOver */ -ECOMM,
0245     /* BuffUnder  */ -ENOSR,
0246     /* (for HCD)  */ -EALREADY,
0247     /* (for HCD)  */ -EALREADY
0248 };
0249 
0250 /*--------------------------------------------------------------*/
0251 
0252 #define LOG2_PERIODIC_SIZE  5   /* arbitrary; this matches OHCI */
0253 #define PERIODIC_SIZE       (1 << LOG2_PERIODIC_SIZE)
0254 
0255 struct isp116x {
0256     spinlock_t lock;
0257 
0258     void __iomem *addr_reg;
0259     void __iomem *data_reg;
0260 
0261     struct isp116x_platform_data *board;
0262 
0263     unsigned long stat1, stat2, stat4, stat8, stat16;
0264 
0265     /* HC registers */
0266     u32 intenb;     /* "OHCI" interrupts */
0267     u16 irqenb;     /* uP interrupts */
0268 
0269     /* Root hub registers */
0270     u32 rhdesca;
0271     u32 rhdescb;
0272     u32 rhstatus;
0273 
0274     /* async schedule: control, bulk */
0275     struct list_head async;
0276 
0277     /* periodic schedule: int */
0278     u16 load[PERIODIC_SIZE];
0279     struct isp116x_ep *periodic[PERIODIC_SIZE];
0280     unsigned periodic_count;
0281     u16 fmindex;
0282 
0283     /* Schedule for the current frame */
0284     struct isp116x_ep *atl_active;
0285     int atl_buflen;
0286     int atl_bufshrt;
0287     int atl_last_dir;
0288     atomic_t atl_finishing;
0289 };
0290 
0291 static inline struct isp116x *hcd_to_isp116x(struct usb_hcd *hcd)
0292 {
0293     return (struct isp116x *)(hcd->hcd_priv);
0294 }
0295 
0296 static inline struct usb_hcd *isp116x_to_hcd(struct isp116x *isp116x)
0297 {
0298     return container_of((void *)isp116x, struct usb_hcd, hcd_priv);
0299 }
0300 
0301 struct isp116x_ep {
0302     struct usb_host_endpoint *hep;
0303     struct usb_device *udev;
0304     struct ptd ptd;
0305 
0306     u8 maxpacket;
0307     u8 epnum;
0308     u8 nextpid;
0309     u16 error_count;
0310     u16 length;     /* of current packet */
0311     unsigned char *data;    /* to databuf */
0312     /* queue of active EP's (the ones scheduled for the
0313        current frame) */
0314     struct isp116x_ep *active;
0315 
0316     /* periodic schedule */
0317     u16 period;
0318     u16 branch;
0319     u16 load;
0320     struct isp116x_ep *next;
0321 
0322     /* async schedule */
0323     struct list_head schedule;
0324 };
0325 
0326 /*-------------------------------------------------------------------------*/
0327 
0328 #define DBG(stuff...)       pr_debug("116x: " stuff)
0329 
0330 #ifdef VERBOSE
0331 #    define VDBG        DBG
0332 #else
0333 #    define VDBG(stuff...)  do{}while(0)
0334 #endif
0335 
0336 #define ERR(stuff...)       printk(KERN_ERR "116x: " stuff)
0337 #define WARNING(stuff...)   printk(KERN_WARNING "116x: " stuff)
0338 #define INFO(stuff...)      printk(KERN_INFO "116x: " stuff)
0339 
0340 /* ------------------------------------------------- */
0341 
0342 #if defined(USE_PLATFORM_DELAY)
0343 #if defined(USE_NDELAY)
0344 #error USE_PLATFORM_DELAY and USE_NDELAY simultaneously defined.
0345 #endif
0346 #define isp116x_delay(h,d)  (h)->board->delay(  \
0347                 isp116x_to_hcd(h)->self.controller,d)
0348 #define isp116x_check_platform_delay(h) ((h)->board->delay == NULL)
0349 #elif defined(USE_NDELAY)
0350 #define isp116x_delay(h,d)  ndelay(d)
0351 #define isp116x_check_platform_delay(h) 0
0352 #else
0353 #define isp116x_delay(h,d)  do{}while(0)
0354 #define isp116x_check_platform_delay(h) 0
0355 #endif
0356 
0357 static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
0358 {
0359     writew(reg & 0xff, isp116x->addr_reg);
0360     isp116x_delay(isp116x, 300);
0361 }
0362 
0363 static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
0364 {
0365     writew(val, isp116x->data_reg);
0366     isp116x_delay(isp116x, 150);
0367 }
0368 
0369 static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
0370 {
0371     __raw_writew(val, isp116x->data_reg);
0372     isp116x_delay(isp116x, 150);
0373 }
0374 
0375 static inline u16 isp116x_read_data16(struct isp116x *isp116x)
0376 {
0377     u16 val;
0378 
0379     val = readw(isp116x->data_reg);
0380     isp116x_delay(isp116x, 150);
0381     return val;
0382 }
0383 
0384 static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
0385 {
0386     u16 val;
0387 
0388     val = __raw_readw(isp116x->data_reg);
0389     isp116x_delay(isp116x, 150);
0390     return val;
0391 }
0392 
0393 static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
0394 {
0395     writew(val & 0xffff, isp116x->data_reg);
0396     isp116x_delay(isp116x, 150);
0397     writew(val >> 16, isp116x->data_reg);
0398     isp116x_delay(isp116x, 150);
0399 }
0400 
0401 static inline u32 isp116x_read_data32(struct isp116x *isp116x)
0402 {
0403     u32 val;
0404 
0405     val = (u32) readw(isp116x->data_reg);
0406     isp116x_delay(isp116x, 150);
0407     val |= ((u32) readw(isp116x->data_reg)) << 16;
0408     isp116x_delay(isp116x, 150);
0409     return val;
0410 }
0411 
0412 /* Let's keep register access functions out of line. Hint:
0413    we wait at least 150 ns at every access.
0414 */
0415 static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
0416 {
0417     isp116x_write_addr(isp116x, reg);
0418     return isp116x_read_data16(isp116x);
0419 }
0420 
0421 static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
0422 {
0423     isp116x_write_addr(isp116x, reg);
0424     return isp116x_read_data32(isp116x);
0425 }
0426 
0427 static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
0428                 unsigned val)
0429 {
0430     isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
0431     isp116x_write_data16(isp116x, (u16) (val & 0xffff));
0432 }
0433 
0434 static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
0435                 unsigned val)
0436 {
0437     isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
0438     isp116x_write_data32(isp116x, (u32) val);
0439 }
0440 
0441 #define isp116x_show_reg_log(d,r,s) {               \
0442     if ((r) < 0x20) {                           \
0443         DBG("%-12s[%02x]: %08x\n", #r,          \
0444             r, isp116x_read_reg32(d, r));       \
0445     } else {                        \
0446         DBG("%-12s[%02x]:     %04x\n", #r,      \
0447             r, isp116x_read_reg16(d, r));           \
0448     }                           \
0449 }
0450 #define isp116x_show_reg_seq(d,r,s) {               \
0451     if ((r) < 0x20) {                   \
0452         seq_printf(s, "%-12s[%02x]: %08x\n", #r,    \
0453             r, isp116x_read_reg32(d, r));       \
0454     } else {                        \
0455         seq_printf(s, "%-12s[%02x]:     %04x\n", #r,    \
0456             r, isp116x_read_reg16(d, r));       \
0457     }                           \
0458 }
0459 
0460 #define isp116x_show_regs(d,type,s) {           \
0461     isp116x_show_reg_##type(d, HCREVISION, s);  \
0462     isp116x_show_reg_##type(d, HCCONTROL, s);   \
0463     isp116x_show_reg_##type(d, HCCMDSTAT, s);   \
0464     isp116x_show_reg_##type(d, HCINTSTAT, s);   \
0465     isp116x_show_reg_##type(d, HCINTENB, s);    \
0466     isp116x_show_reg_##type(d, HCFMINTVL, s);   \
0467     isp116x_show_reg_##type(d, HCFMREM, s);     \
0468     isp116x_show_reg_##type(d, HCFMNUM, s);     \
0469     isp116x_show_reg_##type(d, HCLSTHRESH, s);  \
0470     isp116x_show_reg_##type(d, HCRHDESCA, s);   \
0471     isp116x_show_reg_##type(d, HCRHDESCB, s);   \
0472     isp116x_show_reg_##type(d, HCRHSTATUS, s);  \
0473     isp116x_show_reg_##type(d, HCRHPORT1, s);   \
0474     isp116x_show_reg_##type(d, HCRHPORT2, s);   \
0475     isp116x_show_reg_##type(d, HCHWCFG, s);     \
0476     isp116x_show_reg_##type(d, HCDMACFG, s);    \
0477     isp116x_show_reg_##type(d, HCXFERCTR, s);   \
0478     isp116x_show_reg_##type(d, HCuPINT, s);     \
0479     isp116x_show_reg_##type(d, HCuPINTENB, s);  \
0480     isp116x_show_reg_##type(d, HCCHIPID, s);    \
0481     isp116x_show_reg_##type(d, HCSCRATCH, s);   \
0482     isp116x_show_reg_##type(d, HCITLBUFLEN, s); \
0483     isp116x_show_reg_##type(d, HCATLBUFLEN, s); \
0484     isp116x_show_reg_##type(d, HCBUFSTAT, s);   \
0485     isp116x_show_reg_##type(d, HCRDITL0LEN, s); \
0486     isp116x_show_reg_##type(d, HCRDITL1LEN, s); \
0487 }
0488 
0489 /*
0490    Dump registers for debugfs.
0491 */
0492 static inline void isp116x_show_regs_seq(struct isp116x *isp116x,
0493                       struct seq_file *s)
0494 {
0495     isp116x_show_regs(isp116x, seq, s);
0496 }
0497 
0498 /*
0499    Dump registers to syslog.
0500 */
0501 static inline void isp116x_show_regs_log(struct isp116x *isp116x)
0502 {
0503     isp116x_show_regs(isp116x, log, NULL);
0504 }
0505 
0506 #if defined(URB_TRACE)
0507 
0508 #define PIPETYPE(pipe)  ({ char *__s;           \
0509     if (usb_pipecontrol(pipe))  __s = "ctrl";   \
0510     else if (usb_pipeint(pipe)) __s = "int";    \
0511     else if (usb_pipebulk(pipe))    __s = "bulk";   \
0512     else                __s = "iso";    \
0513     __s;})
0514 #define PIPEDIR(pipe)   ({ usb_pipein(pipe) ? "in" : "out"; })
0515 #define URB_NOTSHORT(urb) ({ (urb)->transfer_flags & URB_SHORT_NOT_OK ? \
0516     "short_not_ok" : ""; })
0517 
0518 /* print debug info about the URB */
0519 static void urb_dbg(struct urb *urb, char *msg)
0520 {
0521     unsigned int pipe;
0522 
0523     if (!urb) {
0524         DBG("%s: zero urb\n", msg);
0525         return;
0526     }
0527     pipe = urb->pipe;
0528     DBG("%s: FA %d ep%d%s %s: len %d/%d %s\n", msg,
0529         usb_pipedevice(pipe), usb_pipeendpoint(pipe),
0530         PIPEDIR(pipe), PIPETYPE(pipe),
0531         urb->transfer_buffer_length, urb->actual_length, URB_NOTSHORT(urb));
0532 }
0533 
0534 #else
0535 
0536 #define  urb_dbg(urb,msg)   do{}while(0)
0537 
0538 #endif              /* ! defined(URB_TRACE) */
0539 
0540 #if defined(PTD_TRACE)
0541 
0542 #define PTD_DIR_STR(ptd)  ({char __c;       \
0543     switch(PTD_GET_DIR(ptd)){       \
0544     case 0:  __c = 's'; break;      \
0545     case 1:  __c = 'o'; break;      \
0546     default: __c = 'i'; break;      \
0547     }; __c;})
0548 
0549 /*
0550   Dump PTD info. The code documents the format
0551   perfectly, right :)
0552 */
0553 static inline void dump_ptd(struct ptd *ptd)
0554 {
0555     printk(KERN_WARNING "td: %x %d%c%d %d,%d,%d  %x %x%x%x\n",
0556            PTD_GET_CC(ptd), PTD_GET_FA(ptd),
0557            PTD_DIR_STR(ptd), PTD_GET_EP(ptd),
0558            PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
0559            PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd),
0560            PTD_GET_SPD(ptd), PTD_GET_LAST(ptd));
0561 }
0562 
0563 static inline void dump_ptd_out_data(struct ptd *ptd, u8 * buf)
0564 {
0565     int k;
0566 
0567     if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) {
0568         printk(KERN_WARNING "-> ");
0569         for (k = 0; k < PTD_GET_LEN(ptd); ++k)
0570             printk("%02x ", ((u8 *) buf)[k]);
0571         printk("\n");
0572     }
0573 }
0574 
0575 static inline void dump_ptd_in_data(struct ptd *ptd, u8 * buf)
0576 {
0577     int k;
0578 
0579     if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) {
0580         printk(KERN_WARNING "<- ");
0581         for (k = 0; k < PTD_GET_COUNT(ptd); ++k)
0582             printk("%02x ", ((u8 *) buf)[k]);
0583         printk("\n");
0584     }
0585     if (PTD_GET_LAST(ptd))
0586         printk(KERN_WARNING "-\n");
0587 }
0588 
0589 #else
0590 
0591 #define dump_ptd(ptd)               do{}while(0)
0592 #define dump_ptd_in_data(ptd,buf)   do{}while(0)
0593 #define dump_ptd_out_data(ptd,buf)  do{}while(0)
0594 
0595 #endif              /* ! defined(PTD_TRACE) */
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