usb/host/fotg210.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __LINUX_FOTG210_H
0003 #define __LINUX_FOTG210_H
0004
0005 #include <linux/usb/ehci-dbgp.h>
0006
0007 /* definitions used for the EHCI driver */
0008
0009 /*
0010  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
0011  * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
0012  * the host controller implementation.
0013  *
0014  * To facilitate the strongest possible byte-order checking from "sparse"
0015  * and so on, we use __leXX unless that's not practical.
0016  */
0017 #define __hc32  __le32
0018 #define __hc16  __le16
0019
0020 /* statistics can be kept for tuning/monitoring */
0021 struct fotg210_stats {
0022     /* irq usage */
0023     unsigned long       normal;
0024     unsigned long       error;
0025     unsigned long       iaa;
0026     unsigned long       lost_iaa;
0027
0028     /* termination of urbs from core */
0029     unsigned long       complete;
0030     unsigned long       unlink;
0031 };
0032
0033 /* fotg210_hcd->lock guards shared data against other CPUs:
0034  *   fotg210_hcd:   async, unlink, periodic (and shadow), ...
0035  *   usb_host_endpoint: hcpriv
0036  *   fotg210_qh:    qh_next, qtd_list
0037  *   fotg210_qtd:   qtd_list
0038  *
0039  * Also, hold this lock when talking to HC registers or
0040  * when updating hw_* fields in shared qh/qtd/... structures.
0041  */
0042
0043 #define FOTG210_MAX_ROOT_PORTS  1       /* see HCS_N_PORTS */
0044
0045 /*
0046  * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
0047  * controller may be doing DMA.  Lower values mean there's no DMA.
0048  */
0049 enum fotg210_rh_state {
0050     FOTG210_RH_HALTED,
0051     FOTG210_RH_SUSPENDED,
0052     FOTG210_RH_RUNNING,
0053     FOTG210_RH_STOPPING
0054 };
0055
0056 /*
0057  * Timer events, ordered by increasing delay length.
0058  * Always update event_delays_ns[] and event_handlers[] (defined in
0059  * ehci-timer.c) in parallel with this list.
0060  */
0061 enum fotg210_hrtimer_event {
0062     FOTG210_HRTIMER_POLL_ASS,   /* Poll for async schedule off */
0063     FOTG210_HRTIMER_POLL_PSS,   /* Poll for periodic schedule off */
0064     FOTG210_HRTIMER_POLL_DEAD,  /* Wait for dead controller to stop */
0065     FOTG210_HRTIMER_UNLINK_INTR,    /* Wait for interrupt QH unlink */
0066     FOTG210_HRTIMER_FREE_ITDS,  /* Wait for unused iTDs and siTDs */
0067     FOTG210_HRTIMER_ASYNC_UNLINKS,  /* Unlink empty async QHs */
0068     FOTG210_HRTIMER_IAA_WATCHDOG,   /* Handle lost IAA interrupts */
0069     FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
0070     FOTG210_HRTIMER_DISABLE_ASYNC,  /* Wait to disable async sched */
0071     FOTG210_HRTIMER_IO_WATCHDOG,    /* Check for missing IRQs */
0072     FOTG210_HRTIMER_NUM_EVENTS  /* Must come last */
0073 };
0074 #define FOTG210_HRTIMER_NO_EVENT    99
0075
0076 struct fotg210_hcd {            /* one per controller */
0077     /* timing support */
0078     enum fotg210_hrtimer_event  next_hrtimer_event;
0079     unsigned        enabled_hrtimer_events;
0080     ktime_t         hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
0081     struct hrtimer      hrtimer;
0082
0083     int         PSS_poll_count;
0084     int         ASS_poll_count;
0085     int         died_poll_count;
0086
0087     /* glue to PCI and HCD framework */
0088     struct fotg210_caps __iomem *caps;
0089     struct fotg210_regs __iomem *regs;
0090     struct ehci_dbg_port __iomem *debug;
0091
0092     __u32           hcs_params; /* cached register copy */
0093     spinlock_t      lock;
0094     enum fotg210_rh_state   rh_state;
0095
0096     /* general schedule support */
0097     bool            scanning:1;
0098     bool            need_rescan:1;
0099     bool            intr_unlinking:1;
0100     bool            async_unlinking:1;
0101     bool            shutdown:1;
0102     struct fotg210_qh       *qh_scan_next;
0103
0104     /* async schedule support */
0105     struct fotg210_qh       *async;
0106     struct fotg210_qh       *dummy;     /* For AMD quirk use */
0107     struct fotg210_qh       *async_unlink;
0108     struct fotg210_qh       *async_unlink_last;
0109     struct fotg210_qh       *async_iaa;
0110     unsigned        async_unlink_cycle;
0111     unsigned        async_count;    /* async activity count */
0112
0113     /* periodic schedule support */
0114 #define DEFAULT_I_TDPS      1024        /* some HCs can do less */
0115     unsigned        periodic_size;
0116     __hc32          *periodic;  /* hw periodic table */
0117     dma_addr_t      periodic_dma;
0118     struct list_head    intr_qh_list;
0119     unsigned        i_thresh;   /* uframes HC might cache */
0120
0121     union fotg210_shadow    *pshadow;   /* mirror hw periodic table */
0122     struct fotg210_qh       *intr_unlink;
0123     struct fotg210_qh       *intr_unlink_last;
0124     unsigned        intr_unlink_cycle;
0125     unsigned        now_frame;  /* frame from HC hardware */
0126     unsigned        next_frame; /* scan periodic, start here */
0127     unsigned        intr_count; /* intr activity count */
0128     unsigned        isoc_count; /* isoc activity count */
0129     unsigned        periodic_count; /* periodic activity count */
0130     /* max periodic time per uframe */
0131     unsigned        uframe_periodic_max;
0132
0133
0134     /* list of itds completed while now_frame was still active */
0135     struct list_head    cached_itd_list;
0136     struct fotg210_itd  *last_itd_to_free;
0137
0138     /* per root hub port */
0139     unsigned long       reset_done[FOTG210_MAX_ROOT_PORTS];
0140
0141     /* bit vectors (one bit per port)
0142      * which ports were already suspended at the start of a bus suspend
0143      */
0144     unsigned long       bus_suspended;
0145
0146     /* which ports are edicated to the companion controller */
0147     unsigned long       companion_ports;
0148
0149     /* which ports are owned by the companion during a bus suspend */
0150     unsigned long       owned_ports;
0151
0152     /* which ports have the change-suspend feature turned on */
0153     unsigned long       port_c_suspend;
0154
0155     /* which ports are suspended */
0156     unsigned long       suspended_ports;
0157
0158     /* which ports have started to resume */
0159     unsigned long       resuming_ports;
0160
0161     /* per-HC memory pools (could be per-bus, but ...) */
0162     struct dma_pool     *qh_pool;   /* qh per active urb */
0163     struct dma_pool     *qtd_pool;  /* one or more per qh */
0164     struct dma_pool     *itd_pool;  /* itd per iso urb */
0165
0166     unsigned        random_frame;
0167     unsigned long       next_statechange;
0168     ktime_t         last_periodic_enable;
0169     u32         command;
0170
0171     /* SILICON QUIRKS */
0172     unsigned        need_io_watchdog:1;
0173     unsigned        fs_i_thresh:1;  /* Intel iso scheduling */
0174
0175     u8          sbrn;       /* packed release number */
0176
0177     /* irq statistics */
0178 #ifdef FOTG210_STATS
0179     struct fotg210_stats    stats;
0180 #   define INCR(x) ((x)++)
0181 #else
0182 #   define INCR(x) do {} while (0)
0183 #endif
0184
0185     /* silicon clock */
0186     struct clk      *pclk;
0187 };
0188
0189 /* convert between an HCD pointer and the corresponding FOTG210_HCD */
0190 static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
0191 {
0192     return (struct fotg210_hcd *)(hcd->hcd_priv);
0193 }
0194 static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
0195 {
0196     return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
0197 }
0198
0199 /*-------------------------------------------------------------------------*/
0200
0201 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
0202
0203 /* Section 2.2 Host Controller Capability Registers */
0204 struct fotg210_caps {
0205     /* these fields are specified as 8 and 16 bit registers,
0206      * but some hosts can't perform 8 or 16 bit PCI accesses.
0207      * some hosts treat caplength and hciversion as parts of a 32-bit
0208      * register, others treat them as two separate registers, this
0209      * affects the memory map for big endian controllers.
0210      */
0211     u32     hc_capbase;
0212 #define HC_LENGTH(fotg210, p)   (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
0213                 (fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
0214 #define HC_VERSION(fotg210, p)  (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
0215                 (fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
0216     u32     hcs_params;     /* HCSPARAMS - offset 0x4 */
0217 #define HCS_N_PORTS(p)      (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
0218
0219     u32     hcc_params; /* HCCPARAMS - offset 0x8 */
0220 #define HCC_CANPARK(p)      ((p)&(1 << 2))  /* true: can park on async qh */
0221 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
0222     u8      portroute[8];    /* nibbles for routing - offset 0xC */
0223 };
0224
0225
0226 /* Section 2.3 Host Controller Operational Registers */
0227 struct fotg210_regs {
0228
0229     /* USBCMD: offset 0x00 */
0230     u32     command;
0231
0232 /* EHCI 1.1 addendum */
0233 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
0234 #define CMD_PARK    (1<<11)     /* enable "park" on async qh */
0235 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
0236 #define CMD_IAAD    (1<<6)      /* "doorbell" interrupt async advance */
0237 #define CMD_ASE     (1<<5)      /* async schedule enable */
0238 #define CMD_PSE     (1<<4)      /* periodic schedule enable */
0239 /* 3:2 is periodic frame list size */
0240 #define CMD_RESET   (1<<1)      /* reset HC not bus */
0241 #define CMD_RUN     (1<<0)      /* start/stop HC */
0242
0243     /* USBSTS: offset 0x04 */
0244     u32     status;
0245 #define STS_ASS     (1<<15)     /* Async Schedule Status */
0246 #define STS_PSS     (1<<14)     /* Periodic Schedule Status */
0247 #define STS_RECL    (1<<13)     /* Reclamation */
0248 #define STS_HALT    (1<<12)     /* Not running (any reason) */
0249 /* some bits reserved */
0250     /* these STS_* flags are also intr_enable bits (USBINTR) */
0251 #define STS_IAA     (1<<5)      /* Interrupted on async advance */
0252 #define STS_FATAL   (1<<4)      /* such as some PCI access errors */
0253 #define STS_FLR     (1<<3)      /* frame list rolled over */
0254 #define STS_PCD     (1<<2)      /* port change detect */
0255 #define STS_ERR     (1<<1)      /* "error" completion (overflow, ...) */
0256 #define STS_INT     (1<<0)      /* "normal" completion (short, ...) */
0257
0258     /* USBINTR: offset 0x08 */
0259     u32     intr_enable;
0260
0261     /* FRINDEX: offset 0x0C */
0262     u32     frame_index;    /* current microframe number */
0263     /* CTRLDSSEGMENT: offset 0x10 */
0264     u32     segment;    /* address bits 63:32 if needed */
0265     /* PERIODICLISTBASE: offset 0x14 */
0266     u32     frame_list; /* points to periodic list */
0267     /* ASYNCLISTADDR: offset 0x18 */
0268     u32     async_next; /* address of next async queue head */
0269
0270     u32 reserved1;
0271     /* PORTSC: offset 0x20 */
0272     u32 port_status;
0273 /* 31:23 reserved */
0274 #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))    /* USB 1.1 device */
0275 #define PORT_RESET  (1<<8)      /* reset port */
0276 #define PORT_SUSPEND    (1<<7)      /* suspend port */
0277 #define PORT_RESUME (1<<6)      /* resume it */
0278 #define PORT_PEC    (1<<3)      /* port enable change */
0279 #define PORT_PE     (1<<2)      /* port enable */
0280 #define PORT_CSC    (1<<1)      /* connect status change */
0281 #define PORT_CONNECT    (1<<0)      /* device connected */
0282 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC)
0283     u32     reserved2[19];
0284
0285     /* OTGCSR: offet 0x70 */
0286     u32     otgcsr;
0287 #define OTGCSR_HOST_SPD_TYP     (3 << 22)
0288 #define OTGCSR_A_BUS_DROP   (1 << 5)
0289 #define OTGCSR_A_BUS_REQ    (1 << 4)
0290
0291     /* OTGISR: offset 0x74 */
0292     u32     otgisr;
0293 #define OTGISR_OVC  (1 << 10)
0294
0295     u32     reserved3[15];
0296
0297     /* GMIR: offset 0xB4 */
0298     u32     gmir;
0299 #define GMIR_INT_POLARITY   (1 << 3) /*Active High*/
0300 #define GMIR_MHC_INT        (1 << 2)
0301 #define GMIR_MOTG_INT       (1 << 1)
0302 #define GMIR_MDEV_INT   (1 << 0)
0303 };
0304
0305 /*-------------------------------------------------------------------------*/
0306
0307 #define QTD_NEXT(fotg210, dma)  cpu_to_hc32(fotg210, (u32)dma)
0308
0309 /*
0310  * EHCI Specification 0.95 Section 3.5
0311  * QTD: describe data transfer components (buffer, direction, ...)
0312  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
0313  *
0314  * These are associated only with "QH" (Queue Head) structures,
0315  * used with control, bulk, and interrupt transfers.
0316  */
0317 struct fotg210_qtd {
0318     /* first part defined by EHCI spec */
0319     __hc32          hw_next;    /* see EHCI 3.5.1 */
0320     __hc32          hw_alt_next;    /* see EHCI 3.5.2 */
0321     __hc32          hw_token;   /* see EHCI 3.5.3 */
0322 #define QTD_TOGGLE  (1 << 31)   /* data toggle */
0323 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
0324 #define QTD_IOC     (1 << 15)   /* interrupt on complete */
0325 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
0326 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
0327 #define QTD_STS_ACTIVE  (1 << 7)    /* HC may execute this */
0328 #define QTD_STS_HALT    (1 << 6)    /* halted on error */
0329 #define QTD_STS_DBE (1 << 5)    /* data buffer error (in HC) */
0330 #define QTD_STS_BABBLE  (1 << 4)    /* device was babbling (qtd halted) */
0331 #define QTD_STS_XACT    (1 << 3)    /* device gave illegal response */
0332 #define QTD_STS_MMF (1 << 2)    /* incomplete split transaction */
0333 #define QTD_STS_STS (1 << 1)    /* split transaction state */
0334 #define QTD_STS_PING    (1 << 0)    /* issue PING? */
0335
0336 #define ACTIVE_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
0337 #define HALT_BIT(fotg210)       cpu_to_hc32(fotg210, QTD_STS_HALT)
0338 #define STATUS_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_STS)
0339
0340     __hc32          hw_buf[5];  /* see EHCI 3.5.4 */
0341     __hc32          hw_buf_hi[5];   /* Appendix B */
0342
0343     /* the rest is HCD-private */
0344     dma_addr_t      qtd_dma;        /* qtd address */
0345     struct list_head    qtd_list;       /* sw qtd list */
0346     struct urb      *urb;           /* qtd's urb */
0347     size_t          length;         /* length of buffer */
0348 } __aligned(32);
0349
0350 /* mask NakCnt+T in qh->hw_alt_next */
0351 #define QTD_MASK(fotg210)   cpu_to_hc32(fotg210, ~0x1f)
0352
0353 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
0354
0355 /*-------------------------------------------------------------------------*/
0356
0357 /* type tag from {qh,itd,fstn}->hw_next */
0358 #define Q_NEXT_TYPE(fotg210, dma)   ((dma) & cpu_to_hc32(fotg210, 3 << 1))
0359
0360 /*
0361  * Now the following defines are not converted using the
0362  * cpu_to_le32() macro anymore, since we have to support
0363  * "dynamic" switching between be and le support, so that the driver
0364  * can be used on one system with SoC EHCI controller using big-endian
0365  * descriptors as well as a normal little-endian PCI EHCI controller.
0366  */
0367 /* values for that type tag */
0368 #define Q_TYPE_ITD  (0 << 1)
0369 #define Q_TYPE_QH   (1 << 1)
0370 #define Q_TYPE_SITD (2 << 1)
0371 #define Q_TYPE_FSTN (3 << 1)
0372
0373 /* next async queue entry, or pointer to interrupt/periodic QH */
0374 #define QH_NEXT(fotg210, dma) \
0375     (cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
0376
0377 /* for periodic/async schedules and qtd lists, mark end of list */
0378 #define FOTG210_LIST_END(fotg210) \
0379     cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
0380
0381 /*
0382  * Entries in periodic shadow table are pointers to one of four kinds
0383  * of data structure.  That's dictated by the hardware; a type tag is
0384  * encoded in the low bits of the hardware's periodic schedule.  Use
0385  * Q_NEXT_TYPE to get the tag.
0386  *
0387  * For entries in the async schedule, the type tag always says "qh".
0388  */
0389 union fotg210_shadow {
0390     struct fotg210_qh   *qh;        /* Q_TYPE_QH */
0391     struct fotg210_itd  *itd;       /* Q_TYPE_ITD */
0392     struct fotg210_fstn *fstn;      /* Q_TYPE_FSTN */
0393     __hc32          *hw_next;   /* (all types) */
0394     void            *ptr;
0395 };
0396
0397 /*-------------------------------------------------------------------------*/
0398
0399 /*
0400  * EHCI Specification 0.95 Section 3.6
0401  * QH: describes control/bulk/interrupt endpoints
0402  * See Fig 3-7 "Queue Head Structure Layout".
0403  *
0404  * These appear in both the async and (for interrupt) periodic schedules.
0405  */
0406
0407 /* first part defined by EHCI spec */
0408 struct fotg210_qh_hw {
0409     __hc32          hw_next;    /* see EHCI 3.6.1 */
0410     __hc32          hw_info1;   /* see EHCI 3.6.2 */
0411 #define QH_CONTROL_EP   (1 << 27)   /* FS/LS control endpoint */
0412 #define QH_HEAD     (1 << 15)   /* Head of async reclamation list */
0413 #define QH_TOGGLE_CTL   (1 << 14)   /* Data toggle control */
0414 #define QH_HIGH_SPEED   (2 << 12)   /* Endpoint speed */
0415 #define QH_LOW_SPEED    (1 << 12)
0416 #define QH_FULL_SPEED   (0 << 12)
0417 #define QH_INACTIVATE   (1 << 7)    /* Inactivate on next transaction */
0418     __hc32          hw_info2;   /* see EHCI 3.6.2 */
0419 #define QH_SMASK    0x000000ff
0420 #define QH_CMASK    0x0000ff00
0421 #define QH_HUBADDR  0x007f0000
0422 #define QH_HUBPORT  0x3f800000
0423 #define QH_MULT     0xc0000000
0424     __hc32          hw_current; /* qtd list - see EHCI 3.6.4 */
0425
0426     /* qtd overlay (hardware parts of a struct fotg210_qtd) */
0427     __hc32          hw_qtd_next;
0428     __hc32          hw_alt_next;
0429     __hc32          hw_token;
0430     __hc32          hw_buf[5];
0431     __hc32          hw_buf_hi[5];
0432 } __aligned(32);
0433
0434 struct fotg210_qh {
0435     struct fotg210_qh_hw    *hw;        /* Must come first */
0436     /* the rest is HCD-private */
0437     dma_addr_t      qh_dma;     /* address of qh */
0438     union fotg210_shadow    qh_next;    /* ptr to qh; or periodic */
0439     struct list_head    qtd_list;   /* sw qtd list */
0440     struct list_head    intr_node;  /* list of intr QHs */
0441     struct fotg210_qtd  *dummy;
0442     struct fotg210_qh   *unlink_next;   /* next on unlink list */
0443
0444     unsigned        unlink_cycle;
0445
0446     u8          needs_rescan;   /* Dequeue during giveback */
0447     u8          qh_state;
0448 #define QH_STATE_LINKED     1       /* HC sees this */
0449 #define QH_STATE_UNLINK     2       /* HC may still see this */
0450 #define QH_STATE_IDLE       3       /* HC doesn't see this */
0451 #define QH_STATE_UNLINK_WAIT    4       /* LINKED and on unlink q */
0452 #define QH_STATE_COMPLETING 5       /* don't touch token.HALT */
0453
0454     u8          xacterrs;   /* XactErr retry counter */
0455 #define QH_XACTERR_MAX      32      /* XactErr retry limit */
0456
0457     /* periodic schedule info */
0458     u8          usecs;      /* intr bandwidth */
0459     u8          gap_uf;     /* uframes split/csplit gap */
0460     u8          c_usecs;    /* ... split completion bw */
0461     u16         tt_usecs;   /* tt downstream bandwidth */
0462     unsigned short      period;     /* polling interval */
0463     unsigned short      start;      /* where polling starts */
0464 #define NO_FRAME ((unsigned short)~0)           /* pick new start */
0465
0466     struct usb_device   *dev;       /* access to TT */
0467     unsigned        is_out:1;   /* bulk or intr OUT */
0468     unsigned        clearing_tt:1;  /* Clear-TT-Buf in progress */
0469 };
0470
0471 /*-------------------------------------------------------------------------*/
0472
0473 /* description of one iso transaction (up to 3 KB data if highspeed) */
0474 struct fotg210_iso_packet {
0475     /* These will be copied to iTD when scheduling */
0476     u64         bufp;       /* itd->hw_bufp{,_hi}[pg] |= */
0477     __hc32          transaction;    /* itd->hw_transaction[i] |= */
0478     u8          cross;      /* buf crosses pages */
0479     /* for full speed OUT splits */
0480     u32         buf1;
0481 };
0482
0483 /* temporary schedule data for packets from iso urbs (both speeds)
0484  * each packet is one logical usb transaction to the device (not TT),
0485  * beginning at stream->next_uframe
0486  */
0487 struct fotg210_iso_sched {
0488     struct list_head    td_list;
0489     unsigned        span;
0490     struct fotg210_iso_packet   packet[];
0491 };
0492
0493 /*
0494  * fotg210_iso_stream - groups all (s)itds for this endpoint.
0495  * acts like a qh would, if EHCI had them for ISO.
0496  */
0497 struct fotg210_iso_stream {
0498     /* first field matches fotg210_hq, but is NULL */
0499     struct fotg210_qh_hw    *hw;
0500
0501     u8          bEndpointAddress;
0502     u8          highspeed;
0503     struct list_head    td_list;    /* queued itds */
0504     struct list_head    free_list;  /* list of unused itds */
0505     struct usb_device   *udev;
0506     struct usb_host_endpoint *ep;
0507
0508     /* output of (re)scheduling */
0509     int         next_uframe;
0510     __hc32          splits;
0511
0512     /* the rest is derived from the endpoint descriptor,
0513      * trusting urb->interval == f(epdesc->bInterval) and
0514      * including the extra info for hw_bufp[0..2]
0515      */
0516     u8          usecs, c_usecs;
0517     u16         interval;
0518     u16         tt_usecs;
0519     u16         maxp;
0520     u16         raw_mask;
0521     unsigned        bandwidth;
0522
0523     /* This is used to initialize iTD's hw_bufp fields */
0524     __hc32          buf0;
0525     __hc32          buf1;
0526     __hc32          buf2;
0527
0528     /* this is used to initialize sITD's tt info */
0529     __hc32          address;
0530 };
0531
0532 /*-------------------------------------------------------------------------*/
0533
0534 /*
0535  * EHCI Specification 0.95 Section 3.3
0536  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
0537  *
0538  * Schedule records for high speed iso xfers
0539  */
0540 struct fotg210_itd {
0541     /* first part defined by EHCI spec */
0542     __hc32          hw_next;    /* see EHCI 3.3.1 */
0543     __hc32          hw_transaction[8]; /* see EHCI 3.3.2 */
0544 #define FOTG210_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
0545 #define FOTG210_ISOC_BUF_ERR    (1<<30) /* Data buffer error */
0546 #define FOTG210_ISOC_BABBLE (1<<29) /* babble detected */
0547 #define FOTG210_ISOC_XACTERR    (1<<28) /* XactErr - transaction error */
0548 #define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
0549 #define FOTG210_ITD_IOC     (1 << 15)   /* interrupt on complete */
0550
0551 #define ITD_ACTIVE(fotg210) cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
0552
0553     __hc32          hw_bufp[7]; /* see EHCI 3.3.3 */
0554     __hc32          hw_bufp_hi[7];  /* Appendix B */
0555
0556     /* the rest is HCD-private */
0557     dma_addr_t      itd_dma;    /* for this itd */
0558     union fotg210_shadow    itd_next;   /* ptr to periodic q entry */
0559
0560     struct urb      *urb;
0561     struct fotg210_iso_stream   *stream;    /* endpoint's queue */
0562     struct list_head    itd_list;   /* list of stream's itds */
0563
0564     /* any/all hw_transactions here may be used by that urb */
0565     unsigned        frame;      /* where scheduled */
0566     unsigned        pg;
0567     unsigned        index[8];   /* in urb->iso_frame_desc */
0568 } __aligned(32);
0569
0570 /*-------------------------------------------------------------------------*/
0571
0572 /*
0573  * EHCI Specification 0.96 Section 3.7
0574  * Periodic Frame Span Traversal Node (FSTN)
0575  *
0576  * Manages split interrupt transactions (using TT) that span frame boundaries
0577  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
0578  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
0579  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
0580  */
0581 struct fotg210_fstn {
0582     __hc32          hw_next;    /* any periodic q entry */
0583     __hc32          hw_prev;    /* qh or FOTG210_LIST_END */
0584
0585     /* the rest is HCD-private */
0586     dma_addr_t      fstn_dma;
0587     union fotg210_shadow    fstn_next;  /* ptr to periodic q entry */
0588 } __aligned(32);
0589
0590 /*-------------------------------------------------------------------------*/
0591
0592 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
0593
0594 #define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
0595         fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup)
0596
0597 #define fotg210_prepare_ports_for_controller_resume(fotg210)        \
0598         fotg210_adjust_port_wakeup_flags(fotg210, false, false)
0599
0600 /*-------------------------------------------------------------------------*/
0601
0602 /*
0603  * Some EHCI controllers have a Transaction Translator built into the
0604  * root hub. This is a non-standard feature.  Each controller will need
0605  * to add code to the following inline functions, and call them as
0606  * needed (mostly in root hub code).
0607  */
0608
0609 static inline unsigned int
0610 fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
0611 {
0612     return (readl(&fotg210->regs->otgcsr)
0613         & OTGCSR_HOST_SPD_TYP) >> 22;
0614 }
0615
0616 /* Returns the speed of a device attached to a port on the root hub. */
0617 static inline unsigned int
0618 fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
0619 {
0620     switch (fotg210_get_speed(fotg210, portsc)) {
0621     case 0:
0622         return 0;
0623     case 1:
0624         return USB_PORT_STAT_LOW_SPEED;
0625     case 2:
0626     default:
0627         return USB_PORT_STAT_HIGH_SPEED;
0628     }
0629 }
0630
0631 /*-------------------------------------------------------------------------*/
0632
0633 #define fotg210_has_fsl_portno_bug(e)       (0)
0634
0635 /*
0636  * While most USB host controllers implement their registers in
0637  * little-endian format, a minority (celleb companion chip) implement
0638  * them in big endian format.
0639  *
0640  * This attempts to support either format at compile time without a
0641  * runtime penalty, or both formats with the additional overhead
0642  * of checking a flag bit.
0643  *
0644  */
0645
0646 #define fotg210_big_endian_mmio(e)  0
0647 #define fotg210_big_endian_capbase(e)   0
0648
0649 static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
0650         __u32 __iomem *regs)
0651 {
0652     return readl(regs);
0653 }
0654
0655 static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
0656         const unsigned int val, __u32 __iomem *regs)
0657 {
0658     writel(val, regs);
0659 }
0660
0661 /* cpu to fotg210 */
0662 static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
0663 {
0664     return cpu_to_le32(x);
0665 }
0666
0667 /* fotg210 to cpu */
0668 static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
0669 {
0670     return le32_to_cpu(x);
0671 }
0672
0673 static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
0674                    const __hc32 *x)
0675 {
0676     return le32_to_cpup(x);
0677 }
0678
0679 /*-------------------------------------------------------------------------*/
0680
0681 static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
0682 {
0683     return fotg210_readl(fotg210, &fotg210->regs->frame_index);
0684 }
0685
0686 /*-------------------------------------------------------------------------*/
0687
0688 #endif /* __LINUX_FOTG210_H */