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0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (c) 2001-2002 by David Brownell
0004  */
0005 
0006 #ifndef __LINUX_EHCI_HCD_H
0007 #define __LINUX_EHCI_HCD_H
0008 
0009 /* definitions used for the EHCI driver */
0010 
0011 /*
0012  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
0013  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
0014  * the host controller implementation.
0015  *
0016  * To facilitate the strongest possible byte-order checking from "sparse"
0017  * and so on, we use __leXX unless that's not practical.
0018  */
0019 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
0020 typedef __u32 __bitwise __hc32;
0021 typedef __u16 __bitwise __hc16;
0022 #else
0023 #define __hc32  __le32
0024 #define __hc16  __le16
0025 #endif
0026 
0027 /* statistics can be kept for tuning/monitoring */
0028 #ifdef CONFIG_DYNAMIC_DEBUG
0029 #define EHCI_STATS
0030 #endif
0031 
0032 struct ehci_stats {
0033     /* irq usage */
0034     unsigned long       normal;
0035     unsigned long       error;
0036     unsigned long       iaa;
0037     unsigned long       lost_iaa;
0038 
0039     /* termination of urbs from core */
0040     unsigned long       complete;
0041     unsigned long       unlink;
0042 };
0043 
0044 /*
0045  * Scheduling and budgeting information for periodic transfers, for both
0046  * high-speed devices and full/low-speed devices lying behind a TT.
0047  */
0048 struct ehci_per_sched {
0049     struct usb_device   *udev;      /* access to the TT */
0050     struct usb_host_endpoint *ep;
0051     struct list_head    ps_list;    /* node on ehci_tt's ps_list */
0052     u16         tt_usecs;   /* time on the FS/LS bus */
0053     u16         cs_mask;    /* C-mask and S-mask bytes */
0054     u16         period;     /* actual period in frames */
0055     u16         phase;      /* actual phase, frame part */
0056     u8          bw_phase;   /* same, for bandwidth
0057                            reservation */
0058     u8          phase_uf;   /* uframe part of the phase */
0059     u8          usecs, c_usecs; /* times on the HS bus */
0060     u8          bw_uperiod; /* period in microframes, for
0061                            bandwidth reservation */
0062     u8          bw_period;  /* same, in frames */
0063 };
0064 #define NO_FRAME    29999           /* frame not assigned yet */
0065 
0066 /* ehci_hcd->lock guards shared data against other CPUs:
0067  *   ehci_hcd:  async, unlink, periodic (and shadow), ...
0068  *   usb_host_endpoint: hcpriv
0069  *   ehci_qh:   qh_next, qtd_list
0070  *   ehci_qtd:  qtd_list
0071  *
0072  * Also, hold this lock when talking to HC registers or
0073  * when updating hw_* fields in shared qh/qtd/... structures.
0074  */
0075 
0076 #define EHCI_MAX_ROOT_PORTS 15      /* see HCS_N_PORTS */
0077 
0078 /*
0079  * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
0080  * controller may be doing DMA.  Lower values mean there's no DMA.
0081  */
0082 enum ehci_rh_state {
0083     EHCI_RH_HALTED,
0084     EHCI_RH_SUSPENDED,
0085     EHCI_RH_RUNNING,
0086     EHCI_RH_STOPPING
0087 };
0088 
0089 /*
0090  * Timer events, ordered by increasing delay length.
0091  * Always update event_delays_ns[] and event_handlers[] (defined in
0092  * ehci-timer.c) in parallel with this list.
0093  */
0094 enum ehci_hrtimer_event {
0095     EHCI_HRTIMER_POLL_ASS,      /* Poll for async schedule off */
0096     EHCI_HRTIMER_POLL_PSS,      /* Poll for periodic schedule off */
0097     EHCI_HRTIMER_POLL_DEAD,     /* Wait for dead controller to stop */
0098     EHCI_HRTIMER_UNLINK_INTR,   /* Wait for interrupt QH unlink */
0099     EHCI_HRTIMER_FREE_ITDS,     /* Wait for unused iTDs and siTDs */
0100     EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */
0101     EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
0102     EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
0103     EHCI_HRTIMER_IAA_WATCHDOG,  /* Handle lost IAA interrupts */
0104     EHCI_HRTIMER_DISABLE_PERIODIC,  /* Wait to disable periodic sched */
0105     EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
0106     EHCI_HRTIMER_IO_WATCHDOG,   /* Check for missing IRQs */
0107     EHCI_HRTIMER_NUM_EVENTS     /* Must come last */
0108 };
0109 #define EHCI_HRTIMER_NO_EVENT   99
0110 
0111 struct ehci_hcd {           /* one per controller */
0112     /* timing support */
0113     enum ehci_hrtimer_event next_hrtimer_event;
0114     unsigned        enabled_hrtimer_events;
0115     ktime_t         hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
0116     struct hrtimer      hrtimer;
0117 
0118     int         PSS_poll_count;
0119     int         ASS_poll_count;
0120     int         died_poll_count;
0121 
0122     /* glue to PCI and HCD framework */
0123     struct ehci_caps __iomem *caps;
0124     struct ehci_regs __iomem *regs;
0125     struct ehci_dbg_port __iomem *debug;
0126 
0127     __u32           hcs_params; /* cached register copy */
0128     spinlock_t      lock;
0129     enum ehci_rh_state  rh_state;
0130 
0131     /* general schedule support */
0132     bool            scanning:1;
0133     bool            need_rescan:1;
0134     bool            intr_unlinking:1;
0135     bool            iaa_in_progress:1;
0136     bool            async_unlinking:1;
0137     bool            shutdown:1;
0138     struct ehci_qh      *qh_scan_next;
0139 
0140     /* async schedule support */
0141     struct ehci_qh      *async;
0142     struct ehci_qh      *dummy;     /* For AMD quirk use */
0143     struct list_head    async_unlink;
0144     struct list_head    async_idle;
0145     unsigned        async_unlink_cycle;
0146     unsigned        async_count;    /* async activity count */
0147     __hc32          old_current;    /* Test for QH becoming */
0148     __hc32          old_token;  /*  inactive during unlink */
0149 
0150     /* periodic schedule support */
0151 #define DEFAULT_I_TDPS      1024        /* some HCs can do less */
0152     unsigned        periodic_size;
0153     __hc32          *periodic;  /* hw periodic table */
0154     dma_addr_t      periodic_dma;
0155     struct list_head    intr_qh_list;
0156     unsigned        i_thresh;   /* uframes HC might cache */
0157 
0158     union ehci_shadow   *pshadow;   /* mirror hw periodic table */
0159     struct list_head    intr_unlink_wait;
0160     struct list_head    intr_unlink;
0161     unsigned        intr_unlink_wait_cycle;
0162     unsigned        intr_unlink_cycle;
0163     unsigned        now_frame;  /* frame from HC hardware */
0164     unsigned        last_iso_frame; /* last frame scanned for iso */
0165     unsigned        intr_count; /* intr activity count */
0166     unsigned        isoc_count; /* isoc activity count */
0167     unsigned        periodic_count; /* periodic activity count */
0168     unsigned        uframe_periodic_max; /* max periodic time per uframe */
0169 
0170 
0171     /* list of itds & sitds completed while now_frame was still active */
0172     struct list_head    cached_itd_list;
0173     struct ehci_itd     *last_itd_to_free;
0174     struct list_head    cached_sitd_list;
0175     struct ehci_sitd    *last_sitd_to_free;
0176 
0177     /* per root hub port */
0178     unsigned long       reset_done[EHCI_MAX_ROOT_PORTS];
0179 
0180     /* bit vectors (one bit per port) */
0181     unsigned long       bus_suspended;      /* which ports were
0182             already suspended at the start of a bus suspend */
0183     unsigned long       companion_ports;    /* which ports are
0184             dedicated to the companion controller */
0185     unsigned long       owned_ports;        /* which ports are
0186             owned by the companion during a bus suspend */
0187     unsigned long       port_c_suspend;     /* which ports have
0188             the change-suspend feature turned on */
0189     unsigned long       suspended_ports;    /* which ports are
0190             suspended */
0191     unsigned long       resuming_ports;     /* which ports have
0192             started to resume */
0193 
0194     /* per-HC memory pools (could be per-bus, but ...) */
0195     struct dma_pool     *qh_pool;   /* qh per active urb */
0196     struct dma_pool     *qtd_pool;  /* one or more per qh */
0197     struct dma_pool     *itd_pool;  /* itd per iso urb */
0198     struct dma_pool     *sitd_pool; /* sitd per split iso urb */
0199 
0200     unsigned        random_frame;
0201     unsigned long       next_statechange;
0202     ktime_t         last_periodic_enable;
0203     u32         command;
0204 
0205     /* SILICON QUIRKS */
0206     unsigned        no_selective_suspend:1;
0207     unsigned        has_fsl_port_bug:1; /* FreeScale */
0208     unsigned        has_fsl_hs_errata:1;    /* Freescale HS quirk */
0209     unsigned        has_fsl_susp_errata:1;  /* NXP SUSP quirk */
0210     unsigned        big_endian_mmio:1;
0211     unsigned        big_endian_desc:1;
0212     unsigned        big_endian_capbase:1;
0213     unsigned        has_amcc_usb23:1;
0214     unsigned        need_io_watchdog:1;
0215     unsigned        amd_pll_fix:1;
0216     unsigned        use_dummy_qh:1; /* AMD Frame List table quirk*/
0217     unsigned        has_synopsys_hc_bug:1; /* Synopsys HC */
0218     unsigned        frame_index_bug:1; /* MosChip (AKA NetMos) */
0219     unsigned        need_oc_pp_cycle:1; /* MPC834X port power */
0220     unsigned        imx28_write_fix:1; /* For Freescale i.MX28 */
0221     unsigned        spurious_oc:1;
0222     unsigned        is_aspeed:1;
0223     unsigned        zx_wakeup_clear_needed:1;
0224 
0225     /* required for usb32 quirk */
0226     #define OHCI_CTRL_HCFS          (3 << 6)
0227     #define OHCI_USB_OPER           (2 << 6)
0228     #define OHCI_USB_SUSPEND        (3 << 6)
0229 
0230     #define OHCI_HCCTRL_OFFSET      0x4
0231     #define OHCI_HCCTRL_LEN         0x4
0232     __hc32          *ohci_hcctrl_reg;
0233     unsigned        has_hostpc:1;
0234     unsigned        has_tdi_phy_lpm:1;
0235     unsigned        has_ppcd:1; /* support per-port change bits */
0236     u8          sbrn;       /* packed release number */
0237 
0238     /* irq statistics */
0239 #ifdef EHCI_STATS
0240     struct ehci_stats   stats;
0241 #   define INCR(x) ((x)++)
0242 #else
0243 #   define INCR(x) do {} while (0)
0244 #endif
0245 
0246     /* debug files */
0247 #ifdef CONFIG_DYNAMIC_DEBUG
0248     struct dentry       *debug_dir;
0249 #endif
0250 
0251     /* bandwidth usage */
0252 #define EHCI_BANDWIDTH_SIZE 64
0253 #define EHCI_BANDWIDTH_FRAMES   (EHCI_BANDWIDTH_SIZE >> 3)
0254     u8          bandwidth[EHCI_BANDWIDTH_SIZE];
0255                         /* us allocated per uframe */
0256     u8          tt_budget[EHCI_BANDWIDTH_SIZE];
0257                         /* us budgeted per uframe */
0258     struct list_head    tt_list;
0259 
0260     /* platform-specific data -- must come last */
0261     unsigned long       priv[] __aligned(sizeof(s64));
0262 };
0263 
0264 /* convert between an HCD pointer and the corresponding EHCI_HCD */
0265 static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
0266 {
0267     return (struct ehci_hcd *) (hcd->hcd_priv);
0268 }
0269 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
0270 {
0271     return container_of((void *) ehci, struct usb_hcd, hcd_priv);
0272 }
0273 
0274 /*-------------------------------------------------------------------------*/
0275 
0276 #include <linux/usb/ehci_def.h>
0277 
0278 /*-------------------------------------------------------------------------*/
0279 
0280 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
0281 
0282 /*
0283  * EHCI Specification 0.95 Section 3.5
0284  * QTD: describe data transfer components (buffer, direction, ...)
0285  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
0286  *
0287  * These are associated only with "QH" (Queue Head) structures,
0288  * used with control, bulk, and interrupt transfers.
0289  */
0290 struct ehci_qtd {
0291     /* first part defined by EHCI spec */
0292     __hc32          hw_next;    /* see EHCI 3.5.1 */
0293     __hc32          hw_alt_next;    /* see EHCI 3.5.2 */
0294     __hc32          hw_token;       /* see EHCI 3.5.3 */
0295 #define QTD_TOGGLE  (1 << 31)   /* data toggle */
0296 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
0297 #define QTD_IOC     (1 << 15)   /* interrupt on complete */
0298 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
0299 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
0300 #define QTD_STS_ACTIVE  (1 << 7)    /* HC may execute this */
0301 #define QTD_STS_HALT    (1 << 6)    /* halted on error */
0302 #define QTD_STS_DBE (1 << 5)    /* data buffer error (in HC) */
0303 #define QTD_STS_BABBLE  (1 << 4)    /* device was babbling (qtd halted) */
0304 #define QTD_STS_XACT    (1 << 3)    /* device gave illegal response */
0305 #define QTD_STS_MMF (1 << 2)    /* incomplete split transaction */
0306 #define QTD_STS_STS (1 << 1)    /* split transaction state */
0307 #define QTD_STS_PING    (1 << 0)    /* issue PING? */
0308 
0309 #define ACTIVE_BIT(ehci)    cpu_to_hc32(ehci, QTD_STS_ACTIVE)
0310 #define HALT_BIT(ehci)      cpu_to_hc32(ehci, QTD_STS_HALT)
0311 #define STATUS_BIT(ehci)    cpu_to_hc32(ehci, QTD_STS_STS)
0312 
0313     __hc32          hw_buf[5];        /* see EHCI 3.5.4 */
0314     __hc32          hw_buf_hi[5];        /* Appendix B */
0315 
0316     /* the rest is HCD-private */
0317     dma_addr_t      qtd_dma;        /* qtd address */
0318     struct list_head    qtd_list;       /* sw qtd list */
0319     struct urb      *urb;           /* qtd's urb */
0320     size_t          length;         /* length of buffer */
0321 } __aligned(32);
0322 
0323 /* mask NakCnt+T in qh->hw_alt_next */
0324 #define QTD_MASK(ehci)  cpu_to_hc32(ehci, ~0x1f)
0325 
0326 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
0327 
0328 /*-------------------------------------------------------------------------*/
0329 
0330 /* type tag from {qh,itd,sitd,fstn}->hw_next */
0331 #define Q_NEXT_TYPE(ehci, dma)  ((dma) & cpu_to_hc32(ehci, 3 << 1))
0332 
0333 /*
0334  * Now the following defines are not converted using the
0335  * cpu_to_le32() macro anymore, since we have to support
0336  * "dynamic" switching between be and le support, so that the driver
0337  * can be used on one system with SoC EHCI controller using big-endian
0338  * descriptors as well as a normal little-endian PCI EHCI controller.
0339  */
0340 /* values for that type tag */
0341 #define Q_TYPE_ITD  (0 << 1)
0342 #define Q_TYPE_QH   (1 << 1)
0343 #define Q_TYPE_SITD (2 << 1)
0344 #define Q_TYPE_FSTN (3 << 1)
0345 
0346 /* next async queue entry, or pointer to interrupt/periodic QH */
0347 #define QH_NEXT(ehci, dma) \
0348         (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
0349 
0350 /* for periodic/async schedules and qtd lists, mark end of list */
0351 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
0352 
0353 /*
0354  * Entries in periodic shadow table are pointers to one of four kinds
0355  * of data structure.  That's dictated by the hardware; a type tag is
0356  * encoded in the low bits of the hardware's periodic schedule.  Use
0357  * Q_NEXT_TYPE to get the tag.
0358  *
0359  * For entries in the async schedule, the type tag always says "qh".
0360  */
0361 union ehci_shadow {
0362     struct ehci_qh      *qh;        /* Q_TYPE_QH */
0363     struct ehci_itd     *itd;       /* Q_TYPE_ITD */
0364     struct ehci_sitd    *sitd;      /* Q_TYPE_SITD */
0365     struct ehci_fstn    *fstn;      /* Q_TYPE_FSTN */
0366     __hc32          *hw_next;   /* (all types) */
0367     void            *ptr;
0368 };
0369 
0370 /*-------------------------------------------------------------------------*/
0371 
0372 /*
0373  * EHCI Specification 0.95 Section 3.6
0374  * QH: describes control/bulk/interrupt endpoints
0375  * See Fig 3-7 "Queue Head Structure Layout".
0376  *
0377  * These appear in both the async and (for interrupt) periodic schedules.
0378  */
0379 
0380 /* first part defined by EHCI spec */
0381 struct ehci_qh_hw {
0382     __hc32          hw_next;    /* see EHCI 3.6.1 */
0383     __hc32          hw_info1;       /* see EHCI 3.6.2 */
0384 #define QH_CONTROL_EP   (1 << 27)   /* FS/LS control endpoint */
0385 #define QH_HEAD     (1 << 15)   /* Head of async reclamation list */
0386 #define QH_TOGGLE_CTL   (1 << 14)   /* Data toggle control */
0387 #define QH_HIGH_SPEED   (2 << 12)   /* Endpoint speed */
0388 #define QH_LOW_SPEED    (1 << 12)
0389 #define QH_FULL_SPEED   (0 << 12)
0390 #define QH_INACTIVATE   (1 << 7)    /* Inactivate on next transaction */
0391     __hc32          hw_info2;        /* see EHCI 3.6.2 */
0392 #define QH_SMASK    0x000000ff
0393 #define QH_CMASK    0x0000ff00
0394 #define QH_HUBADDR  0x007f0000
0395 #define QH_HUBPORT  0x3f800000
0396 #define QH_MULT     0xc0000000
0397     __hc32          hw_current; /* qtd list - see EHCI 3.6.4 */
0398 
0399     /* qtd overlay (hardware parts of a struct ehci_qtd) */
0400     __hc32          hw_qtd_next;
0401     __hc32          hw_alt_next;
0402     __hc32          hw_token;
0403     __hc32          hw_buf[5];
0404     __hc32          hw_buf_hi[5];
0405 } __aligned(32);
0406 
0407 struct ehci_qh {
0408     struct ehci_qh_hw   *hw;        /* Must come first */
0409     /* the rest is HCD-private */
0410     dma_addr_t      qh_dma;     /* address of qh */
0411     union ehci_shadow   qh_next;    /* ptr to qh; or periodic */
0412     struct list_head    qtd_list;   /* sw qtd list */
0413     struct list_head    intr_node;  /* list of intr QHs */
0414     struct ehci_qtd     *dummy;
0415     struct list_head    unlink_node;
0416     struct ehci_per_sched   ps;     /* scheduling info */
0417 
0418     unsigned        unlink_cycle;
0419 
0420     u8          qh_state;
0421 #define QH_STATE_LINKED     1       /* HC sees this */
0422 #define QH_STATE_UNLINK     2       /* HC may still see this */
0423 #define QH_STATE_IDLE       3       /* HC doesn't see this */
0424 #define QH_STATE_UNLINK_WAIT    4       /* LINKED and on unlink q */
0425 #define QH_STATE_COMPLETING 5       /* don't touch token.HALT */
0426 
0427     u8          xacterrs;   /* XactErr retry counter */
0428 #define QH_XACTERR_MAX      32      /* XactErr retry limit */
0429 
0430     u8          unlink_reason;
0431 #define QH_UNLINK_HALTED    0x01        /* Halt flag is set */
0432 #define QH_UNLINK_SHORT_READ    0x02        /* Recover from a short read */
0433 #define QH_UNLINK_DUMMY_OVERLAY 0x04        /* QH overlayed the dummy TD */
0434 #define QH_UNLINK_SHUTDOWN  0x08        /* The HC isn't running */
0435 #define QH_UNLINK_QUEUE_EMPTY   0x10        /* Reached end of the queue */
0436 #define QH_UNLINK_REQUESTED 0x20        /* Disable, reset, or dequeue */
0437 
0438     u8          gap_uf;     /* uframes split/csplit gap */
0439 
0440     unsigned        is_out:1;   /* bulk or intr OUT */
0441     unsigned        clearing_tt:1;  /* Clear-TT-Buf in progress */
0442     unsigned        dequeue_during_giveback:1;
0443     unsigned        should_be_inactive:1;
0444 };
0445 
0446 /*-------------------------------------------------------------------------*/
0447 
0448 /* description of one iso transaction (up to 3 KB data if highspeed) */
0449 struct ehci_iso_packet {
0450     /* These will be copied to iTD when scheduling */
0451     u64         bufp;       /* itd->hw_bufp{,_hi}[pg] |= */
0452     __hc32          transaction;    /* itd->hw_transaction[i] |= */
0453     u8          cross;      /* buf crosses pages */
0454     /* for full speed OUT splits */
0455     u32         buf1;
0456 };
0457 
0458 /* temporary schedule data for packets from iso urbs (both speeds)
0459  * each packet is one logical usb transaction to the device (not TT),
0460  * beginning at stream->next_uframe
0461  */
0462 struct ehci_iso_sched {
0463     struct list_head    td_list;
0464     unsigned        span;
0465     unsigned        first_packet;
0466     struct ehci_iso_packet  packet[];
0467 };
0468 
0469 /*
0470  * ehci_iso_stream - groups all (s)itds for this endpoint.
0471  * acts like a qh would, if EHCI had them for ISO.
0472  */
0473 struct ehci_iso_stream {
0474     /* first field matches ehci_hq, but is NULL */
0475     struct ehci_qh_hw   *hw;
0476 
0477     u8          bEndpointAddress;
0478     u8          highspeed;
0479     struct list_head    td_list;    /* queued itds/sitds */
0480     struct list_head    free_list;  /* list of unused itds/sitds */
0481 
0482     /* output of (re)scheduling */
0483     struct ehci_per_sched   ps;     /* scheduling info */
0484     unsigned        next_uframe;
0485     __hc32          splits;
0486 
0487     /* the rest is derived from the endpoint descriptor,
0488      * including the extra info for hw_bufp[0..2]
0489      */
0490     u16         uperiod;    /* period in uframes */
0491     u16         maxp;
0492     unsigned        bandwidth;
0493 
0494     /* This is used to initialize iTD's hw_bufp fields */
0495     __hc32          buf0;
0496     __hc32          buf1;
0497     __hc32          buf2;
0498 
0499     /* this is used to initialize sITD's tt info */
0500     __hc32          address;
0501 };
0502 
0503 /*-------------------------------------------------------------------------*/
0504 
0505 /*
0506  * EHCI Specification 0.95 Section 3.3
0507  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
0508  *
0509  * Schedule records for high speed iso xfers
0510  */
0511 struct ehci_itd {
0512     /* first part defined by EHCI spec */
0513     __hc32          hw_next;           /* see EHCI 3.3.1 */
0514     __hc32          hw_transaction[8]; /* see EHCI 3.3.2 */
0515 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
0516 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
0517 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
0518 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
0519 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
0520 #define EHCI_ITD_IOC        (1 << 15)   /* interrupt on complete */
0521 
0522 #define ITD_ACTIVE(ehci)    cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
0523 
0524     __hc32          hw_bufp[7]; /* see EHCI 3.3.3 */
0525     __hc32          hw_bufp_hi[7];  /* Appendix B */
0526 
0527     /* the rest is HCD-private */
0528     dma_addr_t      itd_dma;    /* for this itd */
0529     union ehci_shadow   itd_next;   /* ptr to periodic q entry */
0530 
0531     struct urb      *urb;
0532     struct ehci_iso_stream  *stream;    /* endpoint's queue */
0533     struct list_head    itd_list;   /* list of stream's itds */
0534 
0535     /* any/all hw_transactions here may be used by that urb */
0536     unsigned        frame;      /* where scheduled */
0537     unsigned        pg;
0538     unsigned        index[8];   /* in urb->iso_frame_desc */
0539 } __aligned(32);
0540 
0541 /*-------------------------------------------------------------------------*/
0542 
0543 /*
0544  * EHCI Specification 0.95 Section 3.4
0545  * siTD, aka split-transaction isochronous Transfer Descriptor
0546  *       ... describe full speed iso xfers through TT in hubs
0547  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
0548  */
0549 struct ehci_sitd {
0550     /* first part defined by EHCI spec */
0551     __hc32          hw_next;
0552 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
0553     __hc32          hw_fullspeed_ep;    /* EHCI table 3-9 */
0554     __hc32          hw_uframe;      /* EHCI table 3-10 */
0555     __hc32          hw_results;     /* EHCI table 3-11 */
0556 #define SITD_IOC    (1 << 31)   /* interrupt on completion */
0557 #define SITD_PAGE   (1 << 30)   /* buffer 0/1 */
0558 #define SITD_LENGTH(x)  (((x) >> 16) & 0x3ff)
0559 #define SITD_STS_ACTIVE (1 << 7)    /* HC may execute this */
0560 #define SITD_STS_ERR    (1 << 6)    /* error from TT */
0561 #define SITD_STS_DBE    (1 << 5)    /* data buffer error (in HC) */
0562 #define SITD_STS_BABBLE (1 << 4)    /* device was babbling */
0563 #define SITD_STS_XACT   (1 << 3)    /* illegal IN response */
0564 #define SITD_STS_MMF    (1 << 2)    /* incomplete split transaction */
0565 #define SITD_STS_STS    (1 << 1)    /* split transaction state */
0566 
0567 #define SITD_ACTIVE(ehci)   cpu_to_hc32(ehci, SITD_STS_ACTIVE)
0568 
0569     __hc32          hw_buf[2];      /* EHCI table 3-12 */
0570     __hc32          hw_backpointer;     /* EHCI table 3-13 */
0571     __hc32          hw_buf_hi[2];       /* Appendix B */
0572 
0573     /* the rest is HCD-private */
0574     dma_addr_t      sitd_dma;
0575     union ehci_shadow   sitd_next;  /* ptr to periodic q entry */
0576 
0577     struct urb      *urb;
0578     struct ehci_iso_stream  *stream;    /* endpoint's queue */
0579     struct list_head    sitd_list;  /* list of stream's sitds */
0580     unsigned        frame;
0581     unsigned        index;
0582 } __aligned(32);
0583 
0584 /*-------------------------------------------------------------------------*/
0585 
0586 /*
0587  * EHCI Specification 0.96 Section 3.7
0588  * Periodic Frame Span Traversal Node (FSTN)
0589  *
0590  * Manages split interrupt transactions (using TT) that span frame boundaries
0591  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
0592  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
0593  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
0594  */
0595 struct ehci_fstn {
0596     __hc32          hw_next;    /* any periodic q entry */
0597     __hc32          hw_prev;    /* qh or EHCI_LIST_END */
0598 
0599     /* the rest is HCD-private */
0600     dma_addr_t      fstn_dma;
0601     union ehci_shadow   fstn_next;  /* ptr to periodic q entry */
0602 } __aligned(32);
0603 
0604 /*-------------------------------------------------------------------------*/
0605 
0606 /*
0607  * USB-2.0 Specification Sections 11.14 and 11.18
0608  * Scheduling and budgeting split transactions using TTs
0609  *
0610  * A hub can have a single TT for all its ports, or multiple TTs (one for each
0611  * port).  The bandwidth and budgeting information for the full/low-speed bus
0612  * below each TT is self-contained and independent of the other TTs or the
0613  * high-speed bus.
0614  *
0615  * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
0616  * to an interrupt or isochronous endpoint for each frame.  "Budget" refers to
0617  * the best-case estimate of the number of full-speed bytes allocated to an
0618  * endpoint for each microframe within an allocated frame.
0619  *
0620  * Removal of an endpoint invalidates a TT's budget.  Instead of trying to
0621  * keep an up-to-date record, we recompute the budget when it is needed.
0622  */
0623 
0624 struct ehci_tt {
0625     u16         bandwidth[EHCI_BANDWIDTH_FRAMES];
0626 
0627     struct list_head    tt_list;    /* List of all ehci_tt's */
0628     struct list_head    ps_list;    /* Items using this TT */
0629     struct usb_tt       *usb_tt;
0630     int         tt_port;    /* TT port number */
0631 };
0632 
0633 /*-------------------------------------------------------------------------*/
0634 
0635 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
0636 
0637 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)  \
0638         ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
0639 
0640 #define ehci_prepare_ports_for_controller_resume(ehci)          \
0641         ehci_adjust_port_wakeup_flags(ehci, false, false)
0642 
0643 /*-------------------------------------------------------------------------*/
0644 
0645 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
0646 
0647 /*
0648  * Some EHCI controllers have a Transaction Translator built into the
0649  * root hub. This is a non-standard feature.  Each controller will need
0650  * to add code to the following inline functions, and call them as
0651  * needed (mostly in root hub code).
0652  */
0653 
0654 #define ehci_is_TDI(e)          (ehci_to_hcd(e)->has_tt)
0655 
0656 /* Returns the speed of a device attached to a port on the root hub. */
0657 static inline unsigned int
0658 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
0659 {
0660     if (ehci_is_TDI(ehci)) {
0661         switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
0662         case 0:
0663             return 0;
0664         case 1:
0665             return USB_PORT_STAT_LOW_SPEED;
0666         case 2:
0667         default:
0668             return USB_PORT_STAT_HIGH_SPEED;
0669         }
0670     }
0671     return USB_PORT_STAT_HIGH_SPEED;
0672 }
0673 
0674 #else
0675 
0676 #define ehci_is_TDI(e)          (0)
0677 
0678 #define ehci_port_speed(ehci, portsc)   USB_PORT_STAT_HIGH_SPEED
0679 #endif
0680 
0681 /*-------------------------------------------------------------------------*/
0682 
0683 #ifdef CONFIG_PPC_83xx
0684 /* Some Freescale processors have an erratum in which the TT
0685  * port number in the queue head was 0..N-1 instead of 1..N.
0686  */
0687 #define ehci_has_fsl_portno_bug(e)      ((e)->has_fsl_port_bug)
0688 #else
0689 #define ehci_has_fsl_portno_bug(e)      (0)
0690 #endif
0691 
0692 #define PORTSC_FSL_PFSC 24  /* Port Force Full-Speed Connect */
0693 
0694 #if defined(CONFIG_PPC_85xx)
0695 /* Some Freescale processors have an erratum (USB A-005275) in which
0696  * incoming packets get corrupted in HS mode
0697  */
0698 #define ehci_has_fsl_hs_errata(e)   ((e)->has_fsl_hs_errata)
0699 #else
0700 #define ehci_has_fsl_hs_errata(e)   (0)
0701 #endif
0702 
0703 /*
0704  * Some Freescale/NXP processors have an erratum (USB A-005697)
0705  * in which we need to wait for 10ms for bus to enter suspend mode
0706  * after setting SUSP bit.
0707  */
0708 #define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
0709 
0710 /*
0711  * While most USB host controllers implement their registers in
0712  * little-endian format, a minority (celleb companion chip) implement
0713  * them in big endian format.
0714  *
0715  * This attempts to support either format at compile time without a
0716  * runtime penalty, or both formats with the additional overhead
0717  * of checking a flag bit.
0718  *
0719  * ehci_big_endian_capbase is a special quirk for controllers that
0720  * implement the HC capability registers as separate registers and not
0721  * as fields of a 32-bit register.
0722  */
0723 
0724 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
0725 #define ehci_big_endian_mmio(e)     ((e)->big_endian_mmio)
0726 #define ehci_big_endian_capbase(e)  ((e)->big_endian_capbase)
0727 #else
0728 #define ehci_big_endian_mmio(e)     0
0729 #define ehci_big_endian_capbase(e)  0
0730 #endif
0731 
0732 /*
0733  * Big-endian read/write functions are arch-specific.
0734  * Other arches can be added if/when they're needed.
0735  */
0736 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
0737 #define readl_be(addr)      __raw_readl((__force unsigned *)addr)
0738 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
0739 #endif
0740 
0741 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
0742         __u32 __iomem *regs)
0743 {
0744 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
0745     return ehci_big_endian_mmio(ehci) ?
0746         readl_be(regs) :
0747         readl(regs);
0748 #else
0749     return readl(regs);
0750 #endif
0751 }
0752 
0753 #ifdef CONFIG_SOC_IMX28
0754 static inline void imx28_ehci_writel(const unsigned int val,
0755         volatile __u32 __iomem *addr)
0756 {
0757     __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
0758 }
0759 #else
0760 static inline void imx28_ehci_writel(const unsigned int val,
0761         volatile __u32 __iomem *addr)
0762 {
0763 }
0764 #endif
0765 static inline void ehci_writel(const struct ehci_hcd *ehci,
0766         const unsigned int val, __u32 __iomem *regs)
0767 {
0768 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
0769     ehci_big_endian_mmio(ehci) ?
0770         writel_be(val, regs) :
0771         writel(val, regs);
0772 #else
0773     if (ehci->imx28_write_fix)
0774         imx28_ehci_writel(val, regs);
0775     else
0776         writel(val, regs);
0777 #endif
0778 }
0779 
0780 /*
0781  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
0782  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
0783  * Other common bits are dependent on has_amcc_usb23 quirk flag.
0784  */
0785 #ifdef CONFIG_44x
0786 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
0787 {
0788     u32 hc_control;
0789 
0790     hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
0791     if (operational)
0792         hc_control |= OHCI_USB_OPER;
0793     else
0794         hc_control |= OHCI_USB_SUSPEND;
0795 
0796     writel_be(hc_control, ehci->ohci_hcctrl_reg);
0797     (void) readl_be(ehci->ohci_hcctrl_reg);
0798 }
0799 #else
0800 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
0801 { }
0802 #endif
0803 
0804 /*-------------------------------------------------------------------------*/
0805 
0806 /*
0807  * The AMCC 440EPx not only implements its EHCI registers in big-endian
0808  * format, but also its DMA data structures (descriptors).
0809  *
0810  * EHCI controllers accessed through PCI work normally (little-endian
0811  * everywhere), so we won't bother supporting a BE-only mode for now.
0812  */
0813 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
0814 #define ehci_big_endian_desc(e)     ((e)->big_endian_desc)
0815 
0816 /* cpu to ehci */
0817 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
0818 {
0819     return ehci_big_endian_desc(ehci)
0820         ? (__force __hc32)cpu_to_be32(x)
0821         : (__force __hc32)cpu_to_le32(x);
0822 }
0823 
0824 /* ehci to cpu */
0825 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
0826 {
0827     return ehci_big_endian_desc(ehci)
0828         ? be32_to_cpu((__force __be32)x)
0829         : le32_to_cpu((__force __le32)x);
0830 }
0831 
0832 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
0833 {
0834     return ehci_big_endian_desc(ehci)
0835         ? be32_to_cpup((__force __be32 *)x)
0836         : le32_to_cpup((__force __le32 *)x);
0837 }
0838 
0839 #else
0840 
0841 /* cpu to ehci */
0842 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
0843 {
0844     return cpu_to_le32(x);
0845 }
0846 
0847 /* ehci to cpu */
0848 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
0849 {
0850     return le32_to_cpu(x);
0851 }
0852 
0853 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
0854 {
0855     return le32_to_cpup(x);
0856 }
0857 
0858 #endif
0859 
0860 /*-------------------------------------------------------------------------*/
0861 
0862 #define ehci_dbg(ehci, fmt, args...) \
0863     dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
0864 #define ehci_err(ehci, fmt, args...) \
0865     dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
0866 #define ehci_info(ehci, fmt, args...) \
0867     dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
0868 #define ehci_warn(ehci, fmt, args...) \
0869     dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
0870 
0871 /*-------------------------------------------------------------------------*/
0872 
0873 /* Declarations of things exported for use by ehci platform drivers */
0874 
0875 struct ehci_driver_overrides {
0876     size_t      extra_priv_size;
0877     int     (*reset)(struct usb_hcd *hcd);
0878     int     (*port_power)(struct usb_hcd *hcd,
0879                 int portnum, bool enable);
0880 };
0881 
0882 extern void ehci_init_driver(struct hc_driver *drv,
0883                 const struct ehci_driver_overrides *over);
0884 extern int  ehci_setup(struct usb_hcd *hcd);
0885 extern int  ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
0886                 u32 mask, u32 done, int usec);
0887 extern int  ehci_reset(struct ehci_hcd *ehci);
0888 
0889 extern int  ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
0890 extern int  ehci_resume(struct usb_hcd *hcd, bool force_reset);
0891 extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
0892             bool suspending, bool do_wakeup);
0893 
0894 extern int  ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
0895                  u16 wIndex, char *buf, u16 wLength);
0896 
0897 #endif /* __LINUX_EHCI_HCD_H */
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