Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2001-2004 by David Brownell
0004  */
0005 
0006 /* this file is part of ehci-hcd.c */
0007 
0008 /*-------------------------------------------------------------------------*/
0009 
0010 /*
0011  * EHCI hardware queue manipulation ... the core.  QH/QTD manipulation.
0012  *
0013  * Control, bulk, and interrupt traffic all use "qh" lists.  They list "qtd"
0014  * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned
0015  * buffers needed for the larger number).  We use one QH per endpoint, queue
0016  * multiple urbs (all three types) per endpoint.  URBs may need several qtds.
0017  *
0018  * ISO traffic uses "ISO TD" (itd, and sitd) records, and (along with
0019  * interrupts) needs careful scheduling.  Performance improvements can be
0020  * an ongoing challenge.  That's in "ehci-sched.c".
0021  *
0022  * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs,
0023  * or otherwise through transaction translators (TTs) in USB 2.0 hubs using
0024  * (b) special fields in qh entries or (c) split iso entries.  TTs will
0025  * buffer low/full speed data so the host collects it at high speed.
0026  */
0027 
0028 /*-------------------------------------------------------------------------*/
0029 
0030 /* PID Codes that are used here, from EHCI specification, Table 3-16. */
0031 #define PID_CODE_IN    1
0032 #define PID_CODE_SETUP 2
0033 
0034 /* fill a qtd, returning how much of the buffer we were able to queue up */
0035 
0036 static unsigned int
0037 qtd_fill(struct ehci_hcd *ehci, struct ehci_qtd *qtd, dma_addr_t buf,
0038           size_t len, int token, int maxpacket)
0039 {
0040     unsigned int count;
0041     u64 addr = buf;
0042     int i;
0043 
0044     /* one buffer entry per 4K ... first might be short or unaligned */
0045     qtd->hw_buf[0] = cpu_to_hc32(ehci, (u32)addr);
0046     qtd->hw_buf_hi[0] = cpu_to_hc32(ehci, (u32)(addr >> 32));
0047     count = 0x1000 - (buf & 0x0fff);    /* rest of that page */
0048     if (likely (len < count))       /* ... iff needed */
0049         count = len;
0050     else {
0051         buf +=  0x1000;
0052         buf &= ~0x0fff;
0053 
0054         /* per-qtd limit: from 16K to 20K (best alignment) */
0055         for (i = 1; count < len && i < 5; i++) {
0056             addr = buf;
0057             qtd->hw_buf[i] = cpu_to_hc32(ehci, (u32)addr);
0058             qtd->hw_buf_hi[i] = cpu_to_hc32(ehci,
0059                     (u32)(addr >> 32));
0060             buf += 0x1000;
0061             if ((count + 0x1000) < len)
0062                 count += 0x1000;
0063             else
0064                 count = len;
0065         }
0066 
0067         /* short packets may only terminate transfers */
0068         if (count != len)
0069             count -= (count % maxpacket);
0070     }
0071     qtd->hw_token = cpu_to_hc32(ehci, (count << 16) | token);
0072     qtd->length = count;
0073 
0074     return count;
0075 }
0076 
0077 /*-------------------------------------------------------------------------*/
0078 
0079 static inline void
0080 qh_update (struct ehci_hcd *ehci, struct ehci_qh *qh, struct ehci_qtd *qtd)
0081 {
0082     struct ehci_qh_hw *hw = qh->hw;
0083 
0084     /* writes to an active overlay are unsafe */
0085     WARN_ON(qh->qh_state != QH_STATE_IDLE);
0086 
0087     hw->hw_qtd_next = QTD_NEXT(ehci, qtd->qtd_dma);
0088     hw->hw_alt_next = EHCI_LIST_END(ehci);
0089 
0090     /* Except for control endpoints, we make hardware maintain data
0091      * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
0092      * and set the pseudo-toggle in udev. Only usb_clear_halt() will
0093      * ever clear it.
0094      */
0095     if (!(hw->hw_info1 & cpu_to_hc32(ehci, QH_TOGGLE_CTL))) {
0096         unsigned    is_out, epnum;
0097 
0098         is_out = qh->is_out;
0099         epnum = (hc32_to_cpup(ehci, &hw->hw_info1) >> 8) & 0x0f;
0100         if (unlikely(!usb_gettoggle(qh->ps.udev, epnum, is_out))) {
0101             hw->hw_token &= ~cpu_to_hc32(ehci, QTD_TOGGLE);
0102             usb_settoggle(qh->ps.udev, epnum, is_out, 1);
0103         }
0104     }
0105 
0106     hw->hw_token &= cpu_to_hc32(ehci, QTD_TOGGLE | QTD_STS_PING);
0107 }
0108 
0109 /* if it weren't for a common silicon quirk (writing the dummy into the qh
0110  * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
0111  * recovery (including urb dequeue) would need software changes to a QH...
0112  */
0113 static void
0114 qh_refresh (struct ehci_hcd *ehci, struct ehci_qh *qh)
0115 {
0116     struct ehci_qtd *qtd;
0117 
0118     qtd = list_entry(qh->qtd_list.next, struct ehci_qtd, qtd_list);
0119 
0120     /*
0121      * first qtd may already be partially processed.
0122      * If we come here during unlink, the QH overlay region
0123      * might have reference to the just unlinked qtd. The
0124      * qtd is updated in qh_completions(). Update the QH
0125      * overlay here.
0126      */
0127     if (qh->hw->hw_token & ACTIVE_BIT(ehci)) {
0128         qh->hw->hw_qtd_next = qtd->hw_next;
0129         if (qh->should_be_inactive)
0130             ehci_warn(ehci, "qh %p should be inactive!\n", qh);
0131     } else {
0132         qh_update(ehci, qh, qtd);
0133     }
0134     qh->should_be_inactive = 0;
0135 }
0136 
0137 /*-------------------------------------------------------------------------*/
0138 
0139 static void qh_link_async(struct ehci_hcd *ehci, struct ehci_qh *qh);
0140 
0141 static void ehci_clear_tt_buffer_complete(struct usb_hcd *hcd,
0142         struct usb_host_endpoint *ep)
0143 {
0144     struct ehci_hcd     *ehci = hcd_to_ehci(hcd);
0145     struct ehci_qh      *qh = ep->hcpriv;
0146     unsigned long       flags;
0147 
0148     spin_lock_irqsave(&ehci->lock, flags);
0149     qh->clearing_tt = 0;
0150     if (qh->qh_state == QH_STATE_IDLE && !list_empty(&qh->qtd_list)
0151             && ehci->rh_state == EHCI_RH_RUNNING)
0152         qh_link_async(ehci, qh);
0153     spin_unlock_irqrestore(&ehci->lock, flags);
0154 }
0155 
0156 static void ehci_clear_tt_buffer(struct ehci_hcd *ehci, struct ehci_qh *qh,
0157         struct urb *urb, u32 token)
0158 {
0159 
0160     /* If an async split transaction gets an error or is unlinked,
0161      * the TT buffer may be left in an indeterminate state.  We
0162      * have to clear the TT buffer.
0163      *
0164      * Note: this routine is never called for Isochronous transfers.
0165      */
0166     if (urb->dev->tt && !usb_pipeint(urb->pipe) && !qh->clearing_tt) {
0167 #ifdef CONFIG_DYNAMIC_DEBUG
0168         struct usb_device *tt = urb->dev->tt->hub;
0169         dev_dbg(&tt->dev,
0170             "clear tt buffer port %d, a%d ep%d t%08x\n",
0171             urb->dev->ttport, urb->dev->devnum,
0172             usb_pipeendpoint(urb->pipe), token);
0173 #endif /* CONFIG_DYNAMIC_DEBUG */
0174         if (!ehci_is_TDI(ehci)
0175                 || urb->dev->tt->hub !=
0176                    ehci_to_hcd(ehci)->self.root_hub) {
0177             if (usb_hub_clear_tt_buffer(urb) == 0)
0178                 qh->clearing_tt = 1;
0179         } else {
0180 
0181             /* REVISIT ARC-derived cores don't clear the root
0182              * hub TT buffer in this way...
0183              */
0184         }
0185     }
0186 }
0187 
0188 static int qtd_copy_status (
0189     struct ehci_hcd *ehci,
0190     struct urb *urb,
0191     size_t length,
0192     u32 token
0193 )
0194 {
0195     int status = -EINPROGRESS;
0196 
0197     /* count IN/OUT bytes, not SETUP (even short packets) */
0198     if (likely(QTD_PID(token) != PID_CODE_SETUP))
0199         urb->actual_length += length - QTD_LENGTH (token);
0200 
0201     /* don't modify error codes */
0202     if (unlikely(urb->unlinked))
0203         return status;
0204 
0205     /* force cleanup after short read; not always an error */
0206     if (unlikely (IS_SHORT_READ (token)))
0207         status = -EREMOTEIO;
0208 
0209     /* serious "can't proceed" faults reported by the hardware */
0210     if (token & QTD_STS_HALT) {
0211         if (token & QTD_STS_BABBLE) {
0212             /* FIXME "must" disable babbling device's port too */
0213             status = -EOVERFLOW;
0214         /*
0215          * When MMF is active and PID Code is IN, queue is halted.
0216          * EHCI Specification, Table 4-13.
0217          */
0218         } else if ((token & QTD_STS_MMF) &&
0219                     (QTD_PID(token) == PID_CODE_IN)) {
0220             status = -EPROTO;
0221         /* CERR nonzero + halt --> stall */
0222         } else if (QTD_CERR(token)) {
0223             status = -EPIPE;
0224 
0225         /* In theory, more than one of the following bits can be set
0226          * since they are sticky and the transaction is retried.
0227          * Which to test first is rather arbitrary.
0228          */
0229         } else if (token & QTD_STS_MMF) {
0230             /* fs/ls interrupt xfer missed the complete-split */
0231             status = -EPROTO;
0232         } else if (token & QTD_STS_DBE) {
0233             status = (QTD_PID (token) == 1) /* IN ? */
0234                 ? -ENOSR  /* hc couldn't read data */
0235                 : -ECOMM; /* hc couldn't write data */
0236         } else if (token & QTD_STS_XACT) {
0237             /* timeout, bad CRC, wrong PID, etc */
0238             ehci_dbg(ehci, "devpath %s ep%d%s 3strikes\n",
0239                 urb->dev->devpath,
0240                 usb_pipeendpoint(urb->pipe),
0241                 usb_pipein(urb->pipe) ? "in" : "out");
0242             status = -EPROTO;
0243         } else {    /* unknown */
0244             status = -EPROTO;
0245         }
0246     }
0247 
0248     return status;
0249 }
0250 
0251 static void
0252 ehci_urb_done(struct ehci_hcd *ehci, struct urb *urb, int status)
0253 {
0254     if (usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
0255         /* ... update hc-wide periodic stats */
0256         ehci_to_hcd(ehci)->self.bandwidth_int_reqs--;
0257     }
0258 
0259     if (unlikely(urb->unlinked)) {
0260         INCR(ehci->stats.unlink);
0261     } else {
0262         /* report non-error and short read status as zero */
0263         if (status == -EINPROGRESS || status == -EREMOTEIO)
0264             status = 0;
0265         INCR(ehci->stats.complete);
0266     }
0267 
0268 #ifdef EHCI_URB_TRACE
0269     ehci_dbg (ehci,
0270         "%s %s urb %p ep%d%s status %d len %d/%d\n",
0271         __func__, urb->dev->devpath, urb,
0272         usb_pipeendpoint (urb->pipe),
0273         usb_pipein (urb->pipe) ? "in" : "out",
0274         status,
0275         urb->actual_length, urb->transfer_buffer_length);
0276 #endif
0277 
0278     usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
0279     usb_hcd_giveback_urb(ehci_to_hcd(ehci), urb, status);
0280 }
0281 
0282 static int qh_schedule (struct ehci_hcd *ehci, struct ehci_qh *qh);
0283 
0284 /*
0285  * Process and free completed qtds for a qh, returning URBs to drivers.
0286  * Chases up to qh->hw_current.  Returns nonzero if the caller should
0287  * unlink qh.
0288  */
0289 static unsigned
0290 qh_completions (struct ehci_hcd *ehci, struct ehci_qh *qh)
0291 {
0292     struct ehci_qtd     *last, *end = qh->dummy;
0293     struct list_head    *entry, *tmp;
0294     int         last_status;
0295     int         stopped;
0296     u8          state;
0297     struct ehci_qh_hw   *hw = qh->hw;
0298 
0299     /* completions (or tasks on other cpus) must never clobber HALT
0300      * till we've gone through and cleaned everything up, even when
0301      * they add urbs to this qh's queue or mark them for unlinking.
0302      *
0303      * NOTE:  unlinking expects to be done in queue order.
0304      *
0305      * It's a bug for qh->qh_state to be anything other than
0306      * QH_STATE_IDLE, unless our caller is scan_async() or
0307      * scan_intr().
0308      */
0309     state = qh->qh_state;
0310     qh->qh_state = QH_STATE_COMPLETING;
0311     stopped = (state == QH_STATE_IDLE);
0312 
0313  rescan:
0314     last = NULL;
0315     last_status = -EINPROGRESS;
0316     qh->dequeue_during_giveback = 0;
0317 
0318     /* remove de-activated QTDs from front of queue.
0319      * after faults (including short reads), cleanup this urb
0320      * then let the queue advance.
0321      * if queue is stopped, handles unlinks.
0322      */
0323     list_for_each_safe (entry, tmp, &qh->qtd_list) {
0324         struct ehci_qtd *qtd;
0325         struct urb  *urb;
0326         u32     token = 0;
0327 
0328         qtd = list_entry (entry, struct ehci_qtd, qtd_list);
0329         urb = qtd->urb;
0330 
0331         /* clean up any state from previous QTD ...*/
0332         if (last) {
0333             if (likely (last->urb != urb)) {
0334                 ehci_urb_done(ehci, last->urb, last_status);
0335                 last_status = -EINPROGRESS;
0336             }
0337             ehci_qtd_free (ehci, last);
0338             last = NULL;
0339         }
0340 
0341         /* ignore urbs submitted during completions we reported */
0342         if (qtd == end)
0343             break;
0344 
0345         /* hardware copies qtd out of qh overlay */
0346         rmb ();
0347         token = hc32_to_cpu(ehci, qtd->hw_token);
0348 
0349         /* always clean up qtds the hc de-activated */
0350  retry_xacterr:
0351         if ((token & QTD_STS_ACTIVE) == 0) {
0352 
0353             /* Report Data Buffer Error: non-fatal but useful */
0354             if (token & QTD_STS_DBE)
0355                 ehci_dbg(ehci,
0356                     "detected DataBufferErr for urb %p ep%d%s len %d, qtd %p [qh %p]\n",
0357                     urb,
0358                     usb_endpoint_num(&urb->ep->desc),
0359                     usb_endpoint_dir_in(&urb->ep->desc) ? "in" : "out",
0360                     urb->transfer_buffer_length,
0361                     qtd,
0362                     qh);
0363 
0364             /* on STALL, error, and short reads this urb must
0365              * complete and all its qtds must be recycled.
0366              */
0367             if ((token & QTD_STS_HALT) != 0) {
0368 
0369                 /* retry transaction errors until we
0370                  * reach the software xacterr limit
0371                  */
0372                 if ((token & QTD_STS_XACT) &&
0373                         QTD_CERR(token) == 0 &&
0374                         ++qh->xacterrs < QH_XACTERR_MAX &&
0375                         !urb->unlinked) {
0376                     ehci_dbg(ehci,
0377     "detected XactErr len %zu/%zu retry %d\n",
0378     qtd->length - QTD_LENGTH(token), qtd->length, qh->xacterrs);
0379 
0380                     /* reset the token in the qtd and the
0381                      * qh overlay (which still contains
0382                      * the qtd) so that we pick up from
0383                      * where we left off
0384                      */
0385                     token &= ~QTD_STS_HALT;
0386                     token |= QTD_STS_ACTIVE |
0387                             (EHCI_TUNE_CERR << 10);
0388                     qtd->hw_token = cpu_to_hc32(ehci,
0389                             token);
0390                     wmb();
0391                     hw->hw_token = cpu_to_hc32(ehci,
0392                             token);
0393                     goto retry_xacterr;
0394                 }
0395                 stopped = 1;
0396                 qh->unlink_reason |= QH_UNLINK_HALTED;
0397 
0398             /* magic dummy for some short reads; qh won't advance.
0399              * that silicon quirk can kick in with this dummy too.
0400              *
0401              * other short reads won't stop the queue, including
0402              * control transfers (status stage handles that) or
0403              * most other single-qtd reads ... the queue stops if
0404              * URB_SHORT_NOT_OK was set so the driver submitting
0405              * the urbs could clean it up.
0406              */
0407             } else if (IS_SHORT_READ (token)
0408                     && !(qtd->hw_alt_next
0409                         & EHCI_LIST_END(ehci))) {
0410                 stopped = 1;
0411                 qh->unlink_reason |= QH_UNLINK_SHORT_READ;
0412             }
0413 
0414         /* stop scanning when we reach qtds the hc is using */
0415         } else if (likely (!stopped
0416                 && ehci->rh_state >= EHCI_RH_RUNNING)) {
0417             break;
0418 
0419         /* scan the whole queue for unlinks whenever it stops */
0420         } else {
0421             stopped = 1;
0422 
0423             /* cancel everything if we halt, suspend, etc */
0424             if (ehci->rh_state < EHCI_RH_RUNNING) {
0425                 last_status = -ESHUTDOWN;
0426                 qh->unlink_reason |= QH_UNLINK_SHUTDOWN;
0427             }
0428 
0429             /* this qtd is active; skip it unless a previous qtd
0430              * for its urb faulted, or its urb was canceled.
0431              */
0432             else if (last_status == -EINPROGRESS && !urb->unlinked)
0433                 continue;
0434 
0435             /*
0436              * If this was the active qtd when the qh was unlinked
0437              * and the overlay's token is active, then the overlay
0438              * hasn't been written back to the qtd yet so use its
0439              * token instead of the qtd's.  After the qtd is
0440              * processed and removed, the overlay won't be valid
0441              * any more.
0442              */
0443             if (state == QH_STATE_IDLE &&
0444                     qh->qtd_list.next == &qtd->qtd_list &&
0445                     (hw->hw_token & ACTIVE_BIT(ehci))) {
0446                 token = hc32_to_cpu(ehci, hw->hw_token);
0447                 hw->hw_token &= ~ACTIVE_BIT(ehci);
0448                 qh->should_be_inactive = 1;
0449 
0450                 /* An unlink may leave an incomplete
0451                  * async transaction in the TT buffer.
0452                  * We have to clear it.
0453                  */
0454                 ehci_clear_tt_buffer(ehci, qh, urb, token);
0455             }
0456         }
0457 
0458         /* unless we already know the urb's status, collect qtd status
0459          * and update count of bytes transferred.  in common short read
0460          * cases with only one data qtd (including control transfers),
0461          * queue processing won't halt.  but with two or more qtds (for
0462          * example, with a 32 KB transfer), when the first qtd gets a
0463          * short read the second must be removed by hand.
0464          */
0465         if (last_status == -EINPROGRESS) {
0466             last_status = qtd_copy_status(ehci, urb,
0467                     qtd->length, token);
0468             if (last_status == -EREMOTEIO
0469                     && (qtd->hw_alt_next
0470                         & EHCI_LIST_END(ehci)))
0471                 last_status = -EINPROGRESS;
0472 
0473             /* As part of low/full-speed endpoint-halt processing
0474              * we must clear the TT buffer (11.17.5).
0475              */
0476             if (unlikely(last_status != -EINPROGRESS &&
0477                     last_status != -EREMOTEIO)) {
0478                 /* The TT's in some hubs malfunction when they
0479                  * receive this request following a STALL (they
0480                  * stop sending isochronous packets).  Since a
0481                  * STALL can't leave the TT buffer in a busy
0482                  * state (if you believe Figures 11-48 - 11-51
0483                  * in the USB 2.0 spec), we won't clear the TT
0484                  * buffer in this case.  Strictly speaking this
0485                  * is a violation of the spec.
0486                  */
0487                 if (last_status != -EPIPE)
0488                     ehci_clear_tt_buffer(ehci, qh, urb,
0489                             token);
0490             }
0491         }
0492 
0493         /* if we're removing something not at the queue head,
0494          * patch the hardware queue pointer.
0495          */
0496         if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
0497             last = list_entry (qtd->qtd_list.prev,
0498                     struct ehci_qtd, qtd_list);
0499             last->hw_next = qtd->hw_next;
0500         }
0501 
0502         /* remove qtd; it's recycled after possible urb completion */
0503         list_del (&qtd->qtd_list);
0504         last = qtd;
0505 
0506         /* reinit the xacterr counter for the next qtd */
0507         qh->xacterrs = 0;
0508     }
0509 
0510     /* last urb's completion might still need calling */
0511     if (likely (last != NULL)) {
0512         ehci_urb_done(ehci, last->urb, last_status);
0513         ehci_qtd_free (ehci, last);
0514     }
0515 
0516     /* Do we need to rescan for URBs dequeued during a giveback? */
0517     if (unlikely(qh->dequeue_during_giveback)) {
0518         /* If the QH is already unlinked, do the rescan now. */
0519         if (state == QH_STATE_IDLE)
0520             goto rescan;
0521 
0522         /* Otherwise the caller must unlink the QH. */
0523     }
0524 
0525     /* restore original state; caller must unlink or relink */
0526     qh->qh_state = state;
0527 
0528     /* be sure the hardware's done with the qh before refreshing
0529      * it after fault cleanup, or recovering from silicon wrongly
0530      * overlaying the dummy qtd (which reduces DMA chatter).
0531      *
0532      * We won't refresh a QH that's linked (after the HC
0533      * stopped the queue).  That avoids a race:
0534      *  - HC reads first part of QH;
0535      *  - CPU updates that first part and the token;
0536      *  - HC reads rest of that QH, including token
0537      * Result:  HC gets an inconsistent image, and then
0538      * DMAs to/from the wrong memory (corrupting it).
0539      *
0540      * That should be rare for interrupt transfers,
0541      * except maybe high bandwidth ...
0542      */
0543     if (stopped != 0 || hw->hw_qtd_next == EHCI_LIST_END(ehci))
0544         qh->unlink_reason |= QH_UNLINK_DUMMY_OVERLAY;
0545 
0546     /* Let the caller know if the QH needs to be unlinked. */
0547     return qh->unlink_reason;
0548 }
0549 
0550 /*-------------------------------------------------------------------------*/
0551 
0552 /*
0553  * reverse of qh_urb_transaction:  free a list of TDs.
0554  * used for cleanup after errors, before HC sees an URB's TDs.
0555  */
0556 static void qtd_list_free (
0557     struct ehci_hcd     *ehci,
0558     struct urb      *urb,
0559     struct list_head    *qtd_list
0560 ) {
0561     struct list_head    *entry, *temp;
0562 
0563     list_for_each_safe (entry, temp, qtd_list) {
0564         struct ehci_qtd *qtd;
0565 
0566         qtd = list_entry (entry, struct ehci_qtd, qtd_list);
0567         list_del (&qtd->qtd_list);
0568         ehci_qtd_free (ehci, qtd);
0569     }
0570 }
0571 
0572 /*
0573  * create a list of filled qtds for this URB; won't link into qh.
0574  */
0575 static struct list_head *
0576 qh_urb_transaction (
0577     struct ehci_hcd     *ehci,
0578     struct urb      *urb,
0579     struct list_head    *head,
0580     gfp_t           flags
0581 ) {
0582     struct ehci_qtd     *qtd, *qtd_prev;
0583     dma_addr_t      buf;
0584     int         len, this_sg_len, maxpacket;
0585     int         is_input;
0586     u32         token;
0587     int         i;
0588     struct scatterlist  *sg;
0589 
0590     /*
0591      * URBs map to sequences of QTDs:  one logical transaction
0592      */
0593     qtd = ehci_qtd_alloc (ehci, flags);
0594     if (unlikely (!qtd))
0595         return NULL;
0596     list_add_tail (&qtd->qtd_list, head);
0597     qtd->urb = urb;
0598 
0599     token = QTD_STS_ACTIVE;
0600     token |= (EHCI_TUNE_CERR << 10);
0601     /* for split transactions, SplitXState initialized to zero */
0602 
0603     len = urb->transfer_buffer_length;
0604     is_input = usb_pipein (urb->pipe);
0605     if (usb_pipecontrol (urb->pipe)) {
0606         /* SETUP pid */
0607         qtd_fill(ehci, qtd, urb->setup_dma,
0608                 sizeof (struct usb_ctrlrequest),
0609                 token | (2 /* "setup" */ << 8), 8);
0610 
0611         /* ... and always at least one more pid */
0612         token ^= QTD_TOGGLE;
0613         qtd_prev = qtd;
0614         qtd = ehci_qtd_alloc (ehci, flags);
0615         if (unlikely (!qtd))
0616             goto cleanup;
0617         qtd->urb = urb;
0618         qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma);
0619         list_add_tail (&qtd->qtd_list, head);
0620 
0621         /* for zero length DATA stages, STATUS is always IN */
0622         if (len == 0)
0623             token |= (1 /* "in" */ << 8);
0624     }
0625 
0626     /*
0627      * data transfer stage:  buffer setup
0628      */
0629     i = urb->num_mapped_sgs;
0630     if (len > 0 && i > 0) {
0631         sg = urb->sg;
0632         buf = sg_dma_address(sg);
0633 
0634         /* urb->transfer_buffer_length may be smaller than the
0635          * size of the scatterlist (or vice versa)
0636          */
0637         this_sg_len = min_t(int, sg_dma_len(sg), len);
0638     } else {
0639         sg = NULL;
0640         buf = urb->transfer_dma;
0641         this_sg_len = len;
0642     }
0643 
0644     if (is_input)
0645         token |= (1 /* "in" */ << 8);
0646     /* else it's already initted to "out" pid (0 << 8) */
0647 
0648     maxpacket = usb_maxpacket(urb->dev, urb->pipe);
0649 
0650     /*
0651      * buffer gets wrapped in one or more qtds;
0652      * last one may be "short" (including zero len)
0653      * and may serve as a control status ack
0654      */
0655     for (;;) {
0656         unsigned int this_qtd_len;
0657 
0658         this_qtd_len = qtd_fill(ehci, qtd, buf, this_sg_len, token,
0659                 maxpacket);
0660         this_sg_len -= this_qtd_len;
0661         len -= this_qtd_len;
0662         buf += this_qtd_len;
0663 
0664         /*
0665          * short reads advance to a "magic" dummy instead of the next
0666          * qtd ... that forces the queue to stop, for manual cleanup.
0667          * (this will usually be overridden later.)
0668          */
0669         if (is_input)
0670             qtd->hw_alt_next = ehci->async->hw->hw_alt_next;
0671 
0672         /* qh makes control packets use qtd toggle; maybe switch it */
0673         if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
0674             token ^= QTD_TOGGLE;
0675 
0676         if (likely(this_sg_len <= 0)) {
0677             if (--i <= 0 || len <= 0)
0678                 break;
0679             sg = sg_next(sg);
0680             buf = sg_dma_address(sg);
0681             this_sg_len = min_t(int, sg_dma_len(sg), len);
0682         }
0683 
0684         qtd_prev = qtd;
0685         qtd = ehci_qtd_alloc (ehci, flags);
0686         if (unlikely (!qtd))
0687             goto cleanup;
0688         qtd->urb = urb;
0689         qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma);
0690         list_add_tail (&qtd->qtd_list, head);
0691     }
0692 
0693     /*
0694      * unless the caller requires manual cleanup after short reads,
0695      * have the alt_next mechanism keep the queue running after the
0696      * last data qtd (the only one, for control and most other cases).
0697      */
0698     if (likely ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0
0699                 || usb_pipecontrol (urb->pipe)))
0700         qtd->hw_alt_next = EHCI_LIST_END(ehci);
0701 
0702     /*
0703      * control requests may need a terminating data "status" ack;
0704      * other OUT ones may need a terminating short packet
0705      * (zero length).
0706      */
0707     if (likely (urb->transfer_buffer_length != 0)) {
0708         int one_more = 0;
0709 
0710         if (usb_pipecontrol (urb->pipe)) {
0711             one_more = 1;
0712             token ^= 0x0100;    /* "in" <--> "out"  */
0713             token |= QTD_TOGGLE;    /* force DATA1 */
0714         } else if (usb_pipeout(urb->pipe)
0715                 && (urb->transfer_flags & URB_ZERO_PACKET)
0716                 && !(urb->transfer_buffer_length % maxpacket)) {
0717             one_more = 1;
0718         }
0719         if (one_more) {
0720             qtd_prev = qtd;
0721             qtd = ehci_qtd_alloc (ehci, flags);
0722             if (unlikely (!qtd))
0723                 goto cleanup;
0724             qtd->urb = urb;
0725             qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma);
0726             list_add_tail (&qtd->qtd_list, head);
0727 
0728             /* never any data in such packets */
0729             qtd_fill(ehci, qtd, 0, 0, token, 0);
0730         }
0731     }
0732 
0733     /* by default, enable interrupt on urb completion */
0734     if (likely (!(urb->transfer_flags & URB_NO_INTERRUPT)))
0735         qtd->hw_token |= cpu_to_hc32(ehci, QTD_IOC);
0736     return head;
0737 
0738 cleanup:
0739     qtd_list_free (ehci, urb, head);
0740     return NULL;
0741 }
0742 
0743 /*-------------------------------------------------------------------------*/
0744 
0745 // Would be best to create all qh's from config descriptors,
0746 // when each interface/altsetting is established.  Unlink
0747 // any previous qh and cancel its urbs first; endpoints are
0748 // implicitly reset then (data toggle too).
0749 // That'd mean updating how usbcore talks to HCDs. (2.7?)
0750 
0751 
0752 /*
0753  * Each QH holds a qtd list; a QH is used for everything except iso.
0754  *
0755  * For interrupt urbs, the scheduler must set the microframe scheduling
0756  * mask(s) each time the QH gets scheduled.  For highspeed, that's
0757  * just one microframe in the s-mask.  For split interrupt transactions
0758  * there are additional complications: c-mask, maybe FSTNs.
0759  */
0760 static struct ehci_qh *
0761 qh_make (
0762     struct ehci_hcd     *ehci,
0763     struct urb      *urb,
0764     gfp_t           flags
0765 ) {
0766     struct ehci_qh      *qh = ehci_qh_alloc (ehci, flags);
0767     struct usb_host_endpoint *ep;
0768     u32         info1 = 0, info2 = 0;
0769     int         is_input, type;
0770     int         maxp = 0;
0771     int         mult;
0772     struct usb_tt       *tt = urb->dev->tt;
0773     struct ehci_qh_hw   *hw;
0774 
0775     if (!qh)
0776         return qh;
0777 
0778     /*
0779      * init endpoint/device data for this QH
0780      */
0781     info1 |= usb_pipeendpoint (urb->pipe) << 8;
0782     info1 |= usb_pipedevice (urb->pipe) << 0;
0783 
0784     is_input = usb_pipein (urb->pipe);
0785     type = usb_pipetype (urb->pipe);
0786     ep = usb_pipe_endpoint (urb->dev, urb->pipe);
0787     maxp = usb_endpoint_maxp (&ep->desc);
0788     mult = usb_endpoint_maxp_mult (&ep->desc);
0789 
0790     /* 1024 byte maxpacket is a hardware ceiling.  High bandwidth
0791      * acts like up to 3KB, but is built from smaller packets.
0792      */
0793     if (maxp > 1024) {
0794         ehci_dbg(ehci, "bogus qh maxpacket %d\n", maxp);
0795         goto done;
0796     }
0797 
0798     /* Compute interrupt scheduling parameters just once, and save.
0799      * - allowing for high bandwidth, how many nsec/uframe are used?
0800      * - split transactions need a second CSPLIT uframe; same question
0801      * - splits also need a schedule gap (for full/low speed I/O)
0802      * - qh has a polling interval
0803      *
0804      * For control/bulk requests, the HC or TT handles these.
0805      */
0806     if (type == PIPE_INTERRUPT) {
0807         unsigned    tmp;
0808 
0809         qh->ps.usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH,
0810                 is_input, 0, mult * maxp));
0811         qh->ps.phase = NO_FRAME;
0812 
0813         if (urb->dev->speed == USB_SPEED_HIGH) {
0814             qh->ps.c_usecs = 0;
0815             qh->gap_uf = 0;
0816 
0817             if (urb->interval > 1 && urb->interval < 8) {
0818                 /* NOTE interval 2 or 4 uframes could work.
0819                  * But interval 1 scheduling is simpler, and
0820                  * includes high bandwidth.
0821                  */
0822                 urb->interval = 1;
0823             } else if (urb->interval > ehci->periodic_size << 3) {
0824                 urb->interval = ehci->periodic_size << 3;
0825             }
0826             qh->ps.period = urb->interval >> 3;
0827 
0828             /* period for bandwidth allocation */
0829             tmp = min_t(unsigned, EHCI_BANDWIDTH_SIZE,
0830                     1 << (urb->ep->desc.bInterval - 1));
0831 
0832             /* Allow urb->interval to override */
0833             qh->ps.bw_uperiod = min_t(unsigned, tmp, urb->interval);
0834             qh->ps.bw_period = qh->ps.bw_uperiod >> 3;
0835         } else {
0836             int     think_time;
0837 
0838             /* gap is f(FS/LS transfer times) */
0839             qh->gap_uf = 1 + usb_calc_bus_time (urb->dev->speed,
0840                     is_input, 0, maxp) / (125 * 1000);
0841 
0842             /* FIXME this just approximates SPLIT/CSPLIT times */
0843             if (is_input) {     // SPLIT, gap, CSPLIT+DATA
0844                 qh->ps.c_usecs = qh->ps.usecs + HS_USECS(0);
0845                 qh->ps.usecs = HS_USECS(1);
0846             } else {        // SPLIT+DATA, gap, CSPLIT
0847                 qh->ps.usecs += HS_USECS(1);
0848                 qh->ps.c_usecs = HS_USECS(0);
0849             }
0850 
0851             think_time = tt ? tt->think_time : 0;
0852             qh->ps.tt_usecs = NS_TO_US(think_time +
0853                     usb_calc_bus_time (urb->dev->speed,
0854                     is_input, 0, maxp));
0855             if (urb->interval > ehci->periodic_size)
0856                 urb->interval = ehci->periodic_size;
0857             qh->ps.period = urb->interval;
0858 
0859             /* period for bandwidth allocation */
0860             tmp = min_t(unsigned, EHCI_BANDWIDTH_FRAMES,
0861                     urb->ep->desc.bInterval);
0862             tmp = rounddown_pow_of_two(tmp);
0863 
0864             /* Allow urb->interval to override */
0865             qh->ps.bw_period = min_t(unsigned, tmp, urb->interval);
0866             qh->ps.bw_uperiod = qh->ps.bw_period << 3;
0867         }
0868     }
0869 
0870     /* support for tt scheduling, and access to toggles */
0871     qh->ps.udev = urb->dev;
0872     qh->ps.ep = urb->ep;
0873 
0874     /* using TT? */
0875     switch (urb->dev->speed) {
0876     case USB_SPEED_LOW:
0877         info1 |= QH_LOW_SPEED;
0878         fallthrough;
0879 
0880     case USB_SPEED_FULL:
0881         /* EPS 0 means "full" */
0882         if (type != PIPE_INTERRUPT)
0883             info1 |= (EHCI_TUNE_RL_TT << 28);
0884         if (type == PIPE_CONTROL) {
0885             info1 |= QH_CONTROL_EP;     /* for TT */
0886             info1 |= QH_TOGGLE_CTL;     /* toggle from qtd */
0887         }
0888         info1 |= maxp << 16;
0889 
0890         info2 |= (EHCI_TUNE_MULT_TT << 30);
0891 
0892         /* Some Freescale processors have an erratum in which the
0893          * port number in the queue head was 0..N-1 instead of 1..N.
0894          */
0895         if (ehci_has_fsl_portno_bug(ehci))
0896             info2 |= (urb->dev->ttport-1) << 23;
0897         else
0898             info2 |= urb->dev->ttport << 23;
0899 
0900         /* set the address of the TT; for TDI's integrated
0901          * root hub tt, leave it zeroed.
0902          */
0903         if (tt && tt->hub != ehci_to_hcd(ehci)->self.root_hub)
0904             info2 |= tt->hub->devnum << 16;
0905 
0906         /* NOTE:  if (PIPE_INTERRUPT) { scheduler sets c-mask } */
0907 
0908         break;
0909 
0910     case USB_SPEED_HIGH:        /* no TT involved */
0911         info1 |= QH_HIGH_SPEED;
0912         if (type == PIPE_CONTROL) {
0913             info1 |= (EHCI_TUNE_RL_HS << 28);
0914             info1 |= 64 << 16;  /* usb2 fixed maxpacket */
0915             info1 |= QH_TOGGLE_CTL; /* toggle from qtd */
0916             info2 |= (EHCI_TUNE_MULT_HS << 30);
0917         } else if (type == PIPE_BULK) {
0918             info1 |= (EHCI_TUNE_RL_HS << 28);
0919             /* The USB spec says that high speed bulk endpoints
0920              * always use 512 byte maxpacket.  But some device
0921              * vendors decided to ignore that, and MSFT is happy
0922              * to help them do so.  So now people expect to use
0923              * such nonconformant devices with Linux too; sigh.
0924              */
0925             info1 |= maxp << 16;
0926             info2 |= (EHCI_TUNE_MULT_HS << 30);
0927         } else {        /* PIPE_INTERRUPT */
0928             info1 |= maxp << 16;
0929             info2 |= mult << 30;
0930         }
0931         break;
0932     default:
0933         ehci_dbg(ehci, "bogus dev %p speed %d\n", urb->dev,
0934             urb->dev->speed);
0935 done:
0936         qh_destroy(ehci, qh);
0937         return NULL;
0938     }
0939 
0940     /* NOTE:  if (PIPE_INTERRUPT) { scheduler sets s-mask } */
0941 
0942     /* init as live, toggle clear */
0943     qh->qh_state = QH_STATE_IDLE;
0944     hw = qh->hw;
0945     hw->hw_info1 = cpu_to_hc32(ehci, info1);
0946     hw->hw_info2 = cpu_to_hc32(ehci, info2);
0947     qh->is_out = !is_input;
0948     usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), !is_input, 1);
0949     return qh;
0950 }
0951 
0952 /*-------------------------------------------------------------------------*/
0953 
0954 static void enable_async(struct ehci_hcd *ehci)
0955 {
0956     if (ehci->async_count++)
0957         return;
0958 
0959     /* Stop waiting to turn off the async schedule */
0960     ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_DISABLE_ASYNC);
0961 
0962     /* Don't start the schedule until ASS is 0 */
0963     ehci_poll_ASS(ehci);
0964     turn_on_io_watchdog(ehci);
0965 }
0966 
0967 static void disable_async(struct ehci_hcd *ehci)
0968 {
0969     if (--ehci->async_count)
0970         return;
0971 
0972     /* The async schedule and unlink lists are supposed to be empty */
0973     WARN_ON(ehci->async->qh_next.qh || !list_empty(&ehci->async_unlink) ||
0974             !list_empty(&ehci->async_idle));
0975 
0976     /* Don't turn off the schedule until ASS is 1 */
0977     ehci_poll_ASS(ehci);
0978 }
0979 
0980 /* move qh (and its qtds) onto async queue; maybe enable queue.  */
0981 
0982 static void qh_link_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
0983 {
0984     __hc32      dma = QH_NEXT(ehci, qh->qh_dma);
0985     struct ehci_qh  *head;
0986 
0987     /* Don't link a QH if there's a Clear-TT-Buffer pending */
0988     if (unlikely(qh->clearing_tt))
0989         return;
0990 
0991     WARN_ON(qh->qh_state != QH_STATE_IDLE);
0992 
0993     /* clear halt and/or toggle; and maybe recover from silicon quirk */
0994     qh_refresh(ehci, qh);
0995 
0996     /* splice right after start */
0997     head = ehci->async;
0998     qh->qh_next = head->qh_next;
0999     qh->hw->hw_next = head->hw->hw_next;
1000     wmb ();
1001 
1002     head->qh_next.qh = qh;
1003     head->hw->hw_next = dma;
1004 
1005     qh->qh_state = QH_STATE_LINKED;
1006     qh->xacterrs = 0;
1007     qh->unlink_reason = 0;
1008     /* qtd completions reported later by interrupt */
1009 
1010     enable_async(ehci);
1011 }
1012 
1013 /*-------------------------------------------------------------------------*/
1014 
1015 /*
1016  * For control/bulk/interrupt, return QH with these TDs appended.
1017  * Allocates and initializes the QH if necessary.
1018  * Returns null if it can't allocate a QH it needs to.
1019  * If the QH has TDs (urbs) already, that's great.
1020  */
1021 static struct ehci_qh *qh_append_tds (
1022     struct ehci_hcd     *ehci,
1023     struct urb      *urb,
1024     struct list_head    *qtd_list,
1025     int         epnum,
1026     void            **ptr
1027 )
1028 {
1029     struct ehci_qh      *qh = NULL;
1030     __hc32          qh_addr_mask = cpu_to_hc32(ehci, 0x7f);
1031 
1032     qh = (struct ehci_qh *) *ptr;
1033     if (unlikely (qh == NULL)) {
1034         /* can't sleep here, we have ehci->lock... */
1035         qh = qh_make (ehci, urb, GFP_ATOMIC);
1036         *ptr = qh;
1037     }
1038     if (likely (qh != NULL)) {
1039         struct ehci_qtd *qtd;
1040 
1041         if (unlikely (list_empty (qtd_list)))
1042             qtd = NULL;
1043         else
1044             qtd = list_entry (qtd_list->next, struct ehci_qtd,
1045                     qtd_list);
1046 
1047         /* control qh may need patching ... */
1048         if (unlikely (epnum == 0)) {
1049 
1050                         /* usb_reset_device() briefly reverts to address 0 */
1051                         if (usb_pipedevice (urb->pipe) == 0)
1052                 qh->hw->hw_info1 &= ~qh_addr_mask;
1053         }
1054 
1055         /* just one way to queue requests: swap with the dummy qtd.
1056          * only hc or qh_refresh() ever modify the overlay.
1057          */
1058         if (likely (qtd != NULL)) {
1059             struct ehci_qtd     *dummy;
1060             dma_addr_t      dma;
1061             __hc32          token;
1062 
1063             /* to avoid racing the HC, use the dummy td instead of
1064              * the first td of our list (becomes new dummy).  both
1065              * tds stay deactivated until we're done, when the
1066              * HC is allowed to fetch the old dummy (4.10.2).
1067              */
1068             token = qtd->hw_token;
1069             qtd->hw_token = HALT_BIT(ehci);
1070 
1071             dummy = qh->dummy;
1072 
1073             dma = dummy->qtd_dma;
1074             *dummy = *qtd;
1075             dummy->qtd_dma = dma;
1076 
1077             list_del (&qtd->qtd_list);
1078             list_add (&dummy->qtd_list, qtd_list);
1079             list_splice_tail(qtd_list, &qh->qtd_list);
1080 
1081             ehci_qtd_init(ehci, qtd, qtd->qtd_dma);
1082             qh->dummy = qtd;
1083 
1084             /* hc must see the new dummy at list end */
1085             dma = qtd->qtd_dma;
1086             qtd = list_entry (qh->qtd_list.prev,
1087                     struct ehci_qtd, qtd_list);
1088             qtd->hw_next = QTD_NEXT(ehci, dma);
1089 
1090             /* let the hc process these next qtds */
1091             wmb ();
1092             dummy->hw_token = token;
1093 
1094             urb->hcpriv = qh;
1095         }
1096     }
1097     return qh;
1098 }
1099 
1100 /*-------------------------------------------------------------------------*/
1101 
1102 static int
1103 submit_async (
1104     struct ehci_hcd     *ehci,
1105     struct urb      *urb,
1106     struct list_head    *qtd_list,
1107     gfp_t           mem_flags
1108 ) {
1109     int         epnum;
1110     unsigned long       flags;
1111     struct ehci_qh      *qh = NULL;
1112     int         rc;
1113 
1114     epnum = urb->ep->desc.bEndpointAddress;
1115 
1116 #ifdef EHCI_URB_TRACE
1117     {
1118         struct ehci_qtd *qtd;
1119         qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list);
1120         ehci_dbg(ehci,
1121              "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
1122              __func__, urb->dev->devpath, urb,
1123              epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
1124              urb->transfer_buffer_length,
1125              qtd, urb->ep->hcpriv);
1126     }
1127 #endif
1128 
1129     spin_lock_irqsave (&ehci->lock, flags);
1130     if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
1131         rc = -ESHUTDOWN;
1132         goto done;
1133     }
1134     rc = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1135     if (unlikely(rc))
1136         goto done;
1137 
1138     qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
1139     if (unlikely(qh == NULL)) {
1140         usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1141         rc = -ENOMEM;
1142         goto done;
1143     }
1144 
1145     /* Control/bulk operations through TTs don't need scheduling,
1146      * the HC and TT handle it when the TT has a buffer ready.
1147      */
1148     if (likely (qh->qh_state == QH_STATE_IDLE))
1149         qh_link_async(ehci, qh);
1150  done:
1151     spin_unlock_irqrestore (&ehci->lock, flags);
1152     if (unlikely (qh == NULL))
1153         qtd_list_free (ehci, urb, qtd_list);
1154     return rc;
1155 }
1156 
1157 /*-------------------------------------------------------------------------*/
1158 #ifdef CONFIG_USB_HCD_TEST_MODE
1159 /*
1160  * This function creates the qtds and submits them for the
1161  * SINGLE_STEP_SET_FEATURE Test.
1162  * This is done in two parts: first SETUP req for GetDesc is sent then
1163  * 15 seconds later, the IN stage for GetDesc starts to req data from dev
1164  *
1165  * is_setup : i/p argument decides which of the two stage needs to be
1166  * performed; TRUE - SETUP and FALSE - IN+STATUS
1167  * Returns 0 if success
1168  */
1169 static int ehci_submit_single_step_set_feature(
1170     struct usb_hcd  *hcd,
1171     struct urb      *urb,
1172     int             is_setup
1173 ) {
1174     struct ehci_hcd     *ehci = hcd_to_ehci(hcd);
1175     struct list_head    qtd_list;
1176     struct list_head    *head;
1177 
1178     struct ehci_qtd     *qtd, *qtd_prev;
1179     dma_addr_t      buf;
1180     int         len, maxpacket;
1181     u32         token;
1182 
1183     INIT_LIST_HEAD(&qtd_list);
1184     head = &qtd_list;
1185 
1186     /* URBs map to sequences of QTDs:  one logical transaction */
1187     qtd = ehci_qtd_alloc(ehci, GFP_KERNEL);
1188     if (unlikely(!qtd))
1189         return -1;
1190     list_add_tail(&qtd->qtd_list, head);
1191     qtd->urb = urb;
1192 
1193     token = QTD_STS_ACTIVE;
1194     token |= (EHCI_TUNE_CERR << 10);
1195 
1196     len = urb->transfer_buffer_length;
1197     /*
1198      * Check if the request is to perform just the SETUP stage (getDesc)
1199      * as in SINGLE_STEP_SET_FEATURE test, DATA stage (IN) happens
1200      * 15 secs after the setup
1201      */
1202     if (is_setup) {
1203         /* SETUP pid, and interrupt after SETUP completion */
1204         qtd_fill(ehci, qtd, urb->setup_dma,
1205                 sizeof(struct usb_ctrlrequest),
1206                 QTD_IOC | token | (2 /* "setup" */ << 8), 8);
1207 
1208         submit_async(ehci, urb, &qtd_list, GFP_ATOMIC);
1209         return 0; /*Return now; we shall come back after 15 seconds*/
1210     }
1211 
1212     /*
1213      * IN: data transfer stage:  buffer setup : start the IN txn phase for
1214      * the get_Desc SETUP which was sent 15seconds back
1215      */
1216     token ^= QTD_TOGGLE;   /*We need to start IN with DATA-1 Pid-sequence*/
1217     buf = urb->transfer_dma;
1218 
1219     token |= (1 /* "in" */ << 8);  /*This is IN stage*/
1220 
1221     maxpacket = usb_maxpacket(urb->dev, urb->pipe);
1222 
1223     qtd_fill(ehci, qtd, buf, len, token, maxpacket);
1224 
1225     /*
1226      * Our IN phase shall always be a short read; so keep the queue running
1227      * and let it advance to the next qtd which zero length OUT status
1228      */
1229     qtd->hw_alt_next = EHCI_LIST_END(ehci);
1230 
1231     /* STATUS stage for GetDesc control request */
1232     token ^= 0x0100;        /* "in" <--> "out"  */
1233     token |= QTD_TOGGLE;    /* force DATA1 */
1234 
1235     qtd_prev = qtd;
1236     qtd = ehci_qtd_alloc(ehci, GFP_ATOMIC);
1237     if (unlikely(!qtd))
1238         goto cleanup;
1239     qtd->urb = urb;
1240     qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma);
1241     list_add_tail(&qtd->qtd_list, head);
1242 
1243     /* Interrupt after STATUS completion */
1244     qtd_fill(ehci, qtd, 0, 0, token | QTD_IOC, 0);
1245 
1246     submit_async(ehci, urb, &qtd_list, GFP_KERNEL);
1247 
1248     return 0;
1249 
1250 cleanup:
1251     qtd_list_free(ehci, urb, head);
1252     return -1;
1253 }
1254 #endif /* CONFIG_USB_HCD_TEST_MODE */
1255 
1256 /*-------------------------------------------------------------------------*/
1257 
1258 static void single_unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh)
1259 {
1260     struct ehci_qh      *prev;
1261 
1262     /* Add to the end of the list of QHs waiting for the next IAAD */
1263     qh->qh_state = QH_STATE_UNLINK_WAIT;
1264     list_add_tail(&qh->unlink_node, &ehci->async_unlink);
1265 
1266     /* Unlink it from the schedule */
1267     prev = ehci->async;
1268     while (prev->qh_next.qh != qh)
1269         prev = prev->qh_next.qh;
1270 
1271     prev->hw->hw_next = qh->hw->hw_next;
1272     prev->qh_next = qh->qh_next;
1273     if (ehci->qh_scan_next == qh)
1274         ehci->qh_scan_next = qh->qh_next.qh;
1275 }
1276 
1277 static void start_iaa_cycle(struct ehci_hcd *ehci)
1278 {
1279     /* If the controller isn't running, we don't have to wait for it */
1280     if (unlikely(ehci->rh_state < EHCI_RH_RUNNING)) {
1281         end_unlink_async(ehci);
1282 
1283     /* Otherwise start a new IAA cycle if one isn't already running */
1284     } else if (ehci->rh_state == EHCI_RH_RUNNING &&
1285             !ehci->iaa_in_progress) {
1286 
1287         /* Make sure the unlinks are all visible to the hardware */
1288         wmb();
1289 
1290         ehci_writel(ehci, ehci->command | CMD_IAAD,
1291                 &ehci->regs->command);
1292         ehci_readl(ehci, &ehci->regs->command);
1293         ehci->iaa_in_progress = true;
1294         ehci_enable_event(ehci, EHCI_HRTIMER_IAA_WATCHDOG, true);
1295     }
1296 }
1297 
1298 static void end_iaa_cycle(struct ehci_hcd *ehci)
1299 {
1300     if (ehci->has_synopsys_hc_bug)
1301         ehci_writel(ehci, (u32) ehci->async->qh_dma,
1302                 &ehci->regs->async_next);
1303 
1304     /* The current IAA cycle has ended */
1305     ehci->iaa_in_progress = false;
1306 
1307     end_unlink_async(ehci);
1308 }
1309 
1310 /* See if the async qh for the qtds being unlinked are now gone from the HC */
1311 
1312 static void end_unlink_async(struct ehci_hcd *ehci)
1313 {
1314     struct ehci_qh      *qh;
1315     bool            early_exit;
1316 
1317     if (list_empty(&ehci->async_unlink))
1318         return;
1319     qh = list_first_entry(&ehci->async_unlink, struct ehci_qh,
1320             unlink_node);   /* QH whose IAA cycle just ended */
1321 
1322     /*
1323      * If async_unlinking is set then this routine is already running,
1324      * either on the stack or on another CPU.
1325      */
1326     early_exit = ehci->async_unlinking;
1327 
1328     /* If the controller isn't running, process all the waiting QHs */
1329     if (ehci->rh_state < EHCI_RH_RUNNING)
1330         list_splice_tail_init(&ehci->async_unlink, &ehci->async_idle);
1331 
1332     /*
1333      * Intel (?) bug: The HC can write back the overlay region even
1334      * after the IAA interrupt occurs.  In self-defense, always go
1335      * through two IAA cycles for each QH.
1336      */
1337     else if (qh->qh_state == QH_STATE_UNLINK) {
1338         /*
1339          * Second IAA cycle has finished.  Process only the first
1340          * waiting QH (NVIDIA (?) bug).
1341          */
1342         list_move_tail(&qh->unlink_node, &ehci->async_idle);
1343     }
1344 
1345     /*
1346      * AMD/ATI (?) bug: The HC can continue to use an active QH long
1347      * after the IAA interrupt occurs.  To prevent problems, QHs that
1348      * may still be active will wait until 2 ms have passed with no
1349      * change to the hw_current and hw_token fields (this delay occurs
1350      * between the two IAA cycles).
1351      *
1352      * The EHCI spec (4.8.2) says that active QHs must not be removed
1353      * from the async schedule and recommends waiting until the QH
1354      * goes inactive.  This is ridiculous because the QH will _never_
1355      * become inactive if the endpoint NAKs indefinitely.
1356      */
1357 
1358     /* Some reasons for unlinking guarantee the QH can't be active */
1359     else if (qh->unlink_reason & (QH_UNLINK_HALTED |
1360             QH_UNLINK_SHORT_READ | QH_UNLINK_DUMMY_OVERLAY))
1361         goto DelayDone;
1362 
1363     /* The QH can't be active if the queue was and still is empty... */
1364     else if ((qh->unlink_reason & QH_UNLINK_QUEUE_EMPTY) &&
1365             list_empty(&qh->qtd_list))
1366         goto DelayDone;
1367 
1368     /* ... or if the QH has halted */
1369     else if (qh->hw->hw_token & cpu_to_hc32(ehci, QTD_STS_HALT))
1370         goto DelayDone;
1371 
1372     /* Otherwise we have to wait until the QH stops changing */
1373     else {
1374         __hc32      qh_current, qh_token;
1375 
1376         qh_current = qh->hw->hw_current;
1377         qh_token = qh->hw->hw_token;
1378         if (qh_current != ehci->old_current ||
1379                 qh_token != ehci->old_token) {
1380             ehci->old_current = qh_current;
1381             ehci->old_token = qh_token;
1382             ehci_enable_event(ehci,
1383                     EHCI_HRTIMER_ACTIVE_UNLINK, true);
1384             return;
1385         }
1386  DelayDone:
1387         qh->qh_state = QH_STATE_UNLINK;
1388         early_exit = true;
1389     }
1390     ehci->old_current = ~0;     /* Prepare for next QH */
1391 
1392     /* Start a new IAA cycle if any QHs are waiting for it */
1393     if (!list_empty(&ehci->async_unlink))
1394         start_iaa_cycle(ehci);
1395 
1396     /*
1397      * Don't allow nesting or concurrent calls,
1398      * or wait for the second IAA cycle for the next QH.
1399      */
1400     if (early_exit)
1401         return;
1402 
1403     /* Process the idle QHs */
1404     ehci->async_unlinking = true;
1405     while (!list_empty(&ehci->async_idle)) {
1406         qh = list_first_entry(&ehci->async_idle, struct ehci_qh,
1407                 unlink_node);
1408         list_del(&qh->unlink_node);
1409 
1410         qh->qh_state = QH_STATE_IDLE;
1411         qh->qh_next.qh = NULL;
1412 
1413         if (!list_empty(&qh->qtd_list))
1414             qh_completions(ehci, qh);
1415         if (!list_empty(&qh->qtd_list) &&
1416                 ehci->rh_state == EHCI_RH_RUNNING)
1417             qh_link_async(ehci, qh);
1418         disable_async(ehci);
1419     }
1420     ehci->async_unlinking = false;
1421 }
1422 
1423 static void start_unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh);
1424 
1425 static void unlink_empty_async(struct ehci_hcd *ehci)
1426 {
1427     struct ehci_qh      *qh;
1428     struct ehci_qh      *qh_to_unlink = NULL;
1429     int         count = 0;
1430 
1431     /* Find the last async QH which has been empty for a timer cycle */
1432     for (qh = ehci->async->qh_next.qh; qh; qh = qh->qh_next.qh) {
1433         if (list_empty(&qh->qtd_list) &&
1434                 qh->qh_state == QH_STATE_LINKED) {
1435             ++count;
1436             if (qh->unlink_cycle != ehci->async_unlink_cycle)
1437                 qh_to_unlink = qh;
1438         }
1439     }
1440 
1441     /* If nothing else is being unlinked, unlink the last empty QH */
1442     if (list_empty(&ehci->async_unlink) && qh_to_unlink) {
1443         qh_to_unlink->unlink_reason |= QH_UNLINK_QUEUE_EMPTY;
1444         start_unlink_async(ehci, qh_to_unlink);
1445         --count;
1446     }
1447 
1448     /* Other QHs will be handled later */
1449     if (count > 0) {
1450         ehci_enable_event(ehci, EHCI_HRTIMER_ASYNC_UNLINKS, true);
1451         ++ehci->async_unlink_cycle;
1452     }
1453 }
1454 
1455 #ifdef  CONFIG_PM
1456 
1457 /* The root hub is suspended; unlink all the async QHs */
1458 static void unlink_empty_async_suspended(struct ehci_hcd *ehci)
1459 {
1460     struct ehci_qh      *qh;
1461 
1462     while (ehci->async->qh_next.qh) {
1463         qh = ehci->async->qh_next.qh;
1464         WARN_ON(!list_empty(&qh->qtd_list));
1465         single_unlink_async(ehci, qh);
1466     }
1467 }
1468 
1469 #endif
1470 
1471 /* makes sure the async qh will become idle */
1472 /* caller must own ehci->lock */
1473 
1474 static void start_unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh)
1475 {
1476     /* If the QH isn't linked then there's nothing we can do. */
1477     if (qh->qh_state != QH_STATE_LINKED)
1478         return;
1479 
1480     single_unlink_async(ehci, qh);
1481     start_iaa_cycle(ehci);
1482 }
1483 
1484 /*-------------------------------------------------------------------------*/
1485 
1486 static void scan_async (struct ehci_hcd *ehci)
1487 {
1488     struct ehci_qh      *qh;
1489     bool            check_unlinks_later = false;
1490 
1491     ehci->qh_scan_next = ehci->async->qh_next.qh;
1492     while (ehci->qh_scan_next) {
1493         qh = ehci->qh_scan_next;
1494         ehci->qh_scan_next = qh->qh_next.qh;
1495 
1496         /* clean any finished work for this qh */
1497         if (!list_empty(&qh->qtd_list)) {
1498             int temp;
1499 
1500             /*
1501              * Unlinks could happen here; completion reporting
1502              * drops the lock.  That's why ehci->qh_scan_next
1503              * always holds the next qh to scan; if the next qh
1504              * gets unlinked then ehci->qh_scan_next is adjusted
1505              * in single_unlink_async().
1506              */
1507             temp = qh_completions(ehci, qh);
1508             if (unlikely(temp)) {
1509                 start_unlink_async(ehci, qh);
1510             } else if (list_empty(&qh->qtd_list)
1511                     && qh->qh_state == QH_STATE_LINKED) {
1512                 qh->unlink_cycle = ehci->async_unlink_cycle;
1513                 check_unlinks_later = true;
1514             }
1515         }
1516     }
1517 
1518     /*
1519      * Unlink empty entries, reducing DMA usage as well
1520      * as HCD schedule-scanning costs.  Delay for any qh
1521      * we just scanned, there's a not-unusual case that it
1522      * doesn't stay idle for long.
1523      */
1524     if (check_unlinks_later && ehci->rh_state == EHCI_RH_RUNNING &&
1525             !(ehci->enabled_hrtimer_events &
1526                 BIT(EHCI_HRTIMER_ASYNC_UNLINKS))) {
1527         ehci_enable_event(ehci, EHCI_HRTIMER_ASYNC_UNLINKS, true);
1528         ++ehci->async_unlink_cycle;
1529     }
1530 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!