usb/host/ehci-pci.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
0004  *
0005  * Copyright (c) 2000-2004 by David Brownell
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/pci.h>
0011 #include <linux/usb.h>
0012 #include <linux/usb/hcd.h>
0013
0014 #include "ehci.h"
0015 #include "pci-quirks.h"
0016
0017 #define DRIVER_DESC "EHCI PCI platform driver"
0018
0019 static const char hcd_name[] = "ehci-pci";
0020
0021 /* defined here to avoid adding to pci_ids.h for single instance use */
0022 #define PCI_DEVICE_ID_INTEL_CE4100_USB  0x2e70
0023
0024 #define PCI_VENDOR_ID_ASPEED        0x1a03
0025 #define PCI_DEVICE_ID_ASPEED_EHCI   0x2603
0026
0027 /*-------------------------------------------------------------------------*/
0028 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC     0x0939
0029 static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
0030 {
0031     return pdev->vendor == PCI_VENDOR_ID_INTEL &&
0032         pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
0033 }
0034
0035 /*
0036  * This is the list of PCI IDs for the devices that have EHCI USB class and
0037  * specific drivers for that. One of the example is a ChipIdea device installed
0038  * on some Intel MID platforms.
0039  */
0040 static const struct pci_device_id bypass_pci_id_table[] = {
0041     /* ChipIdea on Intel MID platform */
0042     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
0043     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
0044     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
0045     {}
0046 };
0047
0048 static inline bool is_bypassed_id(struct pci_dev *pdev)
0049 {
0050     return !!pci_match_id(bypass_pci_id_table, pdev);
0051 }
0052
0053 /*
0054  * 0x84 is the offset of in/out threshold register,
0055  * and it is the same offset as the register of 'hostpc'.
0056  */
0057 #define intel_quark_x1000_insnreg01 hostpc
0058
0059 /* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
0060 #define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD    0x007f007f
0061
0062 /* called after powerup, by probe or system-pm "wakeup" */
0063 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
0064 {
0065     int         retval;
0066
0067     /* we expect static quirk code to handle the "extended capabilities"
0068      * (currently just BIOS handoff) allowed starting with EHCI 0.96
0069      */
0070
0071     /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
0072     retval = pci_set_mwi(pdev);
0073     if (!retval)
0074         ehci_dbg(ehci, "MWI active\n");
0075
0076     /* Reset the threshold limit */
0077     if (is_intel_quark_x1000(pdev)) {
0078         /*
0079          * For the Intel QUARK X1000, raise the I/O threshold to the
0080          * maximum usable value in order to improve performance.
0081          */
0082         ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
0083             ehci->regs->intel_quark_x1000_insnreg01);
0084     }
0085
0086     return 0;
0087 }
0088
0089 /* called during probe() after chip reset completes */
0090 static int ehci_pci_setup(struct usb_hcd *hcd)
0091 {
0092     struct ehci_hcd     *ehci = hcd_to_ehci(hcd);
0093     struct pci_dev      *pdev = to_pci_dev(hcd->self.controller);
0094     u32         temp;
0095     int         retval;
0096
0097     ehci->caps = hcd->regs;
0098
0099     /*
0100      * ehci_init() causes memory for DMA transfers to be
0101      * allocated.  Thus, any vendor-specific workarounds based on
0102      * limiting the type of memory used for DMA transfers must
0103      * happen before ehci_setup() is called.
0104      *
0105      * Most other workarounds can be done either before or after
0106      * init and reset; they are located here too.
0107      */
0108     switch (pdev->vendor) {
0109     case PCI_VENDOR_ID_TOSHIBA_2:
0110         /* celleb's companion chip */
0111         if (pdev->device == 0x01b5) {
0112 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
0113             ehci->big_endian_mmio = 1;
0114 #else
0115             ehci_warn(ehci,
0116                   "unsupported big endian Toshiba quirk\n");
0117 #endif
0118         }
0119         break;
0120     case PCI_VENDOR_ID_NVIDIA:
0121         /* NVidia reports that certain chips don't handle
0122          * QH, ITD, or SITD addresses above 2GB.  (But TD,
0123          * data buffer, and periodic schedule are normal.)
0124          */
0125         switch (pdev->device) {
0126         case 0x003c:    /* MCP04 */
0127         case 0x005b:    /* CK804 */
0128         case 0x00d8:    /* CK8 */
0129         case 0x00e8:    /* CK8S */
0130             if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(31)) < 0)
0131                 ehci_warn(ehci, "can't enable NVidia "
0132                     "workaround for >2GB RAM\n");
0133             break;
0134
0135         /* Some NForce2 chips have problems with selective suspend;
0136          * fixed in newer silicon.
0137          */
0138         case 0x0068:
0139             if (pdev->revision < 0xa4)
0140                 ehci->no_selective_suspend = 1;
0141             break;
0142         }
0143         break;
0144     case PCI_VENDOR_ID_INTEL:
0145         if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
0146             hcd->has_tt = 1;
0147         break;
0148     case PCI_VENDOR_ID_TDI:
0149         if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
0150             hcd->has_tt = 1;
0151         break;
0152     case PCI_VENDOR_ID_AMD:
0153         /* AMD PLL quirk */
0154         if (usb_amd_quirk_pll_check())
0155             ehci->amd_pll_fix = 1;
0156         /* AMD8111 EHCI doesn't work, according to AMD errata */
0157         if (pdev->device == 0x7463) {
0158             ehci_info(ehci, "ignoring AMD8111 (errata)\n");
0159             retval = -EIO;
0160             goto done;
0161         }
0162
0163         /*
0164          * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
0165          * read/write memory space which does not belong to it when
0166          * there is NULL pointer with T-bit set to 1 in the frame list
0167          * table. To avoid the issue, the frame list link pointer
0168          * should always contain a valid pointer to a inactive qh.
0169          */
0170         if (pdev->device == 0x7808) {
0171             ehci->use_dummy_qh = 1;
0172             ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
0173         }
0174         break;
0175     case PCI_VENDOR_ID_VIA:
0176         if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
0177             u8 tmp;
0178
0179             /* The VT6212 defaults to a 1 usec EHCI sleep time which
0180              * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
0181              * that sleep time use the conventional 10 usec.
0182              */
0183             pci_read_config_byte(pdev, 0x4b, &tmp);
0184             if (tmp & 0x20)
0185                 break;
0186             pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
0187         }
0188         break;
0189     case PCI_VENDOR_ID_ATI:
0190         /* AMD PLL quirk */
0191         if (usb_amd_quirk_pll_check())
0192             ehci->amd_pll_fix = 1;
0193
0194         /*
0195          * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
0196          * read/write memory space which does not belong to it when
0197          * there is NULL pointer with T-bit set to 1 in the frame list
0198          * table. To avoid the issue, the frame list link pointer
0199          * should always contain a valid pointer to a inactive qh.
0200          */
0201         if (pdev->device == 0x4396) {
0202             ehci->use_dummy_qh = 1;
0203             ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
0204         }
0205         /* SB600 and old version of SB700 have a bug in EHCI controller,
0206          * which causes usb devices lose response in some cases.
0207          */
0208         if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
0209                 usb_amd_hang_symptom_quirk()) {
0210             u8 tmp;
0211             ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
0212             pci_read_config_byte(pdev, 0x53, &tmp);
0213             pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
0214         }
0215         break;
0216     case PCI_VENDOR_ID_NETMOS:
0217         /* MosChip frame-index-register bug */
0218         ehci_info(ehci, "applying MosChip frame-index workaround\n");
0219         ehci->frame_index_bug = 1;
0220         break;
0221     case PCI_VENDOR_ID_HUAWEI:
0222         /* Synopsys HC bug */
0223         if (pdev->device == 0xa239) {
0224             ehci_info(ehci, "applying Synopsys HC workaround\n");
0225             ehci->has_synopsys_hc_bug = 1;
0226         }
0227         break;
0228     case PCI_VENDOR_ID_ASPEED:
0229         if (pdev->device == PCI_DEVICE_ID_ASPEED_EHCI) {
0230             ehci_info(ehci, "applying Aspeed HC workaround\n");
0231             ehci->is_aspeed = 1;
0232         }
0233         break;
0234     case PCI_VENDOR_ID_ZHAOXIN:
0235         if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x90)
0236             ehci->zx_wakeup_clear_needed = 1;
0237         break;
0238     }
0239
0240     /* optional debug port, normally in the first BAR */
0241     temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
0242     if (temp) {
0243         pci_read_config_dword(pdev, temp, &temp);
0244         temp >>= 16;
0245         if (((temp >> 13) & 7) == 1) {
0246             u32 hcs_params = ehci_readl(ehci,
0247                             &ehci->caps->hcs_params);
0248
0249             temp &= 0x1fff;
0250             ehci->debug = hcd->regs + temp;
0251             temp = ehci_readl(ehci, &ehci->debug->control);
0252             ehci_info(ehci, "debug port %d%s\n",
0253                   HCS_DEBUG_PORT(hcs_params),
0254                   (temp & DBGP_ENABLED) ? " IN USE" : "");
0255             if (!(temp & DBGP_ENABLED))
0256                 ehci->debug = NULL;
0257         }
0258     }
0259
0260     retval = ehci_setup(hcd);
0261     if (retval)
0262         return retval;
0263
0264     /* These workarounds need to be applied after ehci_setup() */
0265     switch (pdev->vendor) {
0266     case PCI_VENDOR_ID_NEC:
0267     case PCI_VENDOR_ID_INTEL:
0268     case PCI_VENDOR_ID_AMD:
0269         ehci->need_io_watchdog = 0;
0270         break;
0271     case PCI_VENDOR_ID_NVIDIA:
0272         switch (pdev->device) {
0273         /* MCP89 chips on the MacBookAir3,1 give EPROTO when
0274          * fetching device descriptors unless LPM is disabled.
0275          * There are also intermittent problems enumerating
0276          * devices with PPCD enabled.
0277          */
0278         case 0x0d9d:
0279             ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
0280             ehci->has_ppcd = 0;
0281             ehci->command &= ~CMD_PPCEE;
0282             break;
0283         }
0284         break;
0285     }
0286
0287     /* at least the Genesys GL880S needs fixup here */
0288     temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
0289     temp &= 0x0f;
0290     if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
0291         ehci_dbg(ehci, "bogus port configuration: "
0292             "cc=%d x pcc=%d < ports=%d\n",
0293             HCS_N_CC(ehci->hcs_params),
0294             HCS_N_PCC(ehci->hcs_params),
0295             HCS_N_PORTS(ehci->hcs_params));
0296
0297         switch (pdev->vendor) {
0298         case 0x17a0:        /* GENESYS */
0299             /* GL880S: should be PORTS=2 */
0300             temp |= (ehci->hcs_params & ~0xf);
0301             ehci->hcs_params = temp;
0302             break;
0303         case PCI_VENDOR_ID_NVIDIA:
0304             /* NF4: should be PCC=10 */
0305             break;
0306         }
0307     }
0308
0309     /* Serial Bus Release Number is at PCI 0x60 offset */
0310     if (pdev->vendor == PCI_VENDOR_ID_STMICRO
0311         && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
0312         ;   /* ConneXT has no sbrn register */
0313     else if (pdev->vendor == PCI_VENDOR_ID_HUAWEI
0314              && pdev->device == 0xa239)
0315         ;   /* HUAWEI Kunpeng920 USB EHCI has no sbrn register */
0316     else
0317         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
0318
0319     /* Keep this around for a while just in case some EHCI
0320      * implementation uses legacy PCI PM support.  This test
0321      * can be removed on 17 Dec 2009 if the dev_warn() hasn't
0322      * been triggered by then.
0323      */
0324     if (!device_can_wakeup(&pdev->dev)) {
0325         u16 port_wake;
0326
0327         pci_read_config_word(pdev, 0x62, &port_wake);
0328         if (port_wake & 0x0001) {
0329             dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
0330             device_set_wakeup_capable(&pdev->dev, 1);
0331         }
0332     }
0333
0334 #ifdef  CONFIG_PM
0335     if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
0336         ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
0337 #endif
0338
0339     retval = ehci_pci_reinit(ehci, pdev);
0340 done:
0341     return retval;
0342 }
0343
0344 /*-------------------------------------------------------------------------*/
0345
0346 #ifdef  CONFIG_PM
0347
0348 /* suspend/resume, section 4.3 */
0349
0350 /* These routines rely on the PCI bus glue
0351  * to handle powerdown and wakeup, and currently also on
0352  * transceivers that don't need any software attention to set up
0353  * the right sort of wakeup.
0354  * Also they depend on separate root hub suspend/resume.
0355  */
0356
0357 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
0358 {
0359     struct ehci_hcd     *ehci = hcd_to_ehci(hcd);
0360     struct pci_dev      *pdev = to_pci_dev(hcd->self.controller);
0361
0362     if (ehci_resume(hcd, hibernated) != 0)
0363         (void) ehci_pci_reinit(ehci, pdev);
0364     return 0;
0365 }
0366
0367 #else
0368
0369 #define ehci_suspend        NULL
0370 #define ehci_pci_resume     NULL
0371 #endif  /* CONFIG_PM */
0372
0373 static struct hc_driver __read_mostly ehci_pci_hc_driver;
0374
0375 static const struct ehci_driver_overrides pci_overrides __initconst = {
0376     .reset =        ehci_pci_setup,
0377 };
0378
0379 /*-------------------------------------------------------------------------*/
0380
0381 static int ehci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
0382 {
0383     if (is_bypassed_id(pdev))
0384         return -ENODEV;
0385     return usb_hcd_pci_probe(pdev, id, &ehci_pci_hc_driver);
0386 }
0387
0388 static void ehci_pci_remove(struct pci_dev *pdev)
0389 {
0390     pci_clear_mwi(pdev);
0391     usb_hcd_pci_remove(pdev);
0392 }
0393
0394 /* PCI driver selection metadata; PCI hotplugging uses this */
0395 static const struct pci_device_id pci_ids [] = { {
0396     /* handle any USB 2.0 EHCI controller */
0397     PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
0398     }, {
0399     PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
0400     },
0401     { /* end: all zeroes */ }
0402 };
0403 MODULE_DEVICE_TABLE(pci, pci_ids);
0404
0405 /* pci driver glue; this is a "new style" PCI driver module */
0406 static struct pci_driver ehci_pci_driver = {
0407     .name =     hcd_name,
0408     .id_table = pci_ids,
0409
0410     .probe =    ehci_pci_probe,
0411     .remove =   ehci_pci_remove,
0412     .shutdown =     usb_hcd_pci_shutdown,
0413
0414 #ifdef CONFIG_PM
0415     .driver =   {
0416         .pm =   &usb_hcd_pci_pm_ops
0417     },
0418 #endif
0419 };
0420
0421 static int __init ehci_pci_init(void)
0422 {
0423     if (usb_disabled())
0424         return -ENODEV;
0425
0426     pr_info("%s: " DRIVER_DESC "\n", hcd_name);
0427
0428     ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
0429
0430     /* Entries for the PCI suspend/resume callbacks are special */
0431     ehci_pci_hc_driver.pci_suspend = ehci_suspend;
0432     ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
0433
0434     return pci_register_driver(&ehci_pci_driver);
0435 }
0436 module_init(ehci_pci_init);
0437
0438 static void __exit ehci_pci_cleanup(void)
0439 {
0440     pci_unregister_driver(&ehci_pci_driver);
0441 }
0442 module_exit(ehci_pci_cleanup);
0443
0444 MODULE_DESCRIPTION(DRIVER_DESC);
0445 MODULE_AUTHOR("David Brownell");
0446 MODULE_AUTHOR("Alan Stern");
0447 MODULE_LICENSE("GPL");