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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Enhanced Host Controller Interface (EHCI) driver for USB.
0004  *
0005  * Maintainer: Alan Stern <stern@rowland.harvard.edu>
0006  *
0007  * Copyright (c) 2000-2004 by David Brownell
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/pci.h>
0012 #include <linux/dmapool.h>
0013 #include <linux/kernel.h>
0014 #include <linux/delay.h>
0015 #include <linux/ioport.h>
0016 #include <linux/sched.h>
0017 #include <linux/vmalloc.h>
0018 #include <linux/errno.h>
0019 #include <linux/init.h>
0020 #include <linux/hrtimer.h>
0021 #include <linux/list.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/usb.h>
0024 #include <linux/usb/hcd.h>
0025 #include <linux/usb/otg.h>
0026 #include <linux/moduleparam.h>
0027 #include <linux/dma-mapping.h>
0028 #include <linux/debugfs.h>
0029 #include <linux/platform_device.h>
0030 #include <linux/slab.h>
0031 
0032 #include <asm/byteorder.h>
0033 #include <asm/io.h>
0034 #include <asm/irq.h>
0035 #include <asm/unaligned.h>
0036 
0037 #if defined(CONFIG_PPC_PS3)
0038 #include <asm/firmware.h>
0039 #endif
0040 
0041 /*-------------------------------------------------------------------------*/
0042 
0043 /*
0044  * EHCI hc_driver implementation ... experimental, incomplete.
0045  * Based on the final 1.0 register interface specification.
0046  *
0047  * USB 2.0 shows up in upcoming www.pcmcia.org technology.
0048  * First was PCMCIA, like ISA; then CardBus, which is PCI.
0049  * Next comes "CardBay", using USB 2.0 signals.
0050  *
0051  * Contains additional contributions by Brad Hards, Rory Bolt, and others.
0052  * Special thanks to Intel and VIA for providing host controllers to
0053  * test this driver on, and Cypress (including In-System Design) for
0054  * providing early devices for those host controllers to talk to!
0055  */
0056 
0057 #define DRIVER_AUTHOR "David Brownell"
0058 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
0059 
0060 static const char   hcd_name [] = "ehci_hcd";
0061 
0062 
0063 #undef EHCI_URB_TRACE
0064 
0065 /* magic numbers that can affect system performance */
0066 #define EHCI_TUNE_CERR      3   /* 0-3 qtd retries; 0 == don't stop */
0067 #define EHCI_TUNE_RL_HS     4   /* nak throttle; see 4.9 */
0068 #define EHCI_TUNE_RL_TT     0
0069 #define EHCI_TUNE_MULT_HS   1   /* 1-3 transactions/uframe; 4.10.3 */
0070 #define EHCI_TUNE_MULT_TT   1
0071 /*
0072  * Some drivers think it's safe to schedule isochronous transfers more than
0073  * 256 ms into the future (partly as a result of an old bug in the scheduling
0074  * code).  In an attempt to avoid trouble, we will use a minimum scheduling
0075  * length of 512 frames instead of 256.
0076  */
0077 #define EHCI_TUNE_FLS       1   /* (medium) 512-frame schedule */
0078 
0079 /* Initial IRQ latency:  faster than hw default */
0080 static int log2_irq_thresh;     // 0 to 6
0081 module_param (log2_irq_thresh, int, S_IRUGO);
0082 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
0083 
0084 /* initial park setting:  slower than hw default */
0085 static unsigned park;
0086 module_param (park, uint, S_IRUGO);
0087 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
0088 
0089 /* for flakey hardware, ignore overcurrent indicators */
0090 static bool ignore_oc;
0091 module_param (ignore_oc, bool, S_IRUGO);
0092 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
0093 
0094 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
0095 
0096 /*-------------------------------------------------------------------------*/
0097 
0098 #include "ehci.h"
0099 #include "pci-quirks.h"
0100 
0101 static void compute_tt_budget(u8 budget_table[EHCI_BANDWIDTH_SIZE],
0102         struct ehci_tt *tt);
0103 
0104 /*
0105  * The MosChip MCS9990 controller updates its microframe counter
0106  * a little before the frame counter, and occasionally we will read
0107  * the invalid intermediate value.  Avoid problems by checking the
0108  * microframe number (the low-order 3 bits); if they are 0 then
0109  * re-read the register to get the correct value.
0110  */
0111 static unsigned ehci_moschip_read_frame_index(struct ehci_hcd *ehci)
0112 {
0113     unsigned uf;
0114 
0115     uf = ehci_readl(ehci, &ehci->regs->frame_index);
0116     if (unlikely((uf & 7) == 0))
0117         uf = ehci_readl(ehci, &ehci->regs->frame_index);
0118     return uf;
0119 }
0120 
0121 static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
0122 {
0123     if (ehci->frame_index_bug)
0124         return ehci_moschip_read_frame_index(ehci);
0125     return ehci_readl(ehci, &ehci->regs->frame_index);
0126 }
0127 
0128 #include "ehci-dbg.c"
0129 
0130 /*-------------------------------------------------------------------------*/
0131 
0132 /*
0133  * ehci_handshake - spin reading hc until handshake completes or fails
0134  * @ptr: address of hc register to be read
0135  * @mask: bits to look at in result of read
0136  * @done: value of those bits when handshake succeeds
0137  * @usec: timeout in microseconds
0138  *
0139  * Returns negative errno, or zero on success
0140  *
0141  * Success happens when the "mask" bits have the specified value (hardware
0142  * handshake done).  There are two failure modes:  "usec" have passed (major
0143  * hardware flakeout), or the register reads as all-ones (hardware removed).
0144  *
0145  * That last failure should_only happen in cases like physical cardbus eject
0146  * before driver shutdown. But it also seems to be caused by bugs in cardbus
0147  * bridge shutdown:  shutting down the bridge before the devices using it.
0148  */
0149 int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
0150            u32 mask, u32 done, int usec)
0151 {
0152     u32 result;
0153 
0154     do {
0155         result = ehci_readl(ehci, ptr);
0156         if (result == ~(u32)0)      /* card removed */
0157             return -ENODEV;
0158         result &= mask;
0159         if (result == done)
0160             return 0;
0161         udelay (1);
0162         usec--;
0163     } while (usec > 0);
0164     return -ETIMEDOUT;
0165 }
0166 EXPORT_SYMBOL_GPL(ehci_handshake);
0167 
0168 /* check TDI/ARC silicon is in host mode */
0169 static int tdi_in_host_mode (struct ehci_hcd *ehci)
0170 {
0171     u32     tmp;
0172 
0173     tmp = ehci_readl(ehci, &ehci->regs->usbmode);
0174     return (tmp & 3) == USBMODE_CM_HC;
0175 }
0176 
0177 /*
0178  * Force HC to halt state from unknown (EHCI spec section 2.3).
0179  * Must be called with interrupts enabled and the lock not held.
0180  */
0181 static int ehci_halt (struct ehci_hcd *ehci)
0182 {
0183     u32 temp;
0184 
0185     spin_lock_irq(&ehci->lock);
0186 
0187     /* disable any irqs left enabled by previous code */
0188     ehci_writel(ehci, 0, &ehci->regs->intr_enable);
0189 
0190     if (ehci_is_TDI(ehci) && !tdi_in_host_mode(ehci)) {
0191         spin_unlock_irq(&ehci->lock);
0192         return 0;
0193     }
0194 
0195     /*
0196      * This routine gets called during probe before ehci->command
0197      * has been initialized, so we can't rely on its value.
0198      */
0199     ehci->command &= ~CMD_RUN;
0200     temp = ehci_readl(ehci, &ehci->regs->command);
0201     temp &= ~(CMD_RUN | CMD_IAAD);
0202     ehci_writel(ehci, temp, &ehci->regs->command);
0203 
0204     spin_unlock_irq(&ehci->lock);
0205     synchronize_irq(ehci_to_hcd(ehci)->irq);
0206 
0207     return ehci_handshake(ehci, &ehci->regs->status,
0208               STS_HALT, STS_HALT, 16 * 125);
0209 }
0210 
0211 /* put TDI/ARC silicon into EHCI mode */
0212 static void tdi_reset (struct ehci_hcd *ehci)
0213 {
0214     u32     tmp;
0215 
0216     tmp = ehci_readl(ehci, &ehci->regs->usbmode);
0217     tmp |= USBMODE_CM_HC;
0218     /* The default byte access to MMR space is LE after
0219      * controller reset. Set the required endian mode
0220      * for transfer buffers to match the host microprocessor
0221      */
0222     if (ehci_big_endian_mmio(ehci))
0223         tmp |= USBMODE_BE;
0224     ehci_writel(ehci, tmp, &ehci->regs->usbmode);
0225 }
0226 
0227 /*
0228  * Reset a non-running (STS_HALT == 1) controller.
0229  * Must be called with interrupts enabled and the lock not held.
0230  */
0231 int ehci_reset(struct ehci_hcd *ehci)
0232 {
0233     int retval;
0234     u32 command = ehci_readl(ehci, &ehci->regs->command);
0235 
0236     /* If the EHCI debug controller is active, special care must be
0237      * taken before and after a host controller reset */
0238     if (ehci->debug && !dbgp_reset_prep(ehci_to_hcd(ehci)))
0239         ehci->debug = NULL;
0240 
0241     command |= CMD_RESET;
0242     dbg_cmd (ehci, "reset", command);
0243     ehci_writel(ehci, command, &ehci->regs->command);
0244     ehci->rh_state = EHCI_RH_HALTED;
0245     ehci->next_statechange = jiffies;
0246     retval = ehci_handshake(ehci, &ehci->regs->command,
0247                 CMD_RESET, 0, 250 * 1000);
0248 
0249     if (ehci->has_hostpc) {
0250         ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
0251                 &ehci->regs->usbmode_ex);
0252         ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
0253     }
0254     if (retval)
0255         return retval;
0256 
0257     if (ehci_is_TDI(ehci))
0258         tdi_reset (ehci);
0259 
0260     if (ehci->debug)
0261         dbgp_external_startup(ehci_to_hcd(ehci));
0262 
0263     ehci->port_c_suspend = ehci->suspended_ports =
0264             ehci->resuming_ports = 0;
0265     return retval;
0266 }
0267 EXPORT_SYMBOL_GPL(ehci_reset);
0268 
0269 /*
0270  * Idle the controller (turn off the schedules).
0271  * Must be called with interrupts enabled and the lock not held.
0272  */
0273 static void ehci_quiesce (struct ehci_hcd *ehci)
0274 {
0275     u32 temp;
0276 
0277     if (ehci->rh_state != EHCI_RH_RUNNING)
0278         return;
0279 
0280     /* wait for any schedule enables/disables to take effect */
0281     temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
0282     ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp,
0283             16 * 125);
0284 
0285     /* then disable anything that's still active */
0286     spin_lock_irq(&ehci->lock);
0287     ehci->command &= ~(CMD_ASE | CMD_PSE);
0288     ehci_writel(ehci, ehci->command, &ehci->regs->command);
0289     spin_unlock_irq(&ehci->lock);
0290 
0291     /* hardware can take 16 microframes to turn off ... */
0292     ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0,
0293             16 * 125);
0294 }
0295 
0296 /*-------------------------------------------------------------------------*/
0297 
0298 static void end_iaa_cycle(struct ehci_hcd *ehci);
0299 static void end_unlink_async(struct ehci_hcd *ehci);
0300 static void unlink_empty_async(struct ehci_hcd *ehci);
0301 static void ehci_work(struct ehci_hcd *ehci);
0302 static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
0303 static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
0304 static int ehci_port_power(struct ehci_hcd *ehci, int portnum, bool enable);
0305 
0306 #include "ehci-timer.c"
0307 #include "ehci-hub.c"
0308 #include "ehci-mem.c"
0309 #include "ehci-q.c"
0310 #include "ehci-sched.c"
0311 #include "ehci-sysfs.c"
0312 
0313 /*-------------------------------------------------------------------------*/
0314 
0315 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
0316  * The firmware seems to think that powering off is a wakeup event!
0317  * This routine turns off remote wakeup and everything else, on all ports.
0318  */
0319 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
0320 {
0321     int port = HCS_N_PORTS(ehci->hcs_params);
0322 
0323     while (port--) {
0324         spin_unlock_irq(&ehci->lock);
0325         ehci_port_power(ehci, port, false);
0326         spin_lock_irq(&ehci->lock);
0327         ehci_writel(ehci, PORT_RWC_BITS,
0328                 &ehci->regs->port_status[port]);
0329     }
0330 }
0331 
0332 /*
0333  * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
0334  * Must be called with interrupts enabled and the lock not held.
0335  */
0336 static void ehci_silence_controller(struct ehci_hcd *ehci)
0337 {
0338     ehci_halt(ehci);
0339 
0340     spin_lock_irq(&ehci->lock);
0341     ehci->rh_state = EHCI_RH_HALTED;
0342     ehci_turn_off_all_ports(ehci);
0343 
0344     /* make BIOS/etc use companion controller during reboot */
0345     ehci_writel(ehci, 0, &ehci->regs->configured_flag);
0346 
0347     /* unblock posted writes */
0348     ehci_readl(ehci, &ehci->regs->configured_flag);
0349     spin_unlock_irq(&ehci->lock);
0350 }
0351 
0352 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
0353  * This forcibly disables dma and IRQs, helping kexec and other cases
0354  * where the next system software may expect clean state.
0355  */
0356 static void ehci_shutdown(struct usb_hcd *hcd)
0357 {
0358     struct ehci_hcd *ehci = hcd_to_ehci(hcd);
0359 
0360     /**
0361      * Protect the system from crashing at system shutdown in cases where
0362      * usb host is not added yet from OTG controller driver.
0363      * As ehci_setup() not done yet, so stop accessing registers or
0364      * variables initialized in ehci_setup()
0365      */
0366     if (!ehci->sbrn)
0367         return;
0368 
0369     spin_lock_irq(&ehci->lock);
0370     ehci->shutdown = true;
0371     ehci->rh_state = EHCI_RH_STOPPING;
0372     ehci->enabled_hrtimer_events = 0;
0373     spin_unlock_irq(&ehci->lock);
0374 
0375     ehci_silence_controller(ehci);
0376 
0377     hrtimer_cancel(&ehci->hrtimer);
0378 }
0379 
0380 /*-------------------------------------------------------------------------*/
0381 
0382 /*
0383  * ehci_work is called from some interrupts, timers, and so on.
0384  * it calls driver completion functions, after dropping ehci->lock.
0385  */
0386 static void ehci_work (struct ehci_hcd *ehci)
0387 {
0388     /* another CPU may drop ehci->lock during a schedule scan while
0389      * it reports urb completions.  this flag guards against bogus
0390      * attempts at re-entrant schedule scanning.
0391      */
0392     if (ehci->scanning) {
0393         ehci->need_rescan = true;
0394         return;
0395     }
0396     ehci->scanning = true;
0397 
0398  rescan:
0399     ehci->need_rescan = false;
0400     if (ehci->async_count)
0401         scan_async(ehci);
0402     if (ehci->intr_count > 0)
0403         scan_intr(ehci);
0404     if (ehci->isoc_count > 0)
0405         scan_isoc(ehci);
0406     if (ehci->need_rescan)
0407         goto rescan;
0408     ehci->scanning = false;
0409 
0410     /* the IO watchdog guards against hardware or driver bugs that
0411      * misplace IRQs, and should let us run completely without IRQs.
0412      * such lossage has been observed on both VT6202 and VT8235.
0413      */
0414     turn_on_io_watchdog(ehci);
0415 }
0416 
0417 /*
0418  * Called when the ehci_hcd module is removed.
0419  */
0420 static void ehci_stop (struct usb_hcd *hcd)
0421 {
0422     struct ehci_hcd     *ehci = hcd_to_ehci (hcd);
0423 
0424     ehci_dbg (ehci, "stop\n");
0425 
0426     /* no more interrupts ... */
0427 
0428     spin_lock_irq(&ehci->lock);
0429     ehci->enabled_hrtimer_events = 0;
0430     spin_unlock_irq(&ehci->lock);
0431 
0432     ehci_quiesce(ehci);
0433     ehci_silence_controller(ehci);
0434     ehci_reset (ehci);
0435 
0436     hrtimer_cancel(&ehci->hrtimer);
0437     remove_sysfs_files(ehci);
0438     remove_debug_files (ehci);
0439 
0440     /* root hub is shut down separately (first, when possible) */
0441     spin_lock_irq (&ehci->lock);
0442     end_free_itds(ehci);
0443     spin_unlock_irq (&ehci->lock);
0444     ehci_mem_cleanup (ehci);
0445 
0446     if (ehci->amd_pll_fix == 1)
0447         usb_amd_dev_put();
0448 
0449     dbg_status (ehci, "ehci_stop completed",
0450             ehci_readl(ehci, &ehci->regs->status));
0451 }
0452 
0453 /* one-time init, only for memory state */
0454 static int ehci_init(struct usb_hcd *hcd)
0455 {
0456     struct ehci_hcd     *ehci = hcd_to_ehci(hcd);
0457     u32         temp;
0458     int         retval;
0459     u32         hcc_params;
0460     struct ehci_qh_hw   *hw;
0461 
0462     spin_lock_init(&ehci->lock);
0463 
0464     /*
0465      * keep io watchdog by default, those good HCDs could turn off it later
0466      */
0467     ehci->need_io_watchdog = 1;
0468 
0469     hrtimer_init(&ehci->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
0470     ehci->hrtimer.function = ehci_hrtimer_func;
0471     ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT;
0472 
0473     hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
0474 
0475     /*
0476      * by default set standard 80% (== 100 usec/uframe) max periodic
0477      * bandwidth as required by USB 2.0
0478      */
0479     ehci->uframe_periodic_max = 100;
0480 
0481     /*
0482      * hw default: 1K periodic list heads, one per frame.
0483      * periodic_size can shrink by USBCMD update if hcc_params allows.
0484      */
0485     ehci->periodic_size = DEFAULT_I_TDPS;
0486     INIT_LIST_HEAD(&ehci->async_unlink);
0487     INIT_LIST_HEAD(&ehci->async_idle);
0488     INIT_LIST_HEAD(&ehci->intr_unlink_wait);
0489     INIT_LIST_HEAD(&ehci->intr_unlink);
0490     INIT_LIST_HEAD(&ehci->intr_qh_list);
0491     INIT_LIST_HEAD(&ehci->cached_itd_list);
0492     INIT_LIST_HEAD(&ehci->cached_sitd_list);
0493     INIT_LIST_HEAD(&ehci->tt_list);
0494 
0495     if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
0496         /* periodic schedule size can be smaller than default */
0497         switch (EHCI_TUNE_FLS) {
0498         case 0: ehci->periodic_size = 1024; break;
0499         case 1: ehci->periodic_size = 512; break;
0500         case 2: ehci->periodic_size = 256; break;
0501         default:    BUG();
0502         }
0503     }
0504     if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
0505         return retval;
0506 
0507     /* controllers may cache some of the periodic schedule ... */
0508     if (HCC_ISOC_CACHE(hcc_params))     // full frame cache
0509         ehci->i_thresh = 0;
0510     else                    // N microframes cached
0511         ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
0512 
0513     /*
0514      * dedicate a qh for the async ring head, since we couldn't unlink
0515      * a 'real' qh without stopping the async schedule [4.8].  use it
0516      * as the 'reclamation list head' too.
0517      * its dummy is used in hw_alt_next of many tds, to prevent the qh
0518      * from automatically advancing to the next td after short reads.
0519      */
0520     ehci->async->qh_next.qh = NULL;
0521     hw = ehci->async->hw;
0522     hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
0523     hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
0524 #if defined(CONFIG_PPC_PS3)
0525     hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE);
0526 #endif
0527     hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
0528     hw->hw_qtd_next = EHCI_LIST_END(ehci);
0529     ehci->async->qh_state = QH_STATE_LINKED;
0530     hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
0531 
0532     /* clear interrupt enables, set irq latency */
0533     if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
0534         log2_irq_thresh = 0;
0535     temp = 1 << (16 + log2_irq_thresh);
0536     if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
0537         ehci->has_ppcd = 1;
0538         ehci_dbg(ehci, "enable per-port change event\n");
0539         temp |= CMD_PPCEE;
0540     }
0541     if (HCC_CANPARK(hcc_params)) {
0542         /* HW default park == 3, on hardware that supports it (like
0543          * NVidia and ALI silicon), maximizes throughput on the async
0544          * schedule by avoiding QH fetches between transfers.
0545          *
0546          * With fast usb storage devices and NForce2, "park" seems to
0547          * make problems:  throughput reduction (!), data errors...
0548          */
0549         if (park) {
0550             park = min(park, (unsigned) 3);
0551             temp |= CMD_PARK;
0552             temp |= park << 8;
0553         }
0554         ehci_dbg(ehci, "park %d\n", park);
0555     }
0556     if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
0557         /* periodic schedule size can be smaller than default */
0558         temp &= ~(3 << 2);
0559         temp |= (EHCI_TUNE_FLS << 2);
0560     }
0561     ehci->command = temp;
0562 
0563     /* Accept arbitrarily long scatter-gather lists */
0564     if (!hcd->localmem_pool)
0565         hcd->self.sg_tablesize = ~0;
0566 
0567     /* Prepare for unlinking active QHs */
0568     ehci->old_current = ~0;
0569     return 0;
0570 }
0571 
0572 /* start HC running; it's halted, ehci_init() has been run (once) */
0573 static int ehci_run (struct usb_hcd *hcd)
0574 {
0575     struct ehci_hcd     *ehci = hcd_to_ehci (hcd);
0576     u32         temp;
0577     u32         hcc_params;
0578     int         rc;
0579 
0580     hcd->uses_new_polling = 1;
0581 
0582     /* EHCI spec section 4.1 */
0583 
0584     ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
0585     ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
0586 
0587     /*
0588      * hcc_params controls whether ehci->regs->segment must (!!!)
0589      * be used; it constrains QH/ITD/SITD and QTD locations.
0590      * dma_pool consistent memory always uses segment zero.
0591      * streaming mappings for I/O buffers, like dma_map_single(),
0592      * can return segments above 4GB, if the device allows.
0593      *
0594      * NOTE:  the dma mask is visible through dev->dma_mask, so
0595      * drivers can pass this info along ... like NETIF_F_HIGHDMA,
0596      * Scsi_Host.highmem_io, and so forth.  It's readonly to all
0597      * host side drivers though.
0598      */
0599     hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
0600     if (HCC_64BIT_ADDR(hcc_params)) {
0601         ehci_writel(ehci, 0, &ehci->regs->segment);
0602 #if 0
0603 // this is deeply broken on almost all architectures
0604         if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
0605             ehci_info(ehci, "enabled 64bit DMA\n");
0606 #endif
0607     }
0608 
0609 
0610     // Philips, Intel, and maybe others need CMD_RUN before the
0611     // root hub will detect new devices (why?); NEC doesn't
0612     ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
0613     ehci->command |= CMD_RUN;
0614     ehci_writel(ehci, ehci->command, &ehci->regs->command);
0615     dbg_cmd (ehci, "init", ehci->command);
0616 
0617     /*
0618      * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
0619      * are explicitly handed to companion controller(s), so no TT is
0620      * involved with the root hub.  (Except where one is integrated,
0621      * and there's no companion controller unless maybe for USB OTG.)
0622      *
0623      * Turning on the CF flag will transfer ownership of all ports
0624      * from the companions to the EHCI controller.  If any of the
0625      * companions are in the middle of a port reset at the time, it
0626      * could cause trouble.  Write-locking ehci_cf_port_reset_rwsem
0627      * guarantees that no resets are in progress.  After we set CF,
0628      * a short delay lets the hardware catch up; new resets shouldn't
0629      * be started before the port switching actions could complete.
0630      */
0631     down_write(&ehci_cf_port_reset_rwsem);
0632     ehci->rh_state = EHCI_RH_RUNNING;
0633     ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
0634 
0635     /* Wait until HC become operational */
0636     ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
0637     msleep(5);
0638 
0639     /* For Aspeed, STS_HALT also depends on ASS/PSS status.
0640      * Check CMD_RUN instead.
0641      */
0642     if (ehci->is_aspeed)
0643         rc = ehci_handshake(ehci, &ehci->regs->command, CMD_RUN,
0644                     1, 100 * 1000);
0645     else
0646         rc = ehci_handshake(ehci, &ehci->regs->status, STS_HALT,
0647                     0, 100 * 1000);
0648 
0649     up_write(&ehci_cf_port_reset_rwsem);
0650 
0651     if (rc) {
0652         ehci_err(ehci, "USB %x.%x, controller refused to start: %d\n",
0653              ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), rc);
0654         return rc;
0655     }
0656 
0657     ehci->last_periodic_enable = ktime_get_real();
0658 
0659     temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
0660     ehci_info (ehci,
0661         "USB %x.%x started, EHCI %x.%02x%s\n",
0662         ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
0663         temp >> 8, temp & 0xff,
0664         (ignore_oc || ehci->spurious_oc) ? ", overcurrent ignored" : "");
0665 
0666     ehci_writel(ehci, INTR_MASK,
0667             &ehci->regs->intr_enable); /* Turn On Interrupts */
0668 
0669     /* GRR this is run-once init(), being done every time the HC starts.
0670      * So long as they're part of class devices, we can't do it init()
0671      * since the class device isn't created that early.
0672      */
0673     create_debug_files(ehci);
0674     create_sysfs_files(ehci);
0675 
0676     return 0;
0677 }
0678 
0679 int ehci_setup(struct usb_hcd *hcd)
0680 {
0681     struct ehci_hcd *ehci = hcd_to_ehci(hcd);
0682     int retval;
0683 
0684     ehci->regs = (void __iomem *)ehci->caps +
0685         HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
0686     dbg_hcs_params(ehci, "reset");
0687     dbg_hcc_params(ehci, "reset");
0688 
0689     /* cache this readonly data; minimize chip reads */
0690     ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
0691 
0692     ehci->sbrn = HCD_USB2;
0693 
0694     /* data structure init */
0695     retval = ehci_init(hcd);
0696     if (retval)
0697         return retval;
0698 
0699     retval = ehci_halt(ehci);
0700     if (retval) {
0701         ehci_mem_cleanup(ehci);
0702         return retval;
0703     }
0704 
0705     ehci_reset(ehci);
0706 
0707     return 0;
0708 }
0709 EXPORT_SYMBOL_GPL(ehci_setup);
0710 
0711 /*-------------------------------------------------------------------------*/
0712 
0713 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
0714 {
0715     struct ehci_hcd     *ehci = hcd_to_ehci (hcd);
0716     u32         status, current_status, masked_status, pcd_status = 0;
0717     u32         cmd;
0718     int         bh;
0719 
0720     spin_lock(&ehci->lock);
0721 
0722     status = 0;
0723     current_status = ehci_readl(ehci, &ehci->regs->status);
0724 restart:
0725 
0726     /* e.g. cardbus physical eject */
0727     if (current_status == ~(u32) 0) {
0728         ehci_dbg (ehci, "device removed\n");
0729         goto dead;
0730     }
0731     status |= current_status;
0732 
0733     /*
0734      * We don't use STS_FLR, but some controllers don't like it to
0735      * remain on, so mask it out along with the other status bits.
0736      */
0737     masked_status = current_status & (INTR_MASK | STS_FLR);
0738 
0739     /* Shared IRQ? */
0740     if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
0741         spin_unlock(&ehci->lock);
0742         return IRQ_NONE;
0743     }
0744 
0745     /* clear (just) interrupts */
0746     ehci_writel(ehci, masked_status, &ehci->regs->status);
0747 
0748     /* For edge interrupts, don't race with an interrupt bit being raised */
0749     current_status = ehci_readl(ehci, &ehci->regs->status);
0750     if (current_status & INTR_MASK)
0751         goto restart;
0752 
0753     cmd = ehci_readl(ehci, &ehci->regs->command);
0754     bh = 0;
0755 
0756     /* normal [4.15.1.2] or error [4.15.1.1] completion */
0757     if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
0758         if (likely ((status & STS_ERR) == 0))
0759             INCR(ehci->stats.normal);
0760         else
0761             INCR(ehci->stats.error);
0762         bh = 1;
0763     }
0764 
0765     /* complete the unlinking of some qh [4.15.2.3] */
0766     if (status & STS_IAA) {
0767 
0768         /* Turn off the IAA watchdog */
0769         ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG);
0770 
0771         /*
0772          * Mild optimization: Allow another IAAD to reset the
0773          * hrtimer, if one occurs before the next expiration.
0774          * In theory we could always cancel the hrtimer, but
0775          * tests show that about half the time it will be reset
0776          * for some other event anyway.
0777          */
0778         if (ehci->next_hrtimer_event == EHCI_HRTIMER_IAA_WATCHDOG)
0779             ++ehci->next_hrtimer_event;
0780 
0781         /* guard against (alleged) silicon errata */
0782         if (cmd & CMD_IAAD)
0783             ehci_dbg(ehci, "IAA with IAAD still set?\n");
0784         if (ehci->iaa_in_progress)
0785             INCR(ehci->stats.iaa);
0786         end_iaa_cycle(ehci);
0787     }
0788 
0789     /* remote wakeup [4.3.1] */
0790     if (status & STS_PCD) {
0791         unsigned    i = HCS_N_PORTS (ehci->hcs_params);
0792         u32     ppcd = ~0;
0793 
0794         /* kick root hub later */
0795         pcd_status = status;
0796 
0797         /* resume root hub? */
0798         if (ehci->rh_state == EHCI_RH_SUSPENDED)
0799             usb_hcd_resume_root_hub(hcd);
0800 
0801         /* get per-port change detect bits */
0802         if (ehci->has_ppcd)
0803             ppcd = status >> 16;
0804 
0805         while (i--) {
0806             int pstatus;
0807 
0808             /* leverage per-port change bits feature */
0809             if (!(ppcd & (1 << i)))
0810                 continue;
0811             pstatus = ehci_readl(ehci,
0812                      &ehci->regs->port_status[i]);
0813 
0814             if (pstatus & PORT_OWNER)
0815                 continue;
0816             if (!(test_bit(i, &ehci->suspended_ports) &&
0817                     ((pstatus & PORT_RESUME) ||
0818                         !(pstatus & PORT_SUSPEND)) &&
0819                     (pstatus & PORT_PE) &&
0820                     ehci->reset_done[i] == 0))
0821                 continue;
0822 
0823             /* start USB_RESUME_TIMEOUT msec resume signaling from
0824              * this port, and make hub_wq collect
0825              * PORT_STAT_C_SUSPEND to stop that signaling.
0826              */
0827             ehci->reset_done[i] = jiffies +
0828                 msecs_to_jiffies(USB_RESUME_TIMEOUT);
0829             set_bit(i, &ehci->resuming_ports);
0830             ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
0831             usb_hcd_start_port_resume(&hcd->self, i);
0832             mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
0833         }
0834     }
0835 
0836     /* PCI errors [4.15.2.4] */
0837     if (unlikely ((status & STS_FATAL) != 0)) {
0838         ehci_err(ehci, "fatal error\n");
0839         dbg_cmd(ehci, "fatal", cmd);
0840         dbg_status(ehci, "fatal", status);
0841 dead:
0842         usb_hc_died(hcd);
0843 
0844         /* Don't let the controller do anything more */
0845         ehci->shutdown = true;
0846         ehci->rh_state = EHCI_RH_STOPPING;
0847         ehci->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
0848         ehci_writel(ehci, ehci->command, &ehci->regs->command);
0849         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
0850         ehci_handle_controller_death(ehci);
0851 
0852         /* Handle completions when the controller stops */
0853         bh = 0;
0854     }
0855 
0856     if (bh)
0857         ehci_work (ehci);
0858     spin_unlock(&ehci->lock);
0859     if (pcd_status)
0860         usb_hcd_poll_rh_status(hcd);
0861     return IRQ_HANDLED;
0862 }
0863 
0864 /*-------------------------------------------------------------------------*/
0865 
0866 /*
0867  * non-error returns are a promise to giveback() the urb later
0868  * we drop ownership so next owner (or urb unlink) can get it
0869  *
0870  * urb + dev is in hcd.self.controller.urb_list
0871  * we're queueing TDs onto software and hardware lists
0872  *
0873  * hcd-specific init for hcpriv hasn't been done yet
0874  *
0875  * NOTE:  control, bulk, and interrupt share the same code to append TDs
0876  * to a (possibly active) QH, and the same QH scanning code.
0877  */
0878 static int ehci_urb_enqueue (
0879     struct usb_hcd  *hcd,
0880     struct urb  *urb,
0881     gfp_t       mem_flags
0882 ) {
0883     struct ehci_hcd     *ehci = hcd_to_ehci (hcd);
0884     struct list_head    qtd_list;
0885 
0886     INIT_LIST_HEAD (&qtd_list);
0887 
0888     switch (usb_pipetype (urb->pipe)) {
0889     case PIPE_CONTROL:
0890         /* qh_completions() code doesn't handle all the fault cases
0891          * in multi-TD control transfers.  Even 1KB is rare anyway.
0892          */
0893         if (urb->transfer_buffer_length > (16 * 1024))
0894             return -EMSGSIZE;
0895         fallthrough;
0896     /* case PIPE_BULK: */
0897     default:
0898         if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
0899             return -ENOMEM;
0900         return submit_async(ehci, urb, &qtd_list, mem_flags);
0901 
0902     case PIPE_INTERRUPT:
0903         if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
0904             return -ENOMEM;
0905         return intr_submit(ehci, urb, &qtd_list, mem_flags);
0906 
0907     case PIPE_ISOCHRONOUS:
0908         if (urb->dev->speed == USB_SPEED_HIGH)
0909             return itd_submit (ehci, urb, mem_flags);
0910         else
0911             return sitd_submit (ehci, urb, mem_flags);
0912     }
0913 }
0914 
0915 /* remove from hardware lists
0916  * completions normally happen asynchronously
0917  */
0918 
0919 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
0920 {
0921     struct ehci_hcd     *ehci = hcd_to_ehci (hcd);
0922     struct ehci_qh      *qh;
0923     unsigned long       flags;
0924     int         rc;
0925 
0926     spin_lock_irqsave (&ehci->lock, flags);
0927     rc = usb_hcd_check_unlink_urb(hcd, urb, status);
0928     if (rc)
0929         goto done;
0930 
0931     if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
0932         /*
0933          * We don't expedite dequeue for isochronous URBs.
0934          * Just wait until they complete normally or their
0935          * time slot expires.
0936          */
0937     } else {
0938         qh = (struct ehci_qh *) urb->hcpriv;
0939         qh->unlink_reason |= QH_UNLINK_REQUESTED;
0940         switch (qh->qh_state) {
0941         case QH_STATE_LINKED:
0942             if (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)
0943                 start_unlink_intr(ehci, qh);
0944             else
0945                 start_unlink_async(ehci, qh);
0946             break;
0947         case QH_STATE_COMPLETING:
0948             qh->dequeue_during_giveback = 1;
0949             break;
0950         case QH_STATE_UNLINK:
0951         case QH_STATE_UNLINK_WAIT:
0952             /* already started */
0953             break;
0954         case QH_STATE_IDLE:
0955             /* QH might be waiting for a Clear-TT-Buffer */
0956             qh_completions(ehci, qh);
0957             break;
0958         }
0959     }
0960 done:
0961     spin_unlock_irqrestore (&ehci->lock, flags);
0962     return rc;
0963 }
0964 
0965 /*-------------------------------------------------------------------------*/
0966 
0967 // bulk qh holds the data toggle
0968 
0969 static void
0970 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
0971 {
0972     struct ehci_hcd     *ehci = hcd_to_ehci (hcd);
0973     unsigned long       flags;
0974     struct ehci_qh      *qh;
0975 
0976     /* ASSERT:  any requests/urbs are being unlinked */
0977     /* ASSERT:  nobody can be submitting urbs for this any more */
0978 
0979 rescan:
0980     spin_lock_irqsave (&ehci->lock, flags);
0981     qh = ep->hcpriv;
0982     if (!qh)
0983         goto done;
0984 
0985     /* endpoints can be iso streams.  for now, we don't
0986      * accelerate iso completions ... so spin a while.
0987      */
0988     if (qh->hw == NULL) {
0989         struct ehci_iso_stream  *stream = ep->hcpriv;
0990 
0991         if (!list_empty(&stream->td_list))
0992             goto idle_timeout;
0993 
0994         /* BUG_ON(!list_empty(&stream->free_list)); */
0995         reserve_release_iso_bandwidth(ehci, stream, -1);
0996         kfree(stream);
0997         goto done;
0998     }
0999 
1000     qh->unlink_reason |= QH_UNLINK_REQUESTED;
1001     switch (qh->qh_state) {
1002     case QH_STATE_LINKED:
1003         if (list_empty(&qh->qtd_list))
1004             qh->unlink_reason |= QH_UNLINK_QUEUE_EMPTY;
1005         else
1006             WARN_ON(1);
1007         if (usb_endpoint_type(&ep->desc) != USB_ENDPOINT_XFER_INT)
1008             start_unlink_async(ehci, qh);
1009         else
1010             start_unlink_intr(ehci, qh);
1011         fallthrough;
1012     case QH_STATE_COMPLETING:   /* already in unlinking */
1013     case QH_STATE_UNLINK:       /* wait for hw to finish? */
1014     case QH_STATE_UNLINK_WAIT:
1015 idle_timeout:
1016         spin_unlock_irqrestore (&ehci->lock, flags);
1017         schedule_timeout_uninterruptible(1);
1018         goto rescan;
1019     case QH_STATE_IDLE:     /* fully unlinked */
1020         if (qh->clearing_tt)
1021             goto idle_timeout;
1022         if (list_empty (&qh->qtd_list)) {
1023             if (qh->ps.bw_uperiod)
1024                 reserve_release_intr_bandwidth(ehci, qh, -1);
1025             qh_destroy(ehci, qh);
1026             break;
1027         }
1028         fallthrough;
1029     default:
1030         /* caller was supposed to have unlinked any requests;
1031          * that's not our job.  just leak this memory.
1032          */
1033         ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1034             qh, ep->desc.bEndpointAddress, qh->qh_state,
1035             list_empty (&qh->qtd_list) ? "" : "(has tds)");
1036         break;
1037     }
1038  done:
1039     ep->hcpriv = NULL;
1040     spin_unlock_irqrestore (&ehci->lock, flags);
1041 }
1042 
1043 static void
1044 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1045 {
1046     struct ehci_hcd     *ehci = hcd_to_ehci(hcd);
1047     struct ehci_qh      *qh;
1048     int         eptype = usb_endpoint_type(&ep->desc);
1049     int         epnum = usb_endpoint_num(&ep->desc);
1050     int         is_out = usb_endpoint_dir_out(&ep->desc);
1051     unsigned long       flags;
1052 
1053     if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1054         return;
1055 
1056     spin_lock_irqsave(&ehci->lock, flags);
1057     qh = ep->hcpriv;
1058 
1059     /* For Bulk and Interrupt endpoints we maintain the toggle state
1060      * in the hardware; the toggle bits in udev aren't used at all.
1061      * When an endpoint is reset by usb_clear_halt() we must reset
1062      * the toggle bit in the QH.
1063      */
1064     if (qh) {
1065         if (!list_empty(&qh->qtd_list)) {
1066             WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1067         } else {
1068             /* The toggle value in the QH can't be updated
1069              * while the QH is active.  Unlink it now;
1070              * re-linking will call qh_refresh().
1071              */
1072             usb_settoggle(qh->ps.udev, epnum, is_out, 0);
1073             qh->unlink_reason |= QH_UNLINK_REQUESTED;
1074             if (eptype == USB_ENDPOINT_XFER_BULK)
1075                 start_unlink_async(ehci, qh);
1076             else
1077                 start_unlink_intr(ehci, qh);
1078         }
1079     }
1080     spin_unlock_irqrestore(&ehci->lock, flags);
1081 }
1082 
1083 static int ehci_get_frame (struct usb_hcd *hcd)
1084 {
1085     struct ehci_hcd     *ehci = hcd_to_ehci (hcd);
1086     return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1087 }
1088 
1089 /*-------------------------------------------------------------------------*/
1090 
1091 /* Device addition and removal */
1092 
1093 static void ehci_remove_device(struct usb_hcd *hcd, struct usb_device *udev)
1094 {
1095     struct ehci_hcd     *ehci = hcd_to_ehci(hcd);
1096 
1097     spin_lock_irq(&ehci->lock);
1098     drop_tt(udev);
1099     spin_unlock_irq(&ehci->lock);
1100 }
1101 
1102 /*-------------------------------------------------------------------------*/
1103 
1104 #ifdef  CONFIG_PM
1105 
1106 /* Clear wakeup signal locked in zhaoxin platform when device plug in. */
1107 static void ehci_zx_wakeup_clear(struct ehci_hcd *ehci)
1108 {
1109     u32 __iomem *reg = &ehci->regs->port_status[4];
1110     u32         t1 = ehci_readl(ehci, reg);
1111 
1112     t1 &= (u32)~0xf0000;
1113     t1 |= PORT_TEST_FORCE;
1114     ehci_writel(ehci, t1, reg);
1115     t1 = ehci_readl(ehci, reg);
1116     msleep(1);
1117     t1 &= (u32)~0xf0000;
1118     ehci_writel(ehci, t1, reg);
1119     ehci_readl(ehci, reg);
1120     msleep(1);
1121     t1 = ehci_readl(ehci, reg);
1122     ehci_writel(ehci, t1 | PORT_CSC, reg);
1123     ehci_readl(ehci, reg);
1124 }
1125 
1126 /* suspend/resume, section 4.3 */
1127 
1128 /* These routines handle the generic parts of controller suspend/resume */
1129 
1130 int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1131 {
1132     struct ehci_hcd     *ehci = hcd_to_ehci(hcd);
1133 
1134     if (time_before(jiffies, ehci->next_statechange))
1135         msleep(10);
1136 
1137     /*
1138      * Root hub was already suspended.  Disable IRQ emission and
1139      * mark HW unaccessible.  The PM and USB cores make sure that
1140      * the root hub is either suspended or stopped.
1141      */
1142     ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
1143 
1144     spin_lock_irq(&ehci->lock);
1145     ehci_writel(ehci, 0, &ehci->regs->intr_enable);
1146     (void) ehci_readl(ehci, &ehci->regs->intr_enable);
1147 
1148     clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1149     spin_unlock_irq(&ehci->lock);
1150 
1151     synchronize_irq(hcd->irq);
1152 
1153     /* Check for race with a wakeup request */
1154     if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1155         ehci_resume(hcd, false);
1156         return -EBUSY;
1157     }
1158 
1159     return 0;
1160 }
1161 EXPORT_SYMBOL_GPL(ehci_suspend);
1162 
1163 /* Returns 0 if power was preserved, 1 if power was lost */
1164 int ehci_resume(struct usb_hcd *hcd, bool force_reset)
1165 {
1166     struct ehci_hcd     *ehci = hcd_to_ehci(hcd);
1167 
1168     if (time_before(jiffies, ehci->next_statechange))
1169         msleep(100);
1170 
1171     /* Mark hardware accessible again as we are back to full power by now */
1172     set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1173 
1174     if (ehci->shutdown)
1175         return 0;       /* Controller is dead */
1176 
1177     if (ehci->zx_wakeup_clear_needed)
1178         ehci_zx_wakeup_clear(ehci);
1179 
1180     /*
1181      * If CF is still set and reset isn't forced
1182      * then we maintained suspend power.
1183      * Just undo the effect of ehci_suspend().
1184      */
1185     if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
1186             !force_reset) {
1187         int mask = INTR_MASK;
1188 
1189         ehci_prepare_ports_for_controller_resume(ehci);
1190 
1191         spin_lock_irq(&ehci->lock);
1192         if (ehci->shutdown)
1193             goto skip;
1194 
1195         if (!hcd->self.root_hub->do_remote_wakeup)
1196             mask &= ~STS_PCD;
1197         ehci_writel(ehci, mask, &ehci->regs->intr_enable);
1198         ehci_readl(ehci, &ehci->regs->intr_enable);
1199  skip:
1200         spin_unlock_irq(&ehci->lock);
1201         return 0;
1202     }
1203 
1204     /*
1205      * Else reset, to cope with power loss or resume from hibernation
1206      * having let the firmware kick in during reboot.
1207      */
1208     usb_root_hub_lost_power(hcd->self.root_hub);
1209     (void) ehci_halt(ehci);
1210     (void) ehci_reset(ehci);
1211 
1212     spin_lock_irq(&ehci->lock);
1213     if (ehci->shutdown)
1214         goto skip;
1215 
1216     ehci_writel(ehci, ehci->command, &ehci->regs->command);
1217     ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
1218     ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
1219 
1220     ehci->rh_state = EHCI_RH_SUSPENDED;
1221     spin_unlock_irq(&ehci->lock);
1222 
1223     return 1;
1224 }
1225 EXPORT_SYMBOL_GPL(ehci_resume);
1226 
1227 #endif
1228 
1229 /*-------------------------------------------------------------------------*/
1230 
1231 /*
1232  * Generic structure: This gets copied for platform drivers so that
1233  * individual entries can be overridden as needed.
1234  */
1235 
1236 static const struct hc_driver ehci_hc_driver = {
1237     .description =      hcd_name,
1238     .product_desc =     "EHCI Host Controller",
1239     .hcd_priv_size =    sizeof(struct ehci_hcd),
1240 
1241     /*
1242      * generic hardware linkage
1243      */
1244     .irq =          ehci_irq,
1245     .flags =        HCD_MEMORY | HCD_DMA | HCD_USB2 | HCD_BH,
1246 
1247     /*
1248      * basic lifecycle operations
1249      */
1250     .reset =        ehci_setup,
1251     .start =        ehci_run,
1252     .stop =         ehci_stop,
1253     .shutdown =     ehci_shutdown,
1254 
1255     /*
1256      * managing i/o requests and associated device resources
1257      */
1258     .urb_enqueue =      ehci_urb_enqueue,
1259     .urb_dequeue =      ehci_urb_dequeue,
1260     .endpoint_disable = ehci_endpoint_disable,
1261     .endpoint_reset =   ehci_endpoint_reset,
1262     .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
1263 
1264     /*
1265      * scheduling support
1266      */
1267     .get_frame_number = ehci_get_frame,
1268 
1269     /*
1270      * root hub support
1271      */
1272     .hub_status_data =  ehci_hub_status_data,
1273     .hub_control =      ehci_hub_control,
1274     .bus_suspend =      ehci_bus_suspend,
1275     .bus_resume =       ehci_bus_resume,
1276     .relinquish_port =  ehci_relinquish_port,
1277     .port_handed_over = ehci_port_handed_over,
1278     .get_resuming_ports =   ehci_get_resuming_ports,
1279 
1280     /*
1281      * device support
1282      */
1283     .free_dev =     ehci_remove_device,
1284 #ifdef CONFIG_USB_HCD_TEST_MODE
1285     /* EH SINGLE_STEP_SET_FEATURE test support */
1286     .submit_single_step_set_feature = ehci_submit_single_step_set_feature,
1287 #endif
1288 };
1289 
1290 void ehci_init_driver(struct hc_driver *drv,
1291         const struct ehci_driver_overrides *over)
1292 {
1293     /* Copy the generic table to drv and then apply the overrides */
1294     *drv = ehci_hc_driver;
1295 
1296     if (over) {
1297         drv->hcd_priv_size += over->extra_priv_size;
1298         if (over->reset)
1299             drv->reset = over->reset;
1300         if (over->port_power)
1301             drv->port_power = over->port_power;
1302     }
1303 }
1304 EXPORT_SYMBOL_GPL(ehci_init_driver);
1305 
1306 /*-------------------------------------------------------------------------*/
1307 
1308 MODULE_DESCRIPTION(DRIVER_DESC);
1309 MODULE_AUTHOR (DRIVER_AUTHOR);
1310 MODULE_LICENSE ("GPL");
1311 
1312 #ifdef CONFIG_USB_EHCI_SH
1313 #include "ehci-sh.c"
1314 #endif
1315 
1316 #ifdef CONFIG_PPC_PS3
1317 #include "ehci-ps3.c"
1318 #endif
1319 
1320 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1321 #include "ehci-ppc-of.c"
1322 #endif
1323 
1324 #ifdef CONFIG_XPS_USB_HCD_XILINX
1325 #include "ehci-xilinx-of.c"
1326 #endif
1327 
1328 #ifdef CONFIG_SPARC_LEON
1329 #include "ehci-grlib.c"
1330 #endif
1331 
1332 static struct platform_driver * const platform_drivers[] = {
1333 #ifdef CONFIG_USB_EHCI_SH
1334     &ehci_hcd_sh_driver,
1335 #endif
1336 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1337     &ehci_hcd_ppc_of_driver,
1338 #endif
1339 #ifdef CONFIG_XPS_USB_HCD_XILINX
1340     &ehci_hcd_xilinx_of_driver,
1341 #endif
1342 #ifdef CONFIG_SPARC_LEON
1343     &ehci_grlib_driver,
1344 #endif
1345 };
1346 
1347 static int __init ehci_hcd_init(void)
1348 {
1349     int retval = 0;
1350 
1351     if (usb_disabled())
1352         return -ENODEV;
1353 
1354     printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1355     set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1356     if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1357             test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1358         printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1359                 " before uhci_hcd and ohci_hcd, not after\n");
1360 
1361     pr_debug("%s: block sizes: qh %zd qtd %zd itd %zd sitd %zd\n",
1362          hcd_name,
1363          sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1364          sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1365 
1366 #ifdef CONFIG_DYNAMIC_DEBUG
1367     ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1368 #endif
1369 
1370     retval = platform_register_drivers(platform_drivers, ARRAY_SIZE(platform_drivers));
1371     if (retval < 0)
1372         goto clean0;
1373 
1374 #ifdef CONFIG_PPC_PS3
1375     retval = ps3_ehci_driver_register(&ps3_ehci_driver);
1376     if (retval < 0)
1377         goto clean1;
1378 #endif
1379 
1380     return 0;
1381 
1382 #ifdef CONFIG_PPC_PS3
1383 clean1:
1384 #endif
1385     platform_unregister_drivers(platform_drivers, ARRAY_SIZE(platform_drivers));
1386 clean0:
1387 #ifdef CONFIG_DYNAMIC_DEBUG
1388     debugfs_remove(ehci_debug_root);
1389     ehci_debug_root = NULL;
1390 #endif
1391     clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1392     return retval;
1393 }
1394 module_init(ehci_hcd_init);
1395 
1396 static void __exit ehci_hcd_cleanup(void)
1397 {
1398 #ifdef CONFIG_PPC_PS3
1399     ps3_ehci_driver_unregister(&ps3_ehci_driver);
1400 #endif
1401     platform_unregister_drivers(platform_drivers, ARRAY_SIZE(platform_drivers));
1402 #ifdef CONFIG_DYNAMIC_DEBUG
1403     debugfs_remove(ehci_debug_root);
1404 #endif
1405     clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1406 }
1407 module_exit(ehci_hcd_cleanup);
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