usb/host/ehci-fsl.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc.
0003  * Copyright (c) 2005 MontaVista Software
0004  */
0005 #ifndef _EHCI_FSL_H
0006 #define _EHCI_FSL_H
0007
0008 /* offsets for the non-ehci registers in the FSL SOC USB controller */
0009 #define FSL_SOC_USB_SBUSCFG 0x90
0010 #define SBUSCFG_INCR8       0x02    /* INCR8, specified */
0011 #define FSL_SOC_USB_ULPIVP  0x170
0012 #define FSL_SOC_USB_PORTSC1 0x184
0013 #define PORT_PTS_MSK        (3<<30)
0014 #define PORT_PTS_UTMI       (0<<30)
0015 #define PORT_PTS_ULPI       (2<<30)
0016 #define PORT_PTS_SERIAL     (3<<30)
0017 #define PORT_PTS_PTW        (1<<28)
0018 #define FSL_SOC_USB_PORTSC2 0x188
0019 #define FSL_SOC_USB_USBMODE 0x1a8
0020 #define USBMODE_CM_MASK     (3 << 0)    /* controller mode mask */
0021 #define USBMODE_CM_HOST     (3 << 0)    /* controller mode: host */
0022 #define USBMODE_ES      (1 << 2)    /* (Big) Endian Select */
0023
0024 #define FSL_SOC_USB_USBGENCTRL  0x200
0025 #define USBGENCTRL_PPP      (1 << 3)
0026 #define USBGENCTRL_PFP      (1 << 2)
0027 #define FSL_SOC_USB_ISIPHYCTRL  0x204
0028 #define ISIPHYCTRL_PXE      (1)
0029 #define ISIPHYCTRL_PHYE     (1 << 4)
0030
0031 #define FSL_SOC_USB_SNOOP1  0x400   /* NOTE: big-endian */
0032 #define FSL_SOC_USB_SNOOP2  0x404   /* NOTE: big-endian */
0033 #define FSL_SOC_USB_AGECNTTHRSH 0x408   /* NOTE: big-endian */
0034 #define FSL_SOC_USB_PRICTRL 0x40c   /* NOTE: big-endian */
0035 #define FSL_SOC_USB_SICTRL  0x410   /* NOTE: big-endian */
0036 #define FSL_SOC_USB_CTRL    0x500   /* NOTE: big-endian */
0037 #define CTRL_UTMI_PHY_EN    (1<<9)
0038 #define CTRL_PHY_CLK_VALID  (1 << 17)
0039 #define SNOOP_SIZE_2GB      0x1e
0040
0041 /* control Register Bit Masks */
0042 #define CONTROL_REGISTER_W1C_MASK       0x00020000  /* W1C: PHY_CLK_VALID */
0043 #define ULPI_INT_EN             (1<<0)
0044 #define WU_INT_EN               (1<<1)
0045 #define USB_CTRL_USB_EN         (1<<2)
0046 #define LINE_STATE_FILTER__EN   (1<<3)
0047 #define KEEP_OTG_ON             (1<<4)
0048 #define OTG_PORT                (1<<5)
0049 #define PLL_RESET               (1<<8)
0050 #define UTMI_PHY_EN             (1<<9)
0051 #define ULPI_PHY_CLK_SEL        (1<<10)
0052 #define PHY_CLK_VALID       (1<<17)
0053
0054 /* Retry count for checking UTMI PHY CLK validity */
0055 #define UTMI_PHY_CLK_VALID_CHK_RETRY 5
0056 #endif              /* _EHCI_FSL_H */