Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright 2005-2009 MontaVista Software, Inc.
0004  * Copyright 2008,2012,2015      Freescale Semiconductor, Inc.
0005  *
0006  * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
0007  * by Hunter Wu.
0008  * Power Management support by Dave Liu <daveliu@freescale.com>,
0009  * Jerry Huang <Chang-Ming.Huang@freescale.com> and
0010  * Anton Vorontsov <avorontsov@ru.mvista.com>.
0011  */
0012 
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/types.h>
0016 #include <linux/delay.h>
0017 #include <linux/pm.h>
0018 #include <linux/err.h>
0019 #include <linux/usb.h>
0020 #include <linux/usb/ehci_def.h>
0021 #include <linux/usb/hcd.h>
0022 #include <linux/usb/otg.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/fsl_devices.h>
0025 #include <linux/of_platform.h>
0026 #include <linux/io.h>
0027 
0028 #include "ehci.h"
0029 #include "ehci-fsl.h"
0030 
0031 #define DRIVER_DESC "Freescale EHCI Host controller driver"
0032 #define DRV_NAME "ehci-fsl"
0033 
0034 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
0035 
0036 /* configure so an HC device and id are always provided */
0037 /* always called with process context; sleeping is OK */
0038 
0039 /*
0040  * fsl_ehci_drv_probe - initialize FSL-based HCDs
0041  * @pdev: USB Host Controller being probed
0042  *
0043  * Context: task context, might sleep
0044  *
0045  * Allocates basic resources for this USB host controller.
0046  */
0047 static int fsl_ehci_drv_probe(struct platform_device *pdev)
0048 {
0049     struct fsl_usb2_platform_data *pdata;
0050     struct usb_hcd *hcd;
0051     struct resource *res;
0052     int irq;
0053     int retval;
0054     u32 tmp;
0055 
0056     pr_debug("initializing FSL-SOC USB Controller\n");
0057 
0058     /* Need platform data for setup */
0059     pdata = dev_get_platdata(&pdev->dev);
0060     if (!pdata) {
0061         dev_err(&pdev->dev,
0062             "No platform data for %s.\n", dev_name(&pdev->dev));
0063         return -ENODEV;
0064     }
0065 
0066     /*
0067      * This is a host mode driver, verify that we're supposed to be
0068      * in host mode.
0069      */
0070     if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
0071           (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
0072           (pdata->operating_mode == FSL_USB2_DR_OTG))) {
0073         dev_err(&pdev->dev,
0074             "Non Host Mode configured for %s. Wrong driver linked.\n",
0075             dev_name(&pdev->dev));
0076         return -ENODEV;
0077     }
0078 
0079     irq = platform_get_irq(pdev, 0);
0080     if (irq < 0)
0081         return irq;
0082 
0083     hcd = __usb_create_hcd(&fsl_ehci_hc_driver, pdev->dev.parent,
0084                    &pdev->dev, dev_name(&pdev->dev), NULL);
0085     if (!hcd) {
0086         retval = -ENOMEM;
0087         goto err1;
0088     }
0089 
0090     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0091     hcd->regs = devm_ioremap_resource(&pdev->dev, res);
0092     if (IS_ERR(hcd->regs)) {
0093         retval = PTR_ERR(hcd->regs);
0094         goto err2;
0095     }
0096 
0097     hcd->rsrc_start = res->start;
0098     hcd->rsrc_len = resource_size(res);
0099 
0100     pdata->regs = hcd->regs;
0101 
0102     if (pdata->power_budget)
0103         hcd->power_budget = pdata->power_budget;
0104 
0105     /*
0106      * do platform specific init: check the clock, grab/config pins, etc.
0107      */
0108     if (pdata->init && pdata->init(pdev)) {
0109         retval = -ENODEV;
0110         goto err2;
0111     }
0112 
0113     /* Enable USB controller, 83xx or 8536 */
0114     if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) {
0115         tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
0116         tmp &= ~CONTROL_REGISTER_W1C_MASK;
0117         tmp |= 0x4;
0118         iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
0119     }
0120 
0121     /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
0122     if (pdata->controller_ver == FSL_USB_VER_2_5 &&
0123         pdata->phy_mode == FSL_USB2_PHY_ULPI)
0124         iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
0125 
0126     /*
0127      * Enable UTMI phy and program PTS field in UTMI mode before asserting
0128      * controller reset for USB Controller version 2.5
0129      */
0130     if (pdata->has_fsl_erratum_a007792) {
0131         tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
0132         tmp &= ~CONTROL_REGISTER_W1C_MASK;
0133         tmp |= CTRL_UTMI_PHY_EN;
0134         iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
0135 
0136         writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
0137     }
0138 
0139     /* Don't need to set host mode here. It will be done by tdi_reset() */
0140 
0141     retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
0142     if (retval != 0)
0143         goto err2;
0144     device_wakeup_enable(hcd->self.controller);
0145 
0146 #ifdef CONFIG_USB_OTG
0147     if (pdata->operating_mode == FSL_USB2_DR_OTG) {
0148         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
0149 
0150         hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
0151         dev_dbg(&pdev->dev, "hcd=0x%p  ehci=0x%p, phy=0x%p\n",
0152             hcd, ehci, hcd->usb_phy);
0153 
0154         if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
0155             retval = otg_set_host(hcd->usb_phy->otg,
0156                           &ehci_to_hcd(ehci)->self);
0157             if (retval) {
0158                 usb_put_phy(hcd->usb_phy);
0159                 goto err2;
0160             }
0161         } else {
0162             dev_err(&pdev->dev, "can't find phy\n");
0163             retval = -ENODEV;
0164             goto err2;
0165         }
0166 
0167         hcd->skip_phy_initialization = 1;
0168     }
0169 #endif
0170     return retval;
0171 
0172       err2:
0173     usb_put_hcd(hcd);
0174       err1:
0175     dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
0176     if (pdata->exit)
0177         pdata->exit(pdev);
0178     return retval;
0179 }
0180 
0181 static bool usb_phy_clk_valid(struct usb_hcd *hcd)
0182 {
0183     void __iomem *non_ehci = hcd->regs;
0184     bool ret = true;
0185 
0186     if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
0187         ret = false;
0188 
0189     return ret;
0190 }
0191 
0192 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
0193                    enum fsl_usb2_phy_modes phy_mode,
0194                    unsigned int port_offset)
0195 {
0196     u32 portsc, tmp;
0197     struct ehci_hcd *ehci = hcd_to_ehci(hcd);
0198     void __iomem *non_ehci = hcd->regs;
0199     struct device *dev = hcd->self.controller;
0200     struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
0201 
0202     if (pdata->controller_ver < 0) {
0203         dev_warn(hcd->self.controller, "Could not get controller version\n");
0204         return -ENODEV;
0205     }
0206 
0207     portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
0208     portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
0209 
0210     switch (phy_mode) {
0211     case FSL_USB2_PHY_ULPI:
0212         if (pdata->have_sysif_regs && pdata->controller_ver) {
0213             /* controller version 1.6 or above */
0214             /* turn off UTMI PHY first */
0215             tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
0216             tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
0217             iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
0218 
0219             /* then turn on ULPI and enable USB controller */
0220             tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
0221             tmp &= ~CONTROL_REGISTER_W1C_MASK;
0222             tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN;
0223             iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
0224         }
0225         portsc |= PORT_PTS_ULPI;
0226         break;
0227     case FSL_USB2_PHY_SERIAL:
0228         portsc |= PORT_PTS_SERIAL;
0229         break;
0230     case FSL_USB2_PHY_UTMI_WIDE:
0231         portsc |= PORT_PTS_PTW;
0232         fallthrough;
0233     case FSL_USB2_PHY_UTMI:
0234         /* Presence of this node "has_fsl_erratum_a006918"
0235          * in device-tree is used to stop USB controller
0236          * initialization in Linux
0237          */
0238         if (pdata->has_fsl_erratum_a006918) {
0239             dev_warn(dev, "USB PHY clock invalid\n");
0240             return -EINVAL;
0241         }
0242         fallthrough;
0243     case FSL_USB2_PHY_UTMI_DUAL:
0244         /* PHY_CLK_VALID bit is de-featured from all controller
0245          * versions below 2.4 and is to be checked only for
0246          * internal UTMI phy
0247          */
0248         if (pdata->controller_ver > FSL_USB_VER_2_4 &&
0249             pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
0250             dev_err(dev, "USB PHY clock invalid\n");
0251             return -EINVAL;
0252         }
0253 
0254         if (pdata->have_sysif_regs && pdata->controller_ver) {
0255             /* controller version 1.6 or above */
0256             tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
0257             tmp &= ~CONTROL_REGISTER_W1C_MASK;
0258             tmp |= UTMI_PHY_EN;
0259             iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
0260 
0261             mdelay(FSL_UTMI_PHY_DLY);  /* Delay for UTMI PHY CLK to
0262                         become stable - 10ms*/
0263         }
0264         /* enable UTMI PHY */
0265         if (pdata->have_sysif_regs) {
0266             tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
0267             tmp &= ~CONTROL_REGISTER_W1C_MASK;
0268             tmp |= CTRL_UTMI_PHY_EN;
0269             iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
0270         }
0271         portsc |= PORT_PTS_UTMI;
0272         break;
0273     case FSL_USB2_PHY_NONE:
0274         break;
0275     }
0276 
0277     if (pdata->have_sysif_regs &&
0278         pdata->controller_ver > FSL_USB_VER_1_6 &&
0279         !usb_phy_clk_valid(hcd)) {
0280         dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
0281         return -EINVAL;
0282     }
0283 
0284     ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
0285 
0286     if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) {
0287         tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
0288         tmp &= ~CONTROL_REGISTER_W1C_MASK;
0289         tmp |= USB_CTRL_USB_EN;
0290         iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
0291     }
0292 
0293     return 0;
0294 }
0295 
0296 static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
0297 {
0298     struct usb_hcd *hcd = ehci_to_hcd(ehci);
0299     struct fsl_usb2_platform_data *pdata;
0300     void __iomem *non_ehci = hcd->regs;
0301 
0302     pdata = dev_get_platdata(hcd->self.controller);
0303 
0304     if (pdata->have_sysif_regs) {
0305         /*
0306         * Turn on cache snooping hardware, since some PowerPC platforms
0307         * wholly rely on hardware to deal with cache coherent
0308         */
0309 
0310         /* Setup Snooping for all the 4GB space */
0311         /* SNOOP1 starts from 0x0, size 2G */
0312         iowrite32be(0x0 | SNOOP_SIZE_2GB,
0313                 non_ehci + FSL_SOC_USB_SNOOP1);
0314         /* SNOOP2 starts from 0x80000000, size 2G */
0315         iowrite32be(0x80000000 | SNOOP_SIZE_2GB,
0316                 non_ehci + FSL_SOC_USB_SNOOP2);
0317     }
0318 
0319     /* Deal with USB erratum A-005275 */
0320     if (pdata->has_fsl_erratum_a005275 == 1)
0321         ehci->has_fsl_hs_errata = 1;
0322 
0323     if (pdata->has_fsl_erratum_a005697 == 1)
0324         ehci->has_fsl_susp_errata = 1;
0325 
0326     if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
0327             (pdata->operating_mode == FSL_USB2_DR_OTG))
0328         if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
0329             return -EINVAL;
0330 
0331     if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
0332 
0333         /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
0334         if (pdata->has_fsl_erratum_14 == 1)
0335             ehci->has_fsl_port_bug = 1;
0336 
0337         if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
0338             if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
0339                 return -EINVAL;
0340 
0341         if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
0342             if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
0343                 return -EINVAL;
0344     }
0345 
0346     if (pdata->have_sysif_regs) {
0347 #ifdef CONFIG_FSL_SOC_BOOKE
0348         iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL);
0349         iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
0350 #else
0351         iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL);
0352         iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
0353 #endif
0354         iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL);
0355     }
0356 
0357     return 0;
0358 }
0359 
0360 /* called after powerup, by probe or system-pm "wakeup" */
0361 static int ehci_fsl_reinit(struct ehci_hcd *ehci)
0362 {
0363     if (ehci_fsl_usb_setup(ehci))
0364         return -EINVAL;
0365 
0366     return 0;
0367 }
0368 
0369 /* called during probe() after chip reset completes */
0370 static int ehci_fsl_setup(struct usb_hcd *hcd)
0371 {
0372     struct ehci_hcd *ehci = hcd_to_ehci(hcd);
0373     int retval;
0374     struct fsl_usb2_platform_data *pdata;
0375     struct device *dev;
0376 
0377     dev = hcd->self.controller;
0378     pdata = dev_get_platdata(hcd->self.controller);
0379     ehci->big_endian_desc = pdata->big_endian_desc;
0380     ehci->big_endian_mmio = pdata->big_endian_mmio;
0381 
0382     /* EHCI registers start at offset 0x100 */
0383     ehci->caps = hcd->regs + 0x100;
0384 
0385 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_85xx)
0386     /*
0387      * Deal with MPC834X/85XX that need port power to be cycled
0388      * after the power fault condition is removed. Otherwise the
0389      * state machine does not reflect PORTSC[CSC] correctly.
0390      */
0391     ehci->need_oc_pp_cycle = 1;
0392 #endif
0393 
0394     hcd->has_tt = 1;
0395 
0396     retval = ehci_setup(hcd);
0397     if (retval)
0398         return retval;
0399 
0400     if (of_device_is_compatible(dev->parent->of_node,
0401                     "fsl,mpc5121-usb2-dr")) {
0402         /*
0403          * set SBUSCFG:AHBBRST so that control msgs don't
0404          * fail when doing heavy PATA writes.
0405          */
0406         ehci_writel(ehci, SBUSCFG_INCR8,
0407                 hcd->regs + FSL_SOC_USB_SBUSCFG);
0408     }
0409 
0410     retval = ehci_fsl_reinit(ehci);
0411     return retval;
0412 }
0413 
0414 struct ehci_fsl {
0415     struct ehci_hcd ehci;
0416 
0417 #ifdef CONFIG_PM
0418     /* Saved USB PHY settings, need to restore after deep sleep. */
0419     u32 usb_ctrl;
0420 #endif
0421 };
0422 
0423 #ifdef CONFIG_PM
0424 
0425 #ifdef CONFIG_PPC_MPC512x
0426 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
0427 {
0428     struct usb_hcd *hcd = dev_get_drvdata(dev);
0429     struct ehci_hcd *ehci = hcd_to_ehci(hcd);
0430     struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
0431     u32 tmp;
0432 
0433 #ifdef CONFIG_DYNAMIC_DEBUG
0434     u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
0435     mode &= USBMODE_CM_MASK;
0436     tmp = ehci_readl(ehci, hcd->regs + 0x140);  /* usbcmd */
0437 
0438     dev_dbg(dev, "suspend=%d already_suspended=%d "
0439         "mode=%d  usbcmd %08x\n", pdata->suspended,
0440         pdata->already_suspended, mode, tmp);
0441 #endif
0442 
0443     /*
0444      * If the controller is already suspended, then this must be a
0445      * PM suspend.  Remember this fact, so that we will leave the
0446      * controller suspended at PM resume time.
0447      */
0448     if (pdata->suspended) {
0449         dev_dbg(dev, "already suspended, leaving early\n");
0450         pdata->already_suspended = 1;
0451         return 0;
0452     }
0453 
0454     dev_dbg(dev, "suspending...\n");
0455 
0456     ehci->rh_state = EHCI_RH_SUSPENDED;
0457     dev->power.power_state = PMSG_SUSPEND;
0458 
0459     /* ignore non-host interrupts */
0460     clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
0461 
0462     /* stop the controller */
0463     tmp = ehci_readl(ehci, &ehci->regs->command);
0464     tmp &= ~CMD_RUN;
0465     ehci_writel(ehci, tmp, &ehci->regs->command);
0466 
0467     /* save EHCI registers */
0468     pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
0469     pdata->pm_command &= ~CMD_RUN;
0470     pdata->pm_status  = ehci_readl(ehci, &ehci->regs->status);
0471     pdata->pm_intr_enable  = ehci_readl(ehci, &ehci->regs->intr_enable);
0472     pdata->pm_frame_index  = ehci_readl(ehci, &ehci->regs->frame_index);
0473     pdata->pm_segment  = ehci_readl(ehci, &ehci->regs->segment);
0474     pdata->pm_frame_list  = ehci_readl(ehci, &ehci->regs->frame_list);
0475     pdata->pm_async_next  = ehci_readl(ehci, &ehci->regs->async_next);
0476     pdata->pm_configured_flag  =
0477         ehci_readl(ehci, &ehci->regs->configured_flag);
0478     pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
0479     pdata->pm_usbgenctrl = ehci_readl(ehci,
0480                       hcd->regs + FSL_SOC_USB_USBGENCTRL);
0481 
0482     /* clear the W1C bits */
0483     pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
0484 
0485     pdata->suspended = 1;
0486 
0487     /* clear PP to cut power to the port */
0488     tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
0489     tmp &= ~PORT_POWER;
0490     ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
0491 
0492     return 0;
0493 }
0494 
0495 static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
0496 {
0497     struct usb_hcd *hcd = dev_get_drvdata(dev);
0498     struct ehci_hcd *ehci = hcd_to_ehci(hcd);
0499     struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
0500     u32 tmp;
0501 
0502     dev_dbg(dev, "suspend=%d already_suspended=%d\n",
0503         pdata->suspended, pdata->already_suspended);
0504 
0505     /*
0506      * If the controller was already suspended at suspend time,
0507      * then don't resume it now.
0508      */
0509     if (pdata->already_suspended) {
0510         dev_dbg(dev, "already suspended, leaving early\n");
0511         pdata->already_suspended = 0;
0512         return 0;
0513     }
0514 
0515     if (!pdata->suspended) {
0516         dev_dbg(dev, "not suspended, leaving early\n");
0517         return 0;
0518     }
0519 
0520     pdata->suspended = 0;
0521 
0522     dev_dbg(dev, "resuming...\n");
0523 
0524     /* set host mode */
0525     tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
0526     ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
0527 
0528     ehci_writel(ehci, pdata->pm_usbgenctrl,
0529             hcd->regs + FSL_SOC_USB_USBGENCTRL);
0530     ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
0531             hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
0532 
0533     ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
0534 
0535     /* restore EHCI registers */
0536     ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
0537     ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
0538     ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
0539     ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
0540     ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
0541     ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
0542     ehci_writel(ehci, pdata->pm_configured_flag,
0543             &ehci->regs->configured_flag);
0544     ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
0545 
0546     set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
0547     ehci->rh_state = EHCI_RH_RUNNING;
0548     dev->power.power_state = PMSG_ON;
0549 
0550     tmp = ehci_readl(ehci, &ehci->regs->command);
0551     tmp |= CMD_RUN;
0552     ehci_writel(ehci, tmp, &ehci->regs->command);
0553 
0554     usb_hcd_resume_root_hub(hcd);
0555 
0556     return 0;
0557 }
0558 #else
0559 static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
0560 {
0561     return 0;
0562 }
0563 
0564 static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
0565 {
0566     return 0;
0567 }
0568 #endif /* CONFIG_PPC_MPC512x */
0569 
0570 static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
0571 {
0572     struct ehci_hcd *ehci = hcd_to_ehci(hcd);
0573 
0574     return container_of(ehci, struct ehci_fsl, ehci);
0575 }
0576 
0577 static int ehci_fsl_drv_suspend(struct device *dev)
0578 {
0579     struct usb_hcd *hcd = dev_get_drvdata(dev);
0580     struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
0581     void __iomem *non_ehci = hcd->regs;
0582 
0583     if (of_device_is_compatible(dev->parent->of_node,
0584                     "fsl,mpc5121-usb2-dr")) {
0585         return ehci_fsl_mpc512x_drv_suspend(dev);
0586     }
0587 
0588     ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
0589             device_may_wakeup(dev));
0590     if (!fsl_deep_sleep())
0591         return 0;
0592 
0593     ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
0594     return 0;
0595 }
0596 
0597 static int ehci_fsl_drv_resume(struct device *dev)
0598 {
0599     struct usb_hcd *hcd = dev_get_drvdata(dev);
0600     struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
0601     struct ehci_hcd *ehci = hcd_to_ehci(hcd);
0602     void __iomem *non_ehci = hcd->regs;
0603 
0604     if (of_device_is_compatible(dev->parent->of_node,
0605                     "fsl,mpc5121-usb2-dr")) {
0606         return ehci_fsl_mpc512x_drv_resume(dev);
0607     }
0608 
0609     ehci_prepare_ports_for_controller_resume(ehci);
0610     if (!fsl_deep_sleep())
0611         return 0;
0612 
0613     usb_root_hub_lost_power(hcd->self.root_hub);
0614 
0615     /* Restore USB PHY settings and enable the controller. */
0616     iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
0617 
0618     ehci_reset(ehci);
0619     ehci_fsl_reinit(ehci);
0620 
0621     return 0;
0622 }
0623 
0624 static int ehci_fsl_drv_restore(struct device *dev)
0625 {
0626     struct usb_hcd *hcd = dev_get_drvdata(dev);
0627 
0628     usb_root_hub_lost_power(hcd->self.root_hub);
0629     return 0;
0630 }
0631 
0632 static const struct dev_pm_ops ehci_fsl_pm_ops = {
0633     .suspend = ehci_fsl_drv_suspend,
0634     .resume = ehci_fsl_drv_resume,
0635     .restore = ehci_fsl_drv_restore,
0636 };
0637 
0638 #define EHCI_FSL_PM_OPS     (&ehci_fsl_pm_ops)
0639 #else
0640 #define EHCI_FSL_PM_OPS     NULL
0641 #endif /* CONFIG_PM */
0642 
0643 #ifdef CONFIG_USB_OTG
0644 static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
0645 {
0646     struct ehci_hcd *ehci = hcd_to_ehci(hcd);
0647     u32 status;
0648 
0649     if (!port)
0650         return -EINVAL;
0651 
0652     port--;
0653 
0654     /* start port reset before HNP protocol time out */
0655     status = readl(&ehci->regs->port_status[port]);
0656     if (!(status & PORT_CONNECT))
0657         return -ENODEV;
0658 
0659     /* hub_wq will finish the reset later */
0660     if (ehci_is_TDI(ehci)) {
0661         writel(PORT_RESET |
0662                (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
0663                &ehci->regs->port_status[port]);
0664     } else {
0665         writel(PORT_RESET, &ehci->regs->port_status[port]);
0666     }
0667 
0668     return 0;
0669 }
0670 #else
0671 #define ehci_start_port_reset   NULL
0672 #endif /* CONFIG_USB_OTG */
0673 
0674 static const struct ehci_driver_overrides ehci_fsl_overrides __initconst = {
0675     .extra_priv_size = sizeof(struct ehci_fsl),
0676     .reset = ehci_fsl_setup,
0677 };
0678 
0679 /**
0680  * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs
0681  * @pdev: USB Host Controller being removed
0682  *
0683  * Context: task context, might sleep
0684  *
0685  * Reverses the effect of usb_hcd_fsl_probe().
0686  */
0687 static int fsl_ehci_drv_remove(struct platform_device *pdev)
0688 {
0689     struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
0690     struct usb_hcd *hcd = platform_get_drvdata(pdev);
0691 
0692     if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
0693         otg_set_host(hcd->usb_phy->otg, NULL);
0694         usb_put_phy(hcd->usb_phy);
0695     }
0696 
0697     usb_remove_hcd(hcd);
0698 
0699     /*
0700      * do platform specific un-initialization:
0701      * release iomux pins, disable clock, etc.
0702      */
0703     if (pdata->exit)
0704         pdata->exit(pdev);
0705     usb_put_hcd(hcd);
0706 
0707     return 0;
0708 }
0709 
0710 static struct platform_driver ehci_fsl_driver = {
0711     .probe = fsl_ehci_drv_probe,
0712     .remove = fsl_ehci_drv_remove,
0713     .shutdown = usb_hcd_platform_shutdown,
0714     .driver = {
0715         .name = "fsl-ehci",
0716         .pm = EHCI_FSL_PM_OPS,
0717     },
0718 };
0719 
0720 static int __init ehci_fsl_init(void)
0721 {
0722     if (usb_disabled())
0723         return -ENODEV;
0724 
0725     pr_info(DRV_NAME ": " DRIVER_DESC "\n");
0726 
0727     ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides);
0728 
0729     fsl_ehci_hc_driver.product_desc =
0730             "Freescale On-Chip EHCI Host Controller";
0731     fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset;
0732 
0733 
0734     return platform_driver_register(&ehci_fsl_driver);
0735 }
0736 module_init(ehci_fsl_init);
0737 
0738 static void __exit ehci_fsl_cleanup(void)
0739 {
0740     platform_driver_unregister(&ehci_fsl_driver);
0741 }
0742 module_exit(ehci_fsl_cleanup);
0743 
0744 MODULE_DESCRIPTION(DRIVER_DESC);
0745 MODULE_LICENSE("GPL");
0746 MODULE_ALIAS("platform:" DRV_NAME);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!