usb/early/xhci-dbc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * xhci-dbc.h - xHCI debug capability early driver
0004  *
0005  * Copyright (C) 2016 Intel Corporation
0006  *
0007  * Author: Lu Baolu <baolu.lu@linux.intel.com>
0008  */
0009
0010 #ifndef __LINUX_XHCI_DBC_H
0011 #define __LINUX_XHCI_DBC_H
0012
0013 #include <linux/types.h>
0014 #include <linux/usb/ch9.h>
0015
0016 /*
0017  * xHCI Debug Capability Register interfaces:
0018  */
0019 struct xdbc_regs {
0020     __le32  capability;
0021     __le32  doorbell;
0022     __le32  ersts;      /* Event Ring Segment Table Size*/
0023     __le32  __reserved_0;   /* 0c~0f reserved bits */
0024     __le64  erstba;     /* Event Ring Segment Table Base Address */
0025     __le64  erdp;       /* Event Ring Dequeue Pointer */
0026     __le32  control;
0027     __le32  status;
0028     __le32  portsc;     /* Port status and control */
0029     __le32  __reserved_1;   /* 2b~28 reserved bits */
0030     __le64  dccp;       /* Debug Capability Context Pointer */
0031     __le32  devinfo1;   /* Device Descriptor Info Register 1 */
0032     __le32  devinfo2;   /* Device Descriptor Info Register 2 */
0033 };
0034
0035 #define DEBUG_MAX_BURST(p)  (((p) >> 16) & 0xff)
0036
0037 #define CTRL_DBC_RUN        BIT(0)
0038 #define CTRL_PORT_ENABLE    BIT(1)
0039 #define CTRL_HALT_OUT_TR    BIT(2)
0040 #define CTRL_HALT_IN_TR     BIT(3)
0041 #define CTRL_DBC_RUN_CHANGE BIT(4)
0042 #define CTRL_DBC_ENABLE     BIT(31)
0043
0044 #define DCST_DEBUG_PORT(p)  (((p) >> 24) & 0xff)
0045
0046 #define PORTSC_CONN_STATUS  BIT(0)
0047 #define PORTSC_CONN_CHANGE  BIT(17)
0048 #define PORTSC_RESET_CHANGE BIT(21)
0049 #define PORTSC_LINK_CHANGE  BIT(22)
0050 #define PORTSC_CONFIG_CHANGE    BIT(23)
0051
0052 /*
0053  * xHCI Debug Capability data structures:
0054  */
0055 struct xdbc_trb {
0056     __le32 field[4];
0057 };
0058
0059 struct xdbc_erst_entry {
0060     __le64  seg_addr;
0061     __le32  seg_size;
0062     __le32  __reserved_0;
0063 };
0064
0065 struct xdbc_info_context {
0066     __le64  string0;
0067     __le64  manufacturer;
0068     __le64  product;
0069     __le64  serial;
0070     __le32  length;
0071     __le32  __reserved_0[7];
0072 };
0073
0074 struct xdbc_ep_context {
0075     __le32  ep_info1;
0076     __le32  ep_info2;
0077     __le64  deq;
0078     __le32  tx_info;
0079     __le32  __reserved_0[11];
0080 };
0081
0082 struct xdbc_context {
0083     struct xdbc_info_context    info;
0084     struct xdbc_ep_context      out;
0085     struct xdbc_ep_context      in;
0086 };
0087
0088 #define XDBC_INFO_CONTEXT_SIZE      48
0089 #define XDBC_MAX_STRING_LENGTH      64
0090 #define XDBC_STRING_MANUFACTURER    "Linux Foundation"
0091 #define XDBC_STRING_PRODUCT     "Linux USB GDB Target"
0092 #define XDBC_STRING_SERIAL      "0001"
0093
0094 struct xdbc_strings {
0095     char    string0[XDBC_MAX_STRING_LENGTH];
0096     char    manufacturer[XDBC_MAX_STRING_LENGTH];
0097     char    product[XDBC_MAX_STRING_LENGTH];
0098     char    serial[XDBC_MAX_STRING_LENGTH];
0099 };
0100
0101 #define XDBC_PROTOCOL       1   /* GNU Remote Debug Command Set */
0102 #define XDBC_VENDOR_ID      0x1d6b  /* Linux Foundation 0x1d6b */
0103 #define XDBC_PRODUCT_ID     0x0011  /* __le16 idProduct; device 0011 */
0104 #define XDBC_DEVICE_REV     0x0010  /* 0.10 */
0105
0106 /*
0107  * xHCI Debug Capability software state structures:
0108  */
0109 struct xdbc_segment {
0110     struct xdbc_trb     *trbs;
0111     dma_addr_t      dma;
0112 };
0113
0114 #define XDBC_TRBS_PER_SEGMENT   256
0115
0116 struct xdbc_ring {
0117     struct xdbc_segment *segment;
0118     struct xdbc_trb     *enqueue;
0119     struct xdbc_trb     *dequeue;
0120     u32         cycle_state;
0121 };
0122
0123 /*
0124  * These are the "Endpoint ID" (also known as "Context Index") values for the
0125  * OUT Transfer Ring and the IN Transfer Ring of a Debug Capability Context data
0126  * structure.
0127  * According to the "eXtensible Host Controller Interface for Universal Serial
0128  * Bus (xHCI)" specification, section "7.6.3.2 Endpoint Contexts and Transfer
0129  * Rings", these should be 0 and 1, and those are the values AMD machines give
0130  * you; but Intel machines seem to use the formula from section "4.5.1 Device
0131  * Context Index", which is supposed to be used for the Device Context only.
0132  * Luckily the values from Intel don't overlap with those from AMD, so we can
0133  * just test for both.
0134  */
0135 #define XDBC_EPID_OUT       0
0136 #define XDBC_EPID_IN        1
0137 #define XDBC_EPID_OUT_INTEL 2
0138 #define XDBC_EPID_IN_INTEL  3
0139
0140 struct xdbc_state {
0141     u16         vendor;
0142     u16         device;
0143     u32         bus;
0144     u32         dev;
0145     u32         func;
0146     void __iomem        *xhci_base;
0147     u64         xhci_start;
0148     size_t          xhci_length;
0149     int         port_number;
0150
0151     /* DbC register base */
0152     struct xdbc_regs __iomem *xdbc_reg;
0153
0154     /* DbC table page */
0155     dma_addr_t      table_dma;
0156     void            *table_base;
0157
0158     /* event ring segment table */
0159     dma_addr_t      erst_dma;
0160     size_t          erst_size;
0161     void            *erst_base;
0162
0163     /* event ring segments */
0164     struct xdbc_ring    evt_ring;
0165     struct xdbc_segment evt_seg;
0166
0167     /* debug capability contexts */
0168     dma_addr_t      dbcc_dma;
0169     size_t          dbcc_size;
0170     void            *dbcc_base;
0171
0172     /* descriptor strings */
0173     dma_addr_t      string_dma;
0174     size_t          string_size;
0175     void            *string_base;
0176
0177     /* bulk OUT endpoint */
0178     struct xdbc_ring    out_ring;
0179     struct xdbc_segment out_seg;
0180     void            *out_buf;
0181     dma_addr_t      out_dma;
0182
0183     /* bulk IN endpoint */
0184     struct xdbc_ring    in_ring;
0185     struct xdbc_segment in_seg;
0186     void            *in_buf;
0187     dma_addr_t      in_dma;
0188
0189     u32         flags;
0190
0191     /* spinlock for early_xdbc_write() reentrancy */
0192     raw_spinlock_t      lock;
0193 };
0194
0195 #define XDBC_PCI_MAX_BUSES  256
0196 #define XDBC_PCI_MAX_DEVICES    32
0197 #define XDBC_PCI_MAX_FUNCTION   8
0198
0199 #define XDBC_TABLE_ENTRY_SIZE   64
0200 #define XDBC_ERST_ENTRY_NUM 1
0201 #define XDBC_DBCC_ENTRY_NUM 3
0202 #define XDBC_STRING_ENTRY_NUM   4
0203
0204 /* Bits definitions for xdbc_state.flags: */
0205 #define XDBC_FLAGS_INITIALIZED  BIT(0)
0206 #define XDBC_FLAGS_IN_STALL BIT(1)
0207 #define XDBC_FLAGS_OUT_STALL    BIT(2)
0208 #define XDBC_FLAGS_IN_PROCESS   BIT(3)
0209 #define XDBC_FLAGS_OUT_PROCESS  BIT(4)
0210 #define XDBC_FLAGS_CONFIGURED   BIT(5)
0211
0212 #define XDBC_MAX_PACKET     1024
0213
0214 /* Door bell target: */
0215 #define OUT_EP_DOORBELL     0
0216 #define IN_EP_DOORBELL      1
0217 #define DOOR_BELL_TARGET(p) (((p) & 0xff) << 8)
0218
0219 #define xdbc_read64(regs)   xhci_read_64(NULL, (regs))
0220 #define xdbc_write64(val, regs) xhci_write_64(NULL, (val), (regs))
0221
0222 #endif /* __LINUX_XHCI_DBC_H */