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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Standalone EHCI usb debug driver
0004  *
0005  * Originally written by:
0006  *  Eric W. Biederman" <ebiederm@xmission.com> and
0007  *  Yinghai Lu <yhlu.kernel@gmail.com>
0008  *
0009  * Changes for early/late printk and HW errata:
0010  *  Jason Wessel <jason.wessel@windriver.com>
0011  *  Copyright (C) 2009 Wind River Systems, Inc.
0012  *
0013  */
0014 
0015 #include <linux/console.h>
0016 #include <linux/errno.h>
0017 #include <linux/init.h>
0018 #include <linux/iopoll.h>
0019 #include <linux/pci_regs.h>
0020 #include <linux/pci_ids.h>
0021 #include <linux/usb/ch9.h>
0022 #include <linux/usb/ehci_def.h>
0023 #include <linux/delay.h>
0024 #include <linux/serial_core.h>
0025 #include <linux/kgdb.h>
0026 #include <linux/kthread.h>
0027 #include <asm/io.h>
0028 #include <asm/pci-direct.h>
0029 #include <asm/fixmap.h>
0030 
0031 /* The code here is intended to talk directly to the EHCI debug port
0032  * and does not require that you have any kind of USB host controller
0033  * drivers or USB device drivers compiled into the kernel.
0034  *
0035  * If you make a change to anything in here, the following test cases
0036  * need to pass where a USB debug device works in the following
0037  * configurations.
0038  *
0039  * 1. boot args:  earlyprintk=dbgp
0040  *     o kernel compiled with # CONFIG_USB_EHCI_HCD is not set
0041  *     o kernel compiled with CONFIG_USB_EHCI_HCD=y
0042  * 2. boot args: earlyprintk=dbgp,keep
0043  *     o kernel compiled with # CONFIG_USB_EHCI_HCD is not set
0044  *     o kernel compiled with CONFIG_USB_EHCI_HCD=y
0045  * 3. boot args: earlyprintk=dbgp console=ttyUSB0
0046  *     o kernel has CONFIG_USB_EHCI_HCD=y and
0047  *       CONFIG_USB_SERIAL_DEBUG=y
0048  * 4. boot args: earlyprintk=vga,dbgp
0049  *     o kernel compiled with # CONFIG_USB_EHCI_HCD is not set
0050  *     o kernel compiled with CONFIG_USB_EHCI_HCD=y
0051  *
0052  * For the 4th configuration you can turn on or off the DBGP_DEBUG
0053  * such that you can debug the dbgp device's driver code.
0054  */
0055 
0056 static int dbgp_phys_port = 1;
0057 
0058 static struct ehci_caps __iomem *ehci_caps;
0059 static struct ehci_regs __iomem *ehci_regs;
0060 static struct ehci_dbg_port __iomem *ehci_debug;
0061 static int dbgp_not_safe; /* Cannot use debug device during ehci reset */
0062 static unsigned int dbgp_endpoint_out;
0063 static unsigned int dbgp_endpoint_in;
0064 
0065 struct ehci_dev {
0066     u32 bus;
0067     u32 slot;
0068     u32 func;
0069 };
0070 
0071 static struct ehci_dev ehci_dev;
0072 
0073 #define USB_DEBUG_DEVNUM 127
0074 
0075 #ifdef DBGP_DEBUG
0076 #define dbgp_printk printk
0077 static void dbgp_ehci_status(char *str)
0078 {
0079     if (!ehci_debug)
0080         return;
0081     dbgp_printk("dbgp: %s\n", str);
0082     dbgp_printk("  Debug control: %08x", readl(&ehci_debug->control));
0083     dbgp_printk("  ehci cmd     : %08x", readl(&ehci_regs->command));
0084     dbgp_printk("  ehci conf flg: %08x\n",
0085             readl(&ehci_regs->configured_flag));
0086     dbgp_printk("  ehci status  : %08x", readl(&ehci_regs->status));
0087     dbgp_printk("  ehci portsc  : %08x\n",
0088             readl(&ehci_regs->port_status[dbgp_phys_port - 1]));
0089 }
0090 #else
0091 static inline void dbgp_ehci_status(char *str) { }
0092 static inline void dbgp_printk(const char *fmt, ...) { }
0093 #endif
0094 
0095 static inline u32 dbgp_len_update(u32 x, u32 len)
0096 {
0097     return (x & ~0x0f) | (len & 0x0f);
0098 }
0099 
0100 #ifdef CONFIG_KGDB
0101 static struct kgdb_io kgdbdbgp_io_ops;
0102 #define dbgp_kgdb_mode (dbg_io_ops == &kgdbdbgp_io_ops)
0103 #else
0104 #define dbgp_kgdb_mode (0)
0105 #endif
0106 
0107 /* Local version of HC_LENGTH macro as ehci struct is not available here */
0108 #define EARLY_HC_LENGTH(p)  (0x00ff & (p)) /* bits 7 : 0 */
0109 
0110 /*
0111  * USB Packet IDs (PIDs)
0112  */
0113 
0114 /* token */
0115 #define USB_PID_OUT     0xe1
0116 #define USB_PID_IN      0x69
0117 #define USB_PID_SOF     0xa5
0118 #define USB_PID_SETUP       0x2d
0119 /* handshake */
0120 #define USB_PID_ACK     0xd2
0121 #define USB_PID_NAK     0x5a
0122 #define USB_PID_STALL       0x1e
0123 #define USB_PID_NYET        0x96
0124 /* data */
0125 #define USB_PID_DATA0       0xc3
0126 #define USB_PID_DATA1       0x4b
0127 #define USB_PID_DATA2       0x87
0128 #define USB_PID_MDATA       0x0f
0129 /* Special */
0130 #define USB_PID_PREAMBLE    0x3c
0131 #define USB_PID_ERR     0x3c
0132 #define USB_PID_SPLIT       0x78
0133 #define USB_PID_PING        0xb4
0134 #define USB_PID_UNDEF_0     0xf0
0135 
0136 #define USB_PID_DATA_TOGGLE 0x88
0137 #define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
0138 
0139 #define PCI_CAP_ID_EHCI_DEBUG   0xa
0140 
0141 #define HUB_ROOT_RESET_TIME 50  /* times are in msec */
0142 #define HUB_SHORT_RESET_TIME    10
0143 #define HUB_LONG_RESET_TIME 200
0144 #define HUB_RESET_TIMEOUT   500
0145 
0146 #define DBGP_MAX_PACKET     8
0147 #define DBGP_TIMEOUT        (250 * 1000)
0148 #define DBGP_LOOPS      1000
0149 
0150 static inline u32 dbgp_pid_write_update(u32 x, u32 tok)
0151 {
0152     static int data0 = USB_PID_DATA1;
0153     data0 ^= USB_PID_DATA_TOGGLE;
0154     return (x & 0xffff0000) | (data0 << 8) | (tok & 0xff);
0155 }
0156 
0157 static inline u32 dbgp_pid_read_update(u32 x, u32 tok)
0158 {
0159     return (x & 0xffff0000) | (USB_PID_DATA0 << 8) | (tok & 0xff);
0160 }
0161 
0162 static int dbgp_wait_until_complete(void)
0163 {
0164     u32 ctrl;
0165     int ret;
0166 
0167     ret = readl_poll_timeout_atomic(&ehci_debug->control, ctrl,
0168                 (ctrl & DBGP_DONE), 1, DBGP_TIMEOUT);
0169     if (ret)
0170         return -DBGP_TIMEOUT;
0171 
0172     /*
0173      * Now that we have observed the completed transaction,
0174      * clear the done bit.
0175      */
0176     writel(ctrl | DBGP_DONE, &ehci_debug->control);
0177     return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
0178 }
0179 
0180 static inline void dbgp_mdelay(int ms)
0181 {
0182     int i;
0183 
0184     while (ms--) {
0185         for (i = 0; i < 1000; i++)
0186             outb(0x1, 0x80);
0187     }
0188 }
0189 
0190 static void dbgp_breath(void)
0191 {
0192     /* Sleep to give the debug port a chance to breathe */
0193 }
0194 
0195 static int dbgp_wait_until_done(unsigned ctrl, int loop)
0196 {
0197     u32 pids, lpid;
0198     int ret;
0199 
0200 retry:
0201     writel(ctrl | DBGP_GO, &ehci_debug->control);
0202     ret = dbgp_wait_until_complete();
0203     pids = readl(&ehci_debug->pids);
0204     lpid = DBGP_PID_GET(pids);
0205 
0206     if (ret < 0) {
0207         /* A -DBGP_TIMEOUT failure here means the device has
0208          * failed, perhaps because it was unplugged, in which
0209          * case we do not want to hang the system so the dbgp
0210          * will be marked as unsafe to use.  EHCI reset is the
0211          * only way to recover if you unplug the dbgp device.
0212          */
0213         if (ret == -DBGP_TIMEOUT && !dbgp_not_safe)
0214             dbgp_not_safe = 1;
0215         if (ret == -DBGP_ERR_BAD && --loop > 0)
0216             goto retry;
0217         return ret;
0218     }
0219 
0220     /*
0221      * If the port is getting full or it has dropped data
0222      * start pacing ourselves, not necessary but it's friendly.
0223      */
0224     if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET))
0225         dbgp_breath();
0226 
0227     /* If I get a NACK reissue the transmission */
0228     if (lpid == USB_PID_NAK) {
0229         if (--loop > 0)
0230             goto retry;
0231     }
0232 
0233     return ret;
0234 }
0235 
0236 static inline void dbgp_set_data(const void *buf, int size)
0237 {
0238     const unsigned char *bytes = buf;
0239     u32 lo, hi;
0240     int i;
0241 
0242     lo = hi = 0;
0243     for (i = 0; i < 4 && i < size; i++)
0244         lo |= bytes[i] << (8*i);
0245     for (; i < 8 && i < size; i++)
0246         hi |= bytes[i] << (8*(i - 4));
0247     writel(lo, &ehci_debug->data03);
0248     writel(hi, &ehci_debug->data47);
0249 }
0250 
0251 static inline void dbgp_get_data(void *buf, int size)
0252 {
0253     unsigned char *bytes = buf;
0254     u32 lo, hi;
0255     int i;
0256 
0257     lo = readl(&ehci_debug->data03);
0258     hi = readl(&ehci_debug->data47);
0259     for (i = 0; i < 4 && i < size; i++)
0260         bytes[i] = (lo >> (8*i)) & 0xff;
0261     for (; i < 8 && i < size; i++)
0262         bytes[i] = (hi >> (8*(i - 4))) & 0xff;
0263 }
0264 
0265 static int dbgp_bulk_write(unsigned devnum, unsigned endpoint,
0266              const char *bytes, int size)
0267 {
0268     int ret;
0269     u32 addr;
0270     u32 pids, ctrl;
0271 
0272     if (size > DBGP_MAX_PACKET)
0273         return -1;
0274 
0275     addr = DBGP_EPADDR(devnum, endpoint);
0276 
0277     pids = readl(&ehci_debug->pids);
0278     pids = dbgp_pid_write_update(pids, USB_PID_OUT);
0279 
0280     ctrl = readl(&ehci_debug->control);
0281     ctrl = dbgp_len_update(ctrl, size);
0282     ctrl |= DBGP_OUT;
0283     ctrl |= DBGP_GO;
0284 
0285     dbgp_set_data(bytes, size);
0286     writel(addr, &ehci_debug->address);
0287     writel(pids, &ehci_debug->pids);
0288     ret = dbgp_wait_until_done(ctrl, DBGP_LOOPS);
0289 
0290     return ret;
0291 }
0292 
0293 static int dbgp_bulk_read(unsigned devnum, unsigned endpoint, void *data,
0294               int size, int loops)
0295 {
0296     u32 pids, addr, ctrl;
0297     int ret;
0298 
0299     if (size > DBGP_MAX_PACKET)
0300         return -1;
0301 
0302     addr = DBGP_EPADDR(devnum, endpoint);
0303 
0304     pids = readl(&ehci_debug->pids);
0305     pids = dbgp_pid_read_update(pids, USB_PID_IN);
0306 
0307     ctrl = readl(&ehci_debug->control);
0308     ctrl = dbgp_len_update(ctrl, size);
0309     ctrl &= ~DBGP_OUT;
0310     ctrl |= DBGP_GO;
0311 
0312     writel(addr, &ehci_debug->address);
0313     writel(pids, &ehci_debug->pids);
0314     ret = dbgp_wait_until_done(ctrl, loops);
0315     if (ret < 0)
0316         return ret;
0317 
0318     if (size > ret)
0319         size = ret;
0320     dbgp_get_data(data, size);
0321     return ret;
0322 }
0323 
0324 static int dbgp_control_msg(unsigned devnum, int requesttype,
0325     int request, int value, int index, void *data, int size)
0326 {
0327     u32 pids, addr, ctrl;
0328     struct usb_ctrlrequest req;
0329     int read;
0330     int ret;
0331 
0332     read = (requesttype & USB_DIR_IN) != 0;
0333     if (size > (read ? DBGP_MAX_PACKET : 0))
0334         return -1;
0335 
0336     /* Compute the control message */
0337     req.bRequestType = requesttype;
0338     req.bRequest = request;
0339     req.wValue = cpu_to_le16(value);
0340     req.wIndex = cpu_to_le16(index);
0341     req.wLength = cpu_to_le16(size);
0342 
0343     pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
0344     addr = DBGP_EPADDR(devnum, 0);
0345 
0346     ctrl = readl(&ehci_debug->control);
0347     ctrl = dbgp_len_update(ctrl, sizeof(req));
0348     ctrl |= DBGP_OUT;
0349     ctrl |= DBGP_GO;
0350 
0351     /* Send the setup message */
0352     dbgp_set_data(&req, sizeof(req));
0353     writel(addr, &ehci_debug->address);
0354     writel(pids, &ehci_debug->pids);
0355     ret = dbgp_wait_until_done(ctrl, DBGP_LOOPS);
0356     if (ret < 0)
0357         return ret;
0358 
0359     /* Read the result */
0360     return dbgp_bulk_read(devnum, 0, data, size, DBGP_LOOPS);
0361 }
0362 
0363 /* Find a PCI capability */
0364 static u32 __init find_cap(u32 num, u32 slot, u32 func, int cap)
0365 {
0366     u8 pos;
0367     int bytes;
0368 
0369     if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
0370         PCI_STATUS_CAP_LIST))
0371         return 0;
0372 
0373     pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
0374     for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
0375         u8 id;
0376 
0377         pos &= ~3;
0378         id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
0379         if (id == 0xff)
0380             break;
0381         if (id == cap)
0382             return pos;
0383 
0384         pos = read_pci_config_byte(num, slot, func,
0385                          pos+PCI_CAP_LIST_NEXT);
0386     }
0387     return 0;
0388 }
0389 
0390 static u32 __init __find_dbgp(u32 bus, u32 slot, u32 func)
0391 {
0392     u32 class;
0393 
0394     class = read_pci_config(bus, slot, func, PCI_CLASS_REVISION);
0395     if ((class >> 8) != PCI_CLASS_SERIAL_USB_EHCI)
0396         return 0;
0397 
0398     return find_cap(bus, slot, func, PCI_CAP_ID_EHCI_DEBUG);
0399 }
0400 
0401 static u32 __init find_dbgp(int ehci_num, u32 *rbus, u32 *rslot, u32 *rfunc)
0402 {
0403     u32 bus, slot, func;
0404 
0405     for (bus = 0; bus < 256; bus++) {
0406         for (slot = 0; slot < 32; slot++) {
0407             for (func = 0; func < 8; func++) {
0408                 unsigned cap;
0409 
0410                 cap = __find_dbgp(bus, slot, func);
0411 
0412                 if (!cap)
0413                     continue;
0414                 if (ehci_num-- != 0)
0415                     continue;
0416                 *rbus = bus;
0417                 *rslot = slot;
0418                 *rfunc = func;
0419                 return cap;
0420             }
0421         }
0422     }
0423     return 0;
0424 }
0425 
0426 static int dbgp_ehci_startup(void)
0427 {
0428     u32 ctrl, cmd, status;
0429     int loop;
0430 
0431     /* Claim ownership, but do not enable yet */
0432     ctrl = readl(&ehci_debug->control);
0433     ctrl |= DBGP_OWNER;
0434     ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
0435     writel(ctrl, &ehci_debug->control);
0436     udelay(1);
0437 
0438     dbgp_ehci_status("EHCI startup");
0439     /* Start the ehci running */
0440     cmd = readl(&ehci_regs->command);
0441     cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
0442     cmd |= CMD_RUN;
0443     writel(cmd, &ehci_regs->command);
0444 
0445     /* Ensure everything is routed to the EHCI */
0446     writel(FLAG_CF, &ehci_regs->configured_flag);
0447 
0448     /* Wait until the controller is no longer halted */
0449     loop = 1000;
0450     do {
0451         status = readl(&ehci_regs->status);
0452         if (!(status & STS_HALT))
0453             break;
0454         udelay(1);
0455     } while (--loop > 0);
0456 
0457     if (!loop) {
0458         dbgp_printk("ehci can not be started\n");
0459         return -ENODEV;
0460     }
0461     dbgp_printk("ehci started\n");
0462     return 0;
0463 }
0464 
0465 static int dbgp_ehci_controller_reset(void)
0466 {
0467     int loop = 250 * 1000;
0468     u32 cmd;
0469 
0470     /* Reset the EHCI controller */
0471     cmd = readl(&ehci_regs->command);
0472     cmd |= CMD_RESET;
0473     writel(cmd, &ehci_regs->command);
0474     do {
0475         cmd = readl(&ehci_regs->command);
0476     } while ((cmd & CMD_RESET) && (--loop > 0));
0477 
0478     if (!loop) {
0479         dbgp_printk("can not reset ehci\n");
0480         return -1;
0481     }
0482     dbgp_ehci_status("ehci reset done");
0483     return 0;
0484 }
0485 static int ehci_wait_for_port(int port);
0486 /* Return 0 on success
0487  * Return -ENODEV for any general failure
0488  * Return -EIO if wait for port fails
0489  */
0490 static int _dbgp_external_startup(void)
0491 {
0492     int devnum;
0493     struct usb_debug_descriptor dbgp_desc;
0494     int ret;
0495     u32 ctrl, portsc, cmd;
0496     int dbg_port = dbgp_phys_port;
0497     int tries = 3;
0498     int reset_port_tries = 1;
0499     int try_hard_once = 1;
0500 
0501 try_port_reset_again:
0502     ret = dbgp_ehci_startup();
0503     if (ret)
0504         return ret;
0505 
0506     /* Wait for a device to show up in the debug port */
0507     ret = ehci_wait_for_port(dbg_port);
0508     if (ret < 0) {
0509         portsc = readl(&ehci_regs->port_status[dbg_port - 1]);
0510         if (!(portsc & PORT_CONNECT) && try_hard_once) {
0511             /* Last ditch effort to try to force enable
0512              * the debug device by using the packet test
0513              * ehci command to try and wake it up. */
0514             try_hard_once = 0;
0515             cmd = readl(&ehci_regs->command);
0516             cmd &= ~CMD_RUN;
0517             writel(cmd, &ehci_regs->command);
0518             portsc = readl(&ehci_regs->port_status[dbg_port - 1]);
0519             portsc |= PORT_TEST_PKT;
0520             writel(portsc, &ehci_regs->port_status[dbg_port - 1]);
0521             dbgp_ehci_status("Trying to force debug port online");
0522             mdelay(50);
0523             dbgp_ehci_controller_reset();
0524             goto try_port_reset_again;
0525         } else if (reset_port_tries--) {
0526             goto try_port_reset_again;
0527         }
0528         dbgp_printk("No device found in debug port\n");
0529         return -EIO;
0530     }
0531     dbgp_ehci_status("wait for port done");
0532 
0533     /* Enable the debug port */
0534     ctrl = readl(&ehci_debug->control);
0535     ctrl |= DBGP_CLAIM;
0536     writel(ctrl, &ehci_debug->control);
0537     ctrl = readl(&ehci_debug->control);
0538     if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
0539         dbgp_printk("No device in debug port\n");
0540         writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control);
0541         return -ENODEV;
0542     }
0543     dbgp_ehci_status("debug ported enabled");
0544 
0545     /* Completely transfer the debug device to the debug controller */
0546     portsc = readl(&ehci_regs->port_status[dbg_port - 1]);
0547     portsc &= ~PORT_PE;
0548     writel(portsc, &ehci_regs->port_status[dbg_port - 1]);
0549 
0550     dbgp_mdelay(100);
0551 
0552 try_again:
0553     /* Find the debug device and make it device number 127 */
0554     for (devnum = 0; devnum <= 127; devnum++) {
0555         ret = dbgp_control_msg(devnum,
0556             USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
0557             USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
0558             &dbgp_desc, sizeof(dbgp_desc));
0559         if (ret > 0)
0560             break;
0561     }
0562     if (devnum > 127) {
0563         dbgp_printk("Could not find attached debug device\n");
0564         goto err;
0565     }
0566     dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint;
0567     dbgp_endpoint_in = dbgp_desc.bDebugInEndpoint;
0568 
0569     /* Move the device to 127 if it isn't already there */
0570     if (devnum != USB_DEBUG_DEVNUM) {
0571         ret = dbgp_control_msg(devnum,
0572             USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
0573             USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
0574         if (ret < 0) {
0575             dbgp_printk("Could not move attached device to %d\n",
0576                 USB_DEBUG_DEVNUM);
0577             goto err;
0578         }
0579         dbgp_printk("debug device renamed to 127\n");
0580     }
0581 
0582     /* Enable the debug interface */
0583     ret = dbgp_control_msg(USB_DEBUG_DEVNUM,
0584         USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
0585         USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
0586     if (ret < 0) {
0587         dbgp_printk(" Could not enable the debug device\n");
0588         goto err;
0589     }
0590     dbgp_printk("debug interface enabled\n");
0591     /* Perform a small write to get the even/odd data state in sync
0592      */
0593     ret = dbgp_bulk_write(USB_DEBUG_DEVNUM, dbgp_endpoint_out, " ", 1);
0594     if (ret < 0) {
0595         dbgp_printk("dbgp_bulk_write failed: %d\n", ret);
0596         goto err;
0597     }
0598     dbgp_printk("small write done\n");
0599     dbgp_not_safe = 0;
0600 
0601     return 0;
0602 err:
0603     if (tries--)
0604         goto try_again;
0605     return -ENODEV;
0606 }
0607 
0608 static int ehci_reset_port(int port)
0609 {
0610     u32 portsc;
0611     u32 delay_time, delay;
0612     int loop;
0613 
0614     dbgp_ehci_status("reset port");
0615     /* Reset the usb debug port */
0616     portsc = readl(&ehci_regs->port_status[port - 1]);
0617     portsc &= ~PORT_PE;
0618     portsc |= PORT_RESET;
0619     writel(portsc, &ehci_regs->port_status[port - 1]);
0620 
0621     delay = HUB_ROOT_RESET_TIME;
0622     for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
0623          delay_time += delay) {
0624         dbgp_mdelay(delay);
0625         portsc = readl(&ehci_regs->port_status[port - 1]);
0626         if (!(portsc & PORT_RESET))
0627             break;
0628     }
0629     if (portsc & PORT_RESET) {
0630         /* force reset to complete */
0631         loop = 100 * 1000;
0632         writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
0633             &ehci_regs->port_status[port - 1]);
0634         do {
0635             udelay(1);
0636             portsc = readl(&ehci_regs->port_status[port-1]);
0637         } while ((portsc & PORT_RESET) && (--loop > 0));
0638     }
0639 
0640     /* Device went away? */
0641     if (!(portsc & PORT_CONNECT))
0642         return -ENOTCONN;
0643 
0644     /* bomb out completely if something weird happened */
0645     if ((portsc & PORT_CSC))
0646         return -EINVAL;
0647 
0648     /* If we've finished resetting, then break out of the loop */
0649     if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
0650         return 0;
0651     return -EBUSY;
0652 }
0653 
0654 static int ehci_wait_for_port(int port)
0655 {
0656     u32 status;
0657     int ret, reps;
0658 
0659     for (reps = 0; reps < 300; reps++) {
0660         status = readl(&ehci_regs->status);
0661         if (status & STS_PCD)
0662             break;
0663         dbgp_mdelay(1);
0664     }
0665     ret = ehci_reset_port(port);
0666     if (ret == 0)
0667         return 0;
0668     return -ENOTCONN;
0669 }
0670 
0671 typedef void (*set_debug_port_t)(int port);
0672 
0673 static void __init default_set_debug_port(int port)
0674 {
0675 }
0676 
0677 static set_debug_port_t __initdata set_debug_port = default_set_debug_port;
0678 
0679 static void __init nvidia_set_debug_port(int port)
0680 {
0681     u32 dword;
0682     dword = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
0683                  0x74);
0684     dword &= ~(0x0f<<12);
0685     dword |= ((port & 0x0f)<<12);
0686     write_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func, 0x74,
0687                  dword);
0688     dbgp_printk("set debug port to %d\n", port);
0689 }
0690 
0691 static void __init detect_set_debug_port(void)
0692 {
0693     u32 vendorid;
0694 
0695     vendorid = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
0696          0x00);
0697 
0698     if ((vendorid & 0xffff) == 0x10de) {
0699         dbgp_printk("using nvidia set_debug_port\n");
0700         set_debug_port = nvidia_set_debug_port;
0701     }
0702 }
0703 
0704 /* The code in early_ehci_bios_handoff() is derived from the usb pci
0705  * quirk initialization, but altered so as to use the early PCI
0706  * routines. */
0707 #define EHCI_USBLEGSUP_BIOS (1 << 16)   /* BIOS semaphore */
0708 #define EHCI_USBLEGCTLSTS   4       /* legacy control/status */
0709 static void __init early_ehci_bios_handoff(void)
0710 {
0711     u32 hcc_params = readl(&ehci_caps->hcc_params);
0712     int offset = (hcc_params >> 8) & 0xff;
0713     u32 cap;
0714     int msec;
0715 
0716     if (!offset)
0717         return;
0718 
0719     cap = read_pci_config(ehci_dev.bus, ehci_dev.slot,
0720                   ehci_dev.func, offset);
0721     dbgp_printk("dbgp: ehci BIOS state %08x\n", cap);
0722 
0723     if ((cap & 0xff) == 1 && (cap & EHCI_USBLEGSUP_BIOS)) {
0724         dbgp_printk("dbgp: BIOS handoff\n");
0725         write_pci_config_byte(ehci_dev.bus, ehci_dev.slot,
0726                       ehci_dev.func, offset + 3, 1);
0727     }
0728 
0729     /* if boot firmware now owns EHCI, spin till it hands it over. */
0730     msec = 1000;
0731     while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
0732         mdelay(10);
0733         msec -= 10;
0734         cap = read_pci_config(ehci_dev.bus, ehci_dev.slot,
0735                       ehci_dev.func, offset);
0736     }
0737 
0738     if (cap & EHCI_USBLEGSUP_BIOS) {
0739         /* well, possibly buggy BIOS... try to shut it down,
0740          * and hope nothing goes too wrong */
0741         dbgp_printk("dbgp: BIOS handoff failed: %08x\n", cap);
0742         write_pci_config_byte(ehci_dev.bus, ehci_dev.slot,
0743                       ehci_dev.func, offset + 2, 0);
0744     }
0745 
0746     /* just in case, always disable EHCI SMIs */
0747     write_pci_config_byte(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
0748                   offset + EHCI_USBLEGCTLSTS, 0);
0749 }
0750 
0751 static int __init ehci_setup(void)
0752 {
0753     u32 ctrl, portsc, hcs_params;
0754     u32 debug_port, new_debug_port = 0, n_ports;
0755     int ret, i;
0756     int port_map_tried;
0757     int playtimes = 3;
0758 
0759     early_ehci_bios_handoff();
0760 
0761 try_next_time:
0762     port_map_tried = 0;
0763 
0764 try_next_port:
0765 
0766     hcs_params = readl(&ehci_caps->hcs_params);
0767     debug_port = HCS_DEBUG_PORT(hcs_params);
0768     dbgp_phys_port = debug_port;
0769     n_ports    = HCS_N_PORTS(hcs_params);
0770 
0771     dbgp_printk("debug_port: %d\n", debug_port);
0772     dbgp_printk("n_ports:    %d\n", n_ports);
0773     dbgp_ehci_status("");
0774 
0775     for (i = 1; i <= n_ports; i++) {
0776         portsc = readl(&ehci_regs->port_status[i-1]);
0777         dbgp_printk("portstatus%d: %08x\n", i, portsc);
0778     }
0779 
0780     if (port_map_tried && (new_debug_port != debug_port)) {
0781         if (--playtimes) {
0782             set_debug_port(new_debug_port);
0783             goto try_next_time;
0784         }
0785         return -1;
0786     }
0787 
0788     /* Only reset the controller if it is not already in the
0789      * configured state */
0790     if (!(readl(&ehci_regs->configured_flag) & FLAG_CF)) {
0791         if (dbgp_ehci_controller_reset() != 0)
0792             return -1;
0793     } else {
0794         dbgp_ehci_status("ehci skip - already configured");
0795     }
0796 
0797     ret = _dbgp_external_startup();
0798     if (ret == -EIO)
0799         goto next_debug_port;
0800 
0801     if (ret < 0) {
0802         /* Things didn't work so remove my claim */
0803         ctrl = readl(&ehci_debug->control);
0804         ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
0805         writel(ctrl, &ehci_debug->control);
0806         return -1;
0807     }
0808     return 0;
0809 
0810 next_debug_port:
0811     port_map_tried |= (1<<(debug_port - 1));
0812     new_debug_port = ((debug_port-1+1)%n_ports) + 1;
0813     if (port_map_tried != ((1<<n_ports) - 1)) {
0814         set_debug_port(new_debug_port);
0815         goto try_next_port;
0816     }
0817     if (--playtimes) {
0818         set_debug_port(new_debug_port);
0819         goto try_next_time;
0820     }
0821 
0822     return -1;
0823 }
0824 
0825 int __init early_dbgp_init(char *s)
0826 {
0827     u32 debug_port, bar, offset;
0828     u32 bus, slot, func, cap;
0829     void __iomem *ehci_bar;
0830     u32 dbgp_num;
0831     u32 bar_val;
0832     char *e;
0833     int ret;
0834     u8 byte;
0835 
0836     if (!early_pci_allowed())
0837         return -1;
0838 
0839     dbgp_num = 0;
0840     if (*s)
0841         dbgp_num = simple_strtoul(s, &e, 10);
0842     dbgp_printk("dbgp_num: %d\n", dbgp_num);
0843 
0844     cap = find_dbgp(dbgp_num, &bus, &slot, &func);
0845     if (!cap)
0846         return -1;
0847 
0848     dbgp_printk("Found EHCI debug port on %02x:%02x.%1x\n", bus, slot,
0849              func);
0850 
0851     debug_port = read_pci_config(bus, slot, func, cap);
0852     bar = (debug_port >> 29) & 0x7;
0853     bar = (bar * 4) + 0xc;
0854     offset = (debug_port >> 16) & 0xfff;
0855     dbgp_printk("bar: %02x offset: %03x\n", bar, offset);
0856     if (bar != PCI_BASE_ADDRESS_0) {
0857         dbgp_printk("only debug ports on bar 1 handled.\n");
0858 
0859         return -1;
0860     }
0861 
0862     bar_val = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
0863     dbgp_printk("bar_val: %02x offset: %03x\n", bar_val, offset);
0864     if (bar_val & ~PCI_BASE_ADDRESS_MEM_MASK) {
0865         dbgp_printk("only simple 32bit mmio bars supported\n");
0866 
0867         return -1;
0868     }
0869 
0870     /* double check if the mem space is enabled */
0871     byte = read_pci_config_byte(bus, slot, func, 0x04);
0872     if (!(byte & 0x2)) {
0873         byte  |= 0x02;
0874         write_pci_config_byte(bus, slot, func, 0x04, byte);
0875         dbgp_printk("mmio for ehci enabled\n");
0876     }
0877 
0878     /*
0879      * FIXME I don't have the bar size so just guess PAGE_SIZE is more
0880      * than enough.  1K is the biggest I have seen.
0881      */
0882     set_fixmap_nocache(FIX_DBGP_BASE, bar_val & PAGE_MASK);
0883     ehci_bar = (void __iomem *)__fix_to_virt(FIX_DBGP_BASE);
0884     ehci_bar += bar_val & ~PAGE_MASK;
0885     dbgp_printk("ehci_bar: %p\n", ehci_bar);
0886 
0887     ehci_caps  = ehci_bar;
0888     ehci_regs  = ehci_bar + EARLY_HC_LENGTH(readl(&ehci_caps->hc_capbase));
0889     ehci_debug = ehci_bar + offset;
0890     ehci_dev.bus = bus;
0891     ehci_dev.slot = slot;
0892     ehci_dev.func = func;
0893 
0894     detect_set_debug_port();
0895 
0896     ret = ehci_setup();
0897     if (ret < 0) {
0898         dbgp_printk("ehci_setup failed\n");
0899         ehci_debug = NULL;
0900 
0901         return -1;
0902     }
0903     dbgp_ehci_status("early_init_complete");
0904 
0905     return 0;
0906 }
0907 
0908 static void early_dbgp_write(struct console *con, const char *str, u32 n)
0909 {
0910     int chunk;
0911     char buf[DBGP_MAX_PACKET];
0912     int use_cr = 0;
0913     u32 cmd, ctrl;
0914     int reset_run = 0;
0915 
0916     if (!ehci_debug || dbgp_not_safe)
0917         return;
0918 
0919     cmd = readl(&ehci_regs->command);
0920     if (unlikely(!(cmd & CMD_RUN))) {
0921         /* If the ehci controller is not in the run state do extended
0922          * checks to see if the acpi or some other initialization also
0923          * reset the ehci debug port */
0924         ctrl = readl(&ehci_debug->control);
0925         if (!(ctrl & DBGP_ENABLED)) {
0926             dbgp_not_safe = 1;
0927             _dbgp_external_startup();
0928         } else {
0929             cmd |= CMD_RUN;
0930             writel(cmd, &ehci_regs->command);
0931             reset_run = 1;
0932         }
0933     }
0934     while (n > 0) {
0935         for (chunk = 0; chunk < DBGP_MAX_PACKET && n > 0;
0936              str++, chunk++, n--) {
0937             if (!use_cr && *str == '\n') {
0938                 use_cr = 1;
0939                 buf[chunk] = '\r';
0940                 str--;
0941                 n++;
0942                 continue;
0943             }
0944             if (use_cr)
0945                 use_cr = 0;
0946             buf[chunk] = *str;
0947         }
0948         if (chunk > 0) {
0949             dbgp_bulk_write(USB_DEBUG_DEVNUM,
0950                     dbgp_endpoint_out, buf, chunk);
0951         }
0952     }
0953     if (unlikely(reset_run)) {
0954         cmd = readl(&ehci_regs->command);
0955         cmd &= ~CMD_RUN;
0956         writel(cmd, &ehci_regs->command);
0957     }
0958 }
0959 
0960 struct console early_dbgp_console = {
0961     .name =     "earlydbg",
0962     .write =    early_dbgp_write,
0963     .flags =    CON_PRINTBUFFER,
0964     .index =    -1,
0965 };
0966 
0967 #if IS_ENABLED(CONFIG_USB)
0968 int dbgp_reset_prep(struct usb_hcd *hcd)
0969 {
0970     int ret = xen_dbgp_reset_prep(hcd);
0971     u32 ctrl;
0972 
0973     if (ret)
0974         return ret;
0975 
0976     dbgp_not_safe = 1;
0977     if (!ehci_debug)
0978         return 0;
0979 
0980     if ((early_dbgp_console.index != -1 &&
0981          !(early_dbgp_console.flags & CON_BOOT)) ||
0982         dbgp_kgdb_mode)
0983         return 1;
0984     /* This means the console is not initialized, or should get
0985      * shutdown so as to allow for reuse of the usb device, which
0986      * means it is time to shutdown the usb debug port. */
0987     ctrl = readl(&ehci_debug->control);
0988     if (ctrl & DBGP_ENABLED) {
0989         ctrl &= ~(DBGP_CLAIM);
0990         writel(ctrl, &ehci_debug->control);
0991     }
0992     return 0;
0993 }
0994 EXPORT_SYMBOL_GPL(dbgp_reset_prep);
0995 
0996 int dbgp_external_startup(struct usb_hcd *hcd)
0997 {
0998     return xen_dbgp_external_startup(hcd) ?: _dbgp_external_startup();
0999 }
1000 EXPORT_SYMBOL_GPL(dbgp_external_startup);
1001 #endif /* USB */
1002 
1003 #ifdef CONFIG_KGDB
1004 
1005 static char kgdbdbgp_buf[DBGP_MAX_PACKET];
1006 static int kgdbdbgp_buf_sz;
1007 static int kgdbdbgp_buf_idx;
1008 static int kgdbdbgp_loop_cnt = DBGP_LOOPS;
1009 
1010 static int kgdbdbgp_read_char(void)
1011 {
1012     int ret;
1013 
1014     if (kgdbdbgp_buf_idx < kgdbdbgp_buf_sz) {
1015         char ch = kgdbdbgp_buf[kgdbdbgp_buf_idx++];
1016         return ch;
1017     }
1018 
1019     ret = dbgp_bulk_read(USB_DEBUG_DEVNUM, dbgp_endpoint_in,
1020                  &kgdbdbgp_buf, DBGP_MAX_PACKET,
1021                  kgdbdbgp_loop_cnt);
1022     if (ret <= 0)
1023         return NO_POLL_CHAR;
1024     kgdbdbgp_buf_sz = ret;
1025     kgdbdbgp_buf_idx = 1;
1026     return kgdbdbgp_buf[0];
1027 }
1028 
1029 static void kgdbdbgp_write_char(u8 chr)
1030 {
1031     early_dbgp_write(NULL, &chr, 1);
1032 }
1033 
1034 static struct kgdb_io kgdbdbgp_io_ops = {
1035     .name = "kgdbdbgp",
1036     .read_char = kgdbdbgp_read_char,
1037     .write_char = kgdbdbgp_write_char,
1038 };
1039 
1040 static int kgdbdbgp_wait_time;
1041 
1042 static int __init kgdbdbgp_parse_config(char *str)
1043 {
1044     char *ptr;
1045 
1046     if (!ehci_debug) {
1047         if (early_dbgp_init(str))
1048             return -1;
1049     }
1050     ptr = strchr(str, ',');
1051     if (ptr) {
1052         ptr++;
1053         kgdbdbgp_wait_time = simple_strtoul(ptr, &ptr, 10);
1054     }
1055     kgdb_register_io_module(&kgdbdbgp_io_ops);
1056     if (early_dbgp_console.index != -1)
1057         kgdbdbgp_io_ops.cons = &early_dbgp_console;
1058 
1059     return 0;
1060 }
1061 early_param("kgdbdbgp", kgdbdbgp_parse_config);
1062 
1063 static int kgdbdbgp_reader_thread(void *ptr)
1064 {
1065     int ret;
1066 
1067     while (readl(&ehci_debug->control) & DBGP_ENABLED) {
1068         kgdbdbgp_loop_cnt = 1;
1069         ret = kgdbdbgp_read_char();
1070         kgdbdbgp_loop_cnt = DBGP_LOOPS;
1071         if (ret != NO_POLL_CHAR) {
1072             if (ret == 0x3 || ret == '$') {
1073                 if (ret == '$')
1074                     kgdbdbgp_buf_idx--;
1075                 kgdb_breakpoint();
1076             }
1077             continue;
1078         }
1079         schedule_timeout_interruptible(kgdbdbgp_wait_time * HZ);
1080     }
1081     return 0;
1082 }
1083 
1084 static int __init kgdbdbgp_start_thread(void)
1085 {
1086     if (dbgp_kgdb_mode && kgdbdbgp_wait_time)
1087         kthread_run(kgdbdbgp_reader_thread, NULL, "%s", "dbgp");
1088 
1089     return 0;
1090 }
1091 device_initcall(kgdbdbgp_start_thread);
1092 #endif /* CONFIG_KGDB */
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