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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
0004  *
0005  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
0006  *
0007  * Authors: Felipe Balbi <balbi@ti.com>,
0008  *      Sebastian Andrzej Siewior <bigeasy@linutronix.de>
0009  */
0010 
0011 #include <linux/kernel.h>
0012 #include <linux/slab.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/io.h>
0018 #include <linux/list.h>
0019 #include <linux/dma-mapping.h>
0020 
0021 #include <linux/usb/ch9.h>
0022 #include <linux/usb/gadget.h>
0023 #include <linux/usb/composite.h>
0024 
0025 #include "core.h"
0026 #include "debug.h"
0027 #include "gadget.h"
0028 #include "io.h"
0029 
0030 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
0031 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
0032         struct dwc3_ep *dep, struct dwc3_request *req);
0033 
0034 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
0035         dma_addr_t buf_dma, u32 len, u32 type, bool chain)
0036 {
0037     struct dwc3_trb         *trb;
0038     struct dwc3         *dwc;
0039 
0040     dwc = dep->dwc;
0041     trb = &dwc->ep0_trb[dep->trb_enqueue];
0042 
0043     if (chain)
0044         dep->trb_enqueue++;
0045 
0046     trb->bpl = lower_32_bits(buf_dma);
0047     trb->bph = upper_32_bits(buf_dma);
0048     trb->size = len;
0049     trb->ctrl = type;
0050 
0051     trb->ctrl |= (DWC3_TRB_CTRL_HWO
0052             | DWC3_TRB_CTRL_ISP_IMI);
0053 
0054     if (chain)
0055         trb->ctrl |= DWC3_TRB_CTRL_CHN;
0056     else
0057         trb->ctrl |= (DWC3_TRB_CTRL_IOC
0058                 | DWC3_TRB_CTRL_LST);
0059 
0060     trace_dwc3_prepare_trb(dep, trb);
0061 }
0062 
0063 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
0064 {
0065     struct dwc3_gadget_ep_cmd_params params;
0066     struct dwc3         *dwc;
0067     int             ret;
0068 
0069     if (dep->flags & DWC3_EP_TRANSFER_STARTED)
0070         return 0;
0071 
0072     dwc = dep->dwc;
0073 
0074     memset(&params, 0, sizeof(params));
0075     params.param0 = upper_32_bits(dwc->ep0_trb_addr);
0076     params.param1 = lower_32_bits(dwc->ep0_trb_addr);
0077 
0078     ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
0079     if (ret < 0)
0080         return ret;
0081 
0082     dwc->ep0_next_event = DWC3_EP0_COMPLETE;
0083 
0084     return 0;
0085 }
0086 
0087 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
0088         struct dwc3_request *req)
0089 {
0090     struct dwc3     *dwc = dep->dwc;
0091 
0092     req->request.actual = 0;
0093     req->request.status = -EINPROGRESS;
0094     req->epnum      = dep->number;
0095 
0096     list_add_tail(&req->list, &dep->pending_list);
0097 
0098     /*
0099      * Gadget driver might not be quick enough to queue a request
0100      * before we get a Transfer Not Ready event on this endpoint.
0101      *
0102      * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
0103      * flag is set, it's telling us that as soon as Gadget queues the
0104      * required request, we should kick the transfer here because the
0105      * IRQ we were waiting for is long gone.
0106      */
0107     if (dep->flags & DWC3_EP_PENDING_REQUEST) {
0108         unsigned int direction;
0109 
0110         direction = !!(dep->flags & DWC3_EP0_DIR_IN);
0111 
0112         if (dwc->ep0state != EP0_DATA_PHASE) {
0113             dev_WARN(dwc->dev, "Unexpected pending request\n");
0114             return 0;
0115         }
0116 
0117         __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
0118 
0119         dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
0120                 DWC3_EP0_DIR_IN);
0121 
0122         return 0;
0123     }
0124 
0125     /*
0126      * In case gadget driver asked us to delay the STATUS phase,
0127      * handle it here.
0128      */
0129     if (dwc->delayed_status) {
0130         unsigned int direction;
0131 
0132         direction = !dwc->ep0_expect_in;
0133         dwc->delayed_status = false;
0134         usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
0135 
0136         if (dwc->ep0state == EP0_STATUS_PHASE)
0137             __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
0138 
0139         return 0;
0140     }
0141 
0142     /*
0143      * Unfortunately we have uncovered a limitation wrt the Data Phase.
0144      *
0145      * Section 9.4 says we can wait for the XferNotReady(DATA) event to
0146      * come before issueing Start Transfer command, but if we do, we will
0147      * miss situations where the host starts another SETUP phase instead of
0148      * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
0149      * Layer Compliance Suite.
0150      *
0151      * The problem surfaces due to the fact that in case of back-to-back
0152      * SETUP packets there will be no XferNotReady(DATA) generated and we
0153      * will be stuck waiting for XferNotReady(DATA) forever.
0154      *
0155      * By looking at tables 9-13 and 9-14 of the Databook, we can see that
0156      * it tells us to start Data Phase right away. It also mentions that if
0157      * we receive a SETUP phase instead of the DATA phase, core will issue
0158      * XferComplete for the DATA phase, before actually initiating it in
0159      * the wire, with the TRB's status set to "SETUP_PENDING". Such status
0160      * can only be used to print some debugging logs, as the core expects
0161      * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
0162      * just so it completes right away, without transferring anything and,
0163      * only then, we can go back to the SETUP phase.
0164      *
0165      * Because of this scenario, SNPS decided to change the programming
0166      * model of control transfers and support on-demand transfers only for
0167      * the STATUS phase. To fix the issue we have now, we will always wait
0168      * for gadget driver to queue the DATA phase's struct usb_request, then
0169      * start it right away.
0170      *
0171      * If we're actually in a 2-stage transfer, we will wait for
0172      * XferNotReady(STATUS).
0173      */
0174     if (dwc->three_stage_setup) {
0175         unsigned int direction;
0176 
0177         direction = dwc->ep0_expect_in;
0178         dwc->ep0state = EP0_DATA_PHASE;
0179 
0180         __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
0181 
0182         dep->flags &= ~DWC3_EP0_DIR_IN;
0183     }
0184 
0185     return 0;
0186 }
0187 
0188 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
0189         gfp_t gfp_flags)
0190 {
0191     struct dwc3_request     *req = to_dwc3_request(request);
0192     struct dwc3_ep          *dep = to_dwc3_ep(ep);
0193     struct dwc3         *dwc = dep->dwc;
0194 
0195     unsigned long           flags;
0196 
0197     int             ret;
0198 
0199     spin_lock_irqsave(&dwc->lock, flags);
0200     if (!dep->endpoint.desc || !dwc->pullups_connected) {
0201         dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
0202                 dep->name);
0203         ret = -ESHUTDOWN;
0204         goto out;
0205     }
0206 
0207     /* we share one TRB for ep0/1 */
0208     if (!list_empty(&dep->pending_list)) {
0209         ret = -EBUSY;
0210         goto out;
0211     }
0212 
0213     ret = __dwc3_gadget_ep0_queue(dep, req);
0214 
0215 out:
0216     spin_unlock_irqrestore(&dwc->lock, flags);
0217 
0218     return ret;
0219 }
0220 
0221 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
0222 {
0223     struct dwc3_ep      *dep;
0224 
0225     /* reinitialize physical ep1 */
0226     dep = dwc->eps[1];
0227     dep->flags = DWC3_EP_ENABLED;
0228 
0229     /* stall is always issued on EP0 */
0230     dep = dwc->eps[0];
0231     __dwc3_gadget_ep_set_halt(dep, 1, false);
0232     dep->flags = DWC3_EP_ENABLED;
0233     dwc->delayed_status = false;
0234 
0235     if (!list_empty(&dep->pending_list)) {
0236         struct dwc3_request *req;
0237 
0238         req = next_request(&dep->pending_list);
0239         dwc3_gadget_giveback(dep, req, -ECONNRESET);
0240     }
0241 
0242     dwc->eps[0]->trb_enqueue = 0;
0243     dwc->eps[1]->trb_enqueue = 0;
0244     dwc->ep0state = EP0_SETUP_PHASE;
0245     dwc3_ep0_out_start(dwc);
0246 }
0247 
0248 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
0249 {
0250     struct dwc3_ep          *dep = to_dwc3_ep(ep);
0251     struct dwc3         *dwc = dep->dwc;
0252 
0253     dwc3_ep0_stall_and_restart(dwc);
0254 
0255     return 0;
0256 }
0257 
0258 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
0259 {
0260     struct dwc3_ep          *dep = to_dwc3_ep(ep);
0261     struct dwc3         *dwc = dep->dwc;
0262     unsigned long           flags;
0263     int             ret;
0264 
0265     spin_lock_irqsave(&dwc->lock, flags);
0266     ret = __dwc3_gadget_ep0_set_halt(ep, value);
0267     spin_unlock_irqrestore(&dwc->lock, flags);
0268 
0269     return ret;
0270 }
0271 
0272 void dwc3_ep0_out_start(struct dwc3 *dwc)
0273 {
0274     struct dwc3_ep          *dep;
0275     int             ret;
0276     int                             i;
0277 
0278     complete(&dwc->ep0_in_setup);
0279 
0280     dep = dwc->eps[0];
0281     dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
0282             DWC3_TRBCTL_CONTROL_SETUP, false);
0283     ret = dwc3_ep0_start_trans(dep);
0284     WARN_ON(ret < 0);
0285     for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
0286         struct dwc3_ep *dwc3_ep;
0287 
0288         dwc3_ep = dwc->eps[i];
0289         if (!dwc3_ep)
0290             continue;
0291 
0292         if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
0293             continue;
0294 
0295         dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
0296         dwc3_stop_active_transfer(dwc3_ep, true, true);
0297     }
0298 }
0299 
0300 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
0301 {
0302     struct dwc3_ep      *dep;
0303     u32         windex = le16_to_cpu(wIndex_le);
0304     u32         epnum;
0305 
0306     epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
0307     if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
0308         epnum |= 1;
0309 
0310     dep = dwc->eps[epnum];
0311     if (dep == NULL)
0312         return NULL;
0313 
0314     if (dep->flags & DWC3_EP_ENABLED)
0315         return dep;
0316 
0317     return NULL;
0318 }
0319 
0320 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
0321 {
0322 }
0323 /*
0324  * ch 9.4.5
0325  */
0326 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
0327         struct usb_ctrlrequest *ctrl)
0328 {
0329     struct dwc3_ep      *dep;
0330     u32         recip;
0331     u32         value;
0332     u32         reg;
0333     u16         usb_status = 0;
0334     __le16          *response_pkt;
0335 
0336     /* We don't support PTM_STATUS */
0337     value = le16_to_cpu(ctrl->wValue);
0338     if (value != 0)
0339         return -EINVAL;
0340 
0341     recip = ctrl->bRequestType & USB_RECIP_MASK;
0342     switch (recip) {
0343     case USB_RECIP_DEVICE:
0344         /*
0345          * LTM will be set once we know how to set this in HW.
0346          */
0347         usb_status |= dwc->gadget->is_selfpowered;
0348 
0349         if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
0350             (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
0351             reg = dwc3_readl(dwc->regs, DWC3_DCTL);
0352             if (reg & DWC3_DCTL_INITU1ENA)
0353                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
0354             if (reg & DWC3_DCTL_INITU2ENA)
0355                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
0356         }
0357 
0358         break;
0359 
0360     case USB_RECIP_INTERFACE:
0361         /*
0362          * Function Remote Wake Capable D0
0363          * Function Remote Wakeup   D1
0364          */
0365         break;
0366 
0367     case USB_RECIP_ENDPOINT:
0368         dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
0369         if (!dep)
0370             return -EINVAL;
0371 
0372         if (dep->flags & DWC3_EP_STALL)
0373             usb_status = 1 << USB_ENDPOINT_HALT;
0374         break;
0375     default:
0376         return -EINVAL;
0377     }
0378 
0379     response_pkt = (__le16 *) dwc->setup_buf;
0380     *response_pkt = cpu_to_le16(usb_status);
0381 
0382     dep = dwc->eps[0];
0383     dwc->ep0_usb_req.dep = dep;
0384     dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
0385     dwc->ep0_usb_req.request.buf = dwc->setup_buf;
0386     dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
0387 
0388     return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
0389 }
0390 
0391 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
0392         int set)
0393 {
0394     u32 reg;
0395 
0396     if (state != USB_STATE_CONFIGURED)
0397         return -EINVAL;
0398     if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
0399             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
0400         return -EINVAL;
0401     if (set && dwc->dis_u1_entry_quirk)
0402         return -EINVAL;
0403 
0404     reg = dwc3_readl(dwc->regs, DWC3_DCTL);
0405     if (set)
0406         reg |= DWC3_DCTL_INITU1ENA;
0407     else
0408         reg &= ~DWC3_DCTL_INITU1ENA;
0409     dwc3_writel(dwc->regs, DWC3_DCTL, reg);
0410 
0411     return 0;
0412 }
0413 
0414 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
0415         int set)
0416 {
0417     u32 reg;
0418 
0419 
0420     if (state != USB_STATE_CONFIGURED)
0421         return -EINVAL;
0422     if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
0423             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
0424         return -EINVAL;
0425     if (set && dwc->dis_u2_entry_quirk)
0426         return -EINVAL;
0427 
0428     reg = dwc3_readl(dwc->regs, DWC3_DCTL);
0429     if (set)
0430         reg |= DWC3_DCTL_INITU2ENA;
0431     else
0432         reg &= ~DWC3_DCTL_INITU2ENA;
0433     dwc3_writel(dwc->regs, DWC3_DCTL, reg);
0434 
0435     return 0;
0436 }
0437 
0438 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
0439         u32 wIndex, int set)
0440 {
0441     if ((wIndex & 0xff) != 0)
0442         return -EINVAL;
0443     if (!set)
0444         return -EINVAL;
0445 
0446     switch (wIndex >> 8) {
0447     case USB_TEST_J:
0448     case USB_TEST_K:
0449     case USB_TEST_SE0_NAK:
0450     case USB_TEST_PACKET:
0451     case USB_TEST_FORCE_ENABLE:
0452         dwc->test_mode_nr = wIndex >> 8;
0453         dwc->test_mode = true;
0454         break;
0455     default:
0456         return -EINVAL;
0457     }
0458 
0459     return 0;
0460 }
0461 
0462 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
0463         struct usb_ctrlrequest *ctrl, int set)
0464 {
0465     enum usb_device_state   state;
0466     u32         wValue;
0467     u32         wIndex;
0468     int         ret = 0;
0469 
0470     wValue = le16_to_cpu(ctrl->wValue);
0471     wIndex = le16_to_cpu(ctrl->wIndex);
0472     state = dwc->gadget->state;
0473 
0474     switch (wValue) {
0475     case USB_DEVICE_REMOTE_WAKEUP:
0476         break;
0477     /*
0478      * 9.4.1 says only for SS, in AddressState only for
0479      * default control pipe
0480      */
0481     case USB_DEVICE_U1_ENABLE:
0482         ret = dwc3_ep0_handle_u1(dwc, state, set);
0483         break;
0484     case USB_DEVICE_U2_ENABLE:
0485         ret = dwc3_ep0_handle_u2(dwc, state, set);
0486         break;
0487     case USB_DEVICE_LTM_ENABLE:
0488         ret = -EINVAL;
0489         break;
0490     case USB_DEVICE_TEST_MODE:
0491         ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
0492         break;
0493     default:
0494         ret = -EINVAL;
0495     }
0496 
0497     return ret;
0498 }
0499 
0500 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
0501         struct usb_ctrlrequest *ctrl, int set)
0502 {
0503     u32         wValue;
0504     int         ret = 0;
0505 
0506     wValue = le16_to_cpu(ctrl->wValue);
0507 
0508     switch (wValue) {
0509     case USB_INTRF_FUNC_SUSPEND:
0510         /*
0511          * REVISIT: Ideally we would enable some low power mode here,
0512          * however it's unclear what we should be doing here.
0513          *
0514          * For now, we're not doing anything, just making sure we return
0515          * 0 so USB Command Verifier tests pass without any errors.
0516          */
0517         break;
0518     default:
0519         ret = -EINVAL;
0520     }
0521 
0522     return ret;
0523 }
0524 
0525 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
0526         struct usb_ctrlrequest *ctrl, int set)
0527 {
0528     struct dwc3_ep      *dep;
0529     u32         wValue;
0530     int         ret;
0531 
0532     wValue = le16_to_cpu(ctrl->wValue);
0533 
0534     switch (wValue) {
0535     case USB_ENDPOINT_HALT:
0536         dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
0537         if (!dep)
0538             return -EINVAL;
0539 
0540         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
0541             break;
0542 
0543         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
0544         if (ret)
0545             return -EINVAL;
0546 
0547         /* ClearFeature(Halt) may need delayed status */
0548         if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
0549             return USB_GADGET_DELAYED_STATUS;
0550 
0551         break;
0552     default:
0553         return -EINVAL;
0554     }
0555 
0556     return 0;
0557 }
0558 
0559 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
0560         struct usb_ctrlrequest *ctrl, int set)
0561 {
0562     u32         recip;
0563     int         ret;
0564 
0565     recip = ctrl->bRequestType & USB_RECIP_MASK;
0566 
0567     switch (recip) {
0568     case USB_RECIP_DEVICE:
0569         ret = dwc3_ep0_handle_device(dwc, ctrl, set);
0570         break;
0571     case USB_RECIP_INTERFACE:
0572         ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
0573         break;
0574     case USB_RECIP_ENDPOINT:
0575         ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
0576         break;
0577     default:
0578         ret = -EINVAL;
0579     }
0580 
0581     return ret;
0582 }
0583 
0584 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
0585 {
0586     enum usb_device_state state = dwc->gadget->state;
0587     u32 addr;
0588     u32 reg;
0589 
0590     addr = le16_to_cpu(ctrl->wValue);
0591     if (addr > 127) {
0592         dev_err(dwc->dev, "invalid device address %d\n", addr);
0593         return -EINVAL;
0594     }
0595 
0596     if (state == USB_STATE_CONFIGURED) {
0597         dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
0598         return -EINVAL;
0599     }
0600 
0601     reg = dwc3_readl(dwc->regs, DWC3_DCFG);
0602     reg &= ~(DWC3_DCFG_DEVADDR_MASK);
0603     reg |= DWC3_DCFG_DEVADDR(addr);
0604     dwc3_writel(dwc->regs, DWC3_DCFG, reg);
0605 
0606     if (addr)
0607         usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
0608     else
0609         usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
0610 
0611     return 0;
0612 }
0613 
0614 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
0615 {
0616     int ret = -EINVAL;
0617 
0618     if (dwc->async_callbacks) {
0619         spin_unlock(&dwc->lock);
0620         ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
0621         spin_lock(&dwc->lock);
0622     }
0623     return ret;
0624 }
0625 
0626 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
0627 {
0628     enum usb_device_state state = dwc->gadget->state;
0629     u32 cfg;
0630     int ret;
0631     u32 reg;
0632 
0633     cfg = le16_to_cpu(ctrl->wValue);
0634 
0635     switch (state) {
0636     case USB_STATE_DEFAULT:
0637         return -EINVAL;
0638 
0639     case USB_STATE_ADDRESS:
0640         dwc3_gadget_clear_tx_fifos(dwc);
0641 
0642         ret = dwc3_ep0_delegate_req(dwc, ctrl);
0643         /* if the cfg matches and the cfg is non zero */
0644         if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
0645 
0646             /*
0647              * only change state if set_config has already
0648              * been processed. If gadget driver returns
0649              * USB_GADGET_DELAYED_STATUS, we will wait
0650              * to change the state on the next usb_ep_queue()
0651              */
0652             if (ret == 0)
0653                 usb_gadget_set_state(dwc->gadget,
0654                         USB_STATE_CONFIGURED);
0655 
0656             /*
0657              * Enable transition to U1/U2 state when
0658              * nothing is pending from application.
0659              */
0660             reg = dwc3_readl(dwc->regs, DWC3_DCTL);
0661             if (!dwc->dis_u1_entry_quirk)
0662                 reg |= DWC3_DCTL_ACCEPTU1ENA;
0663             if (!dwc->dis_u2_entry_quirk)
0664                 reg |= DWC3_DCTL_ACCEPTU2ENA;
0665             dwc3_writel(dwc->regs, DWC3_DCTL, reg);
0666         }
0667         break;
0668 
0669     case USB_STATE_CONFIGURED:
0670         ret = dwc3_ep0_delegate_req(dwc, ctrl);
0671         if (!cfg && !ret)
0672             usb_gadget_set_state(dwc->gadget,
0673                     USB_STATE_ADDRESS);
0674         break;
0675     default:
0676         ret = -EINVAL;
0677     }
0678     return ret;
0679 }
0680 
0681 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
0682 {
0683     struct dwc3_ep  *dep = to_dwc3_ep(ep);
0684     struct dwc3 *dwc = dep->dwc;
0685 
0686     u32     param = 0;
0687     u32     reg;
0688 
0689     struct timing {
0690         u8  u1sel;
0691         u8  u1pel;
0692         __le16  u2sel;
0693         __le16  u2pel;
0694     } __packed timing;
0695 
0696     int     ret;
0697 
0698     memcpy(&timing, req->buf, sizeof(timing));
0699 
0700     dwc->u1sel = timing.u1sel;
0701     dwc->u1pel = timing.u1pel;
0702     dwc->u2sel = le16_to_cpu(timing.u2sel);
0703     dwc->u2pel = le16_to_cpu(timing.u2pel);
0704 
0705     reg = dwc3_readl(dwc->regs, DWC3_DCTL);
0706     if (reg & DWC3_DCTL_INITU2ENA)
0707         param = dwc->u2pel;
0708     if (reg & DWC3_DCTL_INITU1ENA)
0709         param = dwc->u1pel;
0710 
0711     /*
0712      * According to Synopsys Databook, if parameter is
0713      * greater than 125, a value of zero should be
0714      * programmed in the register.
0715      */
0716     if (param > 125)
0717         param = 0;
0718 
0719     /* now that we have the time, issue DGCMD Set Sel */
0720     ret = dwc3_send_gadget_generic_command(dwc,
0721             DWC3_DGCMD_SET_PERIODIC_PAR, param);
0722     WARN_ON(ret < 0);
0723 }
0724 
0725 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
0726 {
0727     struct dwc3_ep  *dep;
0728     enum usb_device_state state = dwc->gadget->state;
0729     u16     wLength;
0730 
0731     if (state == USB_STATE_DEFAULT)
0732         return -EINVAL;
0733 
0734     wLength = le16_to_cpu(ctrl->wLength);
0735 
0736     if (wLength != 6) {
0737         dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
0738                 wLength);
0739         return -EINVAL;
0740     }
0741 
0742     /*
0743      * To handle Set SEL we need to receive 6 bytes from Host. So let's
0744      * queue a usb_request for 6 bytes.
0745      *
0746      * Remember, though, this controller can't handle non-wMaxPacketSize
0747      * aligned transfers on the OUT direction, so we queue a request for
0748      * wMaxPacketSize instead.
0749      */
0750     dep = dwc->eps[0];
0751     dwc->ep0_usb_req.dep = dep;
0752     dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
0753     dwc->ep0_usb_req.request.buf = dwc->setup_buf;
0754     dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
0755 
0756     return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
0757 }
0758 
0759 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
0760 {
0761     u16     wLength;
0762     u16     wValue;
0763     u16     wIndex;
0764 
0765     wValue = le16_to_cpu(ctrl->wValue);
0766     wLength = le16_to_cpu(ctrl->wLength);
0767     wIndex = le16_to_cpu(ctrl->wIndex);
0768 
0769     if (wIndex || wLength)
0770         return -EINVAL;
0771 
0772     dwc->gadget->isoch_delay = wValue;
0773 
0774     return 0;
0775 }
0776 
0777 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
0778 {
0779     int ret;
0780 
0781     switch (ctrl->bRequest) {
0782     case USB_REQ_GET_STATUS:
0783         ret = dwc3_ep0_handle_status(dwc, ctrl);
0784         break;
0785     case USB_REQ_CLEAR_FEATURE:
0786         ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
0787         break;
0788     case USB_REQ_SET_FEATURE:
0789         ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
0790         break;
0791     case USB_REQ_SET_ADDRESS:
0792         ret = dwc3_ep0_set_address(dwc, ctrl);
0793         break;
0794     case USB_REQ_SET_CONFIGURATION:
0795         ret = dwc3_ep0_set_config(dwc, ctrl);
0796         break;
0797     case USB_REQ_SET_SEL:
0798         ret = dwc3_ep0_set_sel(dwc, ctrl);
0799         break;
0800     case USB_REQ_SET_ISOCH_DELAY:
0801         ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
0802         break;
0803     default:
0804         ret = dwc3_ep0_delegate_req(dwc, ctrl);
0805         break;
0806     }
0807 
0808     return ret;
0809 }
0810 
0811 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
0812         const struct dwc3_event_depevt *event)
0813 {
0814     struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
0815     int ret = -EINVAL;
0816     u32 len;
0817 
0818     if (!dwc->gadget_driver || !dwc->connected)
0819         goto out;
0820 
0821     trace_dwc3_ctrl_req(ctrl);
0822 
0823     len = le16_to_cpu(ctrl->wLength);
0824     if (!len) {
0825         dwc->three_stage_setup = false;
0826         dwc->ep0_expect_in = false;
0827         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
0828     } else {
0829         dwc->three_stage_setup = true;
0830         dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
0831         dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
0832     }
0833 
0834     if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
0835         ret = dwc3_ep0_std_request(dwc, ctrl);
0836     else
0837         ret = dwc3_ep0_delegate_req(dwc, ctrl);
0838 
0839     if (ret == USB_GADGET_DELAYED_STATUS)
0840         dwc->delayed_status = true;
0841 
0842 out:
0843     if (ret < 0)
0844         dwc3_ep0_stall_and_restart(dwc);
0845 }
0846 
0847 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
0848         const struct dwc3_event_depevt *event)
0849 {
0850     struct dwc3_request *r;
0851     struct usb_request  *ur;
0852     struct dwc3_trb     *trb;
0853     struct dwc3_ep      *ep0;
0854     u32         transferred = 0;
0855     u32         status;
0856     u32         length;
0857     u8          epnum;
0858 
0859     epnum = event->endpoint_number;
0860     ep0 = dwc->eps[0];
0861 
0862     dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
0863     trb = dwc->ep0_trb;
0864     trace_dwc3_complete_trb(ep0, trb);
0865 
0866     r = next_request(&ep0->pending_list);
0867     if (!r)
0868         return;
0869 
0870     status = DWC3_TRB_SIZE_TRBSTS(trb->size);
0871     if (status == DWC3_TRBSTS_SETUP_PENDING) {
0872         dwc->setup_packet_pending = true;
0873         if (r)
0874             dwc3_gadget_giveback(ep0, r, -ECONNRESET);
0875 
0876         return;
0877     }
0878 
0879     ur = &r->request;
0880 
0881     length = trb->size & DWC3_TRB_SIZE_MASK;
0882     transferred = ur->length - length;
0883     ur->actual += transferred;
0884 
0885     if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
0886          ur->length && ur->zero) || dwc->ep0_bounced) {
0887         trb++;
0888         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
0889         trace_dwc3_complete_trb(ep0, trb);
0890 
0891         if (r->direction)
0892             dwc->eps[1]->trb_enqueue = 0;
0893         else
0894             dwc->eps[0]->trb_enqueue = 0;
0895 
0896         dwc->ep0_bounced = false;
0897     }
0898 
0899     if ((epnum & 1) && ur->actual < ur->length)
0900         dwc3_ep0_stall_and_restart(dwc);
0901     else
0902         dwc3_gadget_giveback(ep0, r, 0);
0903 }
0904 
0905 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
0906         const struct dwc3_event_depevt *event)
0907 {
0908     struct dwc3_request *r;
0909     struct dwc3_ep      *dep;
0910     struct dwc3_trb     *trb;
0911     u32         status;
0912 
0913     dep = dwc->eps[0];
0914     trb = dwc->ep0_trb;
0915 
0916     trace_dwc3_complete_trb(dep, trb);
0917 
0918     if (!list_empty(&dep->pending_list)) {
0919         r = next_request(&dep->pending_list);
0920 
0921         dwc3_gadget_giveback(dep, r, 0);
0922     }
0923 
0924     if (dwc->test_mode) {
0925         int ret;
0926 
0927         ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
0928         if (ret < 0) {
0929             dev_err(dwc->dev, "invalid test #%d\n",
0930                     dwc->test_mode_nr);
0931             dwc3_ep0_stall_and_restart(dwc);
0932             return;
0933         }
0934     }
0935 
0936     status = DWC3_TRB_SIZE_TRBSTS(trb->size);
0937     if (status == DWC3_TRBSTS_SETUP_PENDING)
0938         dwc->setup_packet_pending = true;
0939 
0940     dwc->ep0state = EP0_SETUP_PHASE;
0941     dwc3_ep0_out_start(dwc);
0942 }
0943 
0944 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
0945             const struct dwc3_event_depevt *event)
0946 {
0947     struct dwc3_ep      *dep = dwc->eps[event->endpoint_number];
0948 
0949     dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
0950     dep->resource_index = 0;
0951     dwc->setup_packet_pending = false;
0952 
0953     switch (dwc->ep0state) {
0954     case EP0_SETUP_PHASE:
0955         dwc3_ep0_inspect_setup(dwc, event);
0956         break;
0957 
0958     case EP0_DATA_PHASE:
0959         dwc3_ep0_complete_data(dwc, event);
0960         break;
0961 
0962     case EP0_STATUS_PHASE:
0963         dwc3_ep0_complete_status(dwc, event);
0964         break;
0965     default:
0966         WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
0967     }
0968 }
0969 
0970 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
0971         struct dwc3_ep *dep, struct dwc3_request *req)
0972 {
0973     unsigned int        trb_length = 0;
0974     int         ret;
0975 
0976     req->direction = !!dep->number;
0977 
0978     if (req->request.length == 0) {
0979         if (!req->direction)
0980             trb_length = dep->endpoint.maxpacket;
0981 
0982         dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
0983                 DWC3_TRBCTL_CONTROL_DATA, false);
0984         ret = dwc3_ep0_start_trans(dep);
0985     } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
0986             && (dep->number == 0)) {
0987         u32 maxpacket;
0988         u32 rem;
0989 
0990         ret = usb_gadget_map_request_by_dev(dwc->sysdev,
0991                 &req->request, dep->number);
0992         if (ret)
0993             return;
0994 
0995         maxpacket = dep->endpoint.maxpacket;
0996         rem = req->request.length % maxpacket;
0997         dwc->ep0_bounced = true;
0998 
0999         /* prepare normal TRB */
1000         dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1001                      req->request.length,
1002                      DWC3_TRBCTL_CONTROL_DATA,
1003                      true);
1004 
1005         req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1006 
1007         /* Now prepare one extra TRB to align transfer size */
1008         dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1009                      maxpacket - rem,
1010                      DWC3_TRBCTL_CONTROL_DATA,
1011                      false);
1012         ret = dwc3_ep0_start_trans(dep);
1013     } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1014            req->request.length && req->request.zero) {
1015 
1016         ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1017                 &req->request, dep->number);
1018         if (ret)
1019             return;
1020 
1021         /* prepare normal TRB */
1022         dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1023                      req->request.length,
1024                      DWC3_TRBCTL_CONTROL_DATA,
1025                      true);
1026 
1027         req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1028 
1029         if (!req->direction)
1030             trb_length = dep->endpoint.maxpacket;
1031 
1032         /* Now prepare one extra TRB to align transfer size */
1033         dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1034                      trb_length, DWC3_TRBCTL_CONTROL_DATA,
1035                      false);
1036         ret = dwc3_ep0_start_trans(dep);
1037     } else {
1038         ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1039                 &req->request, dep->number);
1040         if (ret)
1041             return;
1042 
1043         dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1044                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1045                 false);
1046 
1047         req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1048 
1049         ret = dwc3_ep0_start_trans(dep);
1050     }
1051 
1052     WARN_ON(ret < 0);
1053 }
1054 
1055 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1056 {
1057     struct dwc3     *dwc = dep->dwc;
1058     u32         type;
1059 
1060     type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1061         : DWC3_TRBCTL_CONTROL_STATUS2;
1062 
1063     dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1064     return dwc3_ep0_start_trans(dep);
1065 }
1066 
1067 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1068 {
1069     WARN_ON(dwc3_ep0_start_control_status(dep));
1070 }
1071 
1072 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1073         const struct dwc3_event_depevt *event)
1074 {
1075     struct dwc3_ep      *dep = dwc->eps[event->endpoint_number];
1076 
1077     __dwc3_ep0_do_control_status(dwc, dep);
1078 }
1079 
1080 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1081 {
1082     unsigned int direction = !dwc->ep0_expect_in;
1083 
1084     dwc->delayed_status = false;
1085     dwc->clear_stall_protocol = 0;
1086 
1087     if (dwc->ep0state != EP0_STATUS_PHASE)
1088         return;
1089 
1090     __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1091 }
1092 
1093 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1094 {
1095     struct dwc3_gadget_ep_cmd_params params;
1096     u32         cmd;
1097     int         ret;
1098 
1099     /*
1100      * For status/DATA OUT stage, TRB will be queued on ep0 out
1101      * endpoint for which resource index is zero. Hence allow
1102      * queuing ENDXFER command for ep0 out endpoint.
1103      */
1104     if (!dep->resource_index && dep->number)
1105         return;
1106 
1107     cmd = DWC3_DEPCMD_ENDTRANSFER;
1108     cmd |= DWC3_DEPCMD_CMDIOC;
1109     cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1110     memset(&params, 0, sizeof(params));
1111     ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1112     WARN_ON_ONCE(ret);
1113     dep->resource_index = 0;
1114 }
1115 
1116 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1117         const struct dwc3_event_depevt *event)
1118 {
1119     switch (event->status) {
1120     case DEPEVT_STATUS_CONTROL_DATA:
1121         /*
1122          * We already have a DATA transfer in the controller's cache,
1123          * if we receive a XferNotReady(DATA) we will ignore it, unless
1124          * it's for the wrong direction.
1125          *
1126          * In that case, we must issue END_TRANSFER command to the Data
1127          * Phase we already have started and issue SetStall on the
1128          * control endpoint.
1129          */
1130         if (dwc->ep0_expect_in != event->endpoint_number) {
1131             struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1132 
1133             dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1134             dwc3_ep0_end_control_data(dwc, dep);
1135             dwc3_ep0_stall_and_restart(dwc);
1136             return;
1137         }
1138 
1139         break;
1140 
1141     case DEPEVT_STATUS_CONTROL_STATUS:
1142         if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1143             return;
1144 
1145         if (dwc->setup_packet_pending) {
1146             dwc3_ep0_stall_and_restart(dwc);
1147             return;
1148         }
1149 
1150         dwc->ep0state = EP0_STATUS_PHASE;
1151 
1152         if (dwc->delayed_status) {
1153             struct dwc3_ep *dep = dwc->eps[0];
1154 
1155             WARN_ON_ONCE(event->endpoint_number != 1);
1156             /*
1157              * We should handle the delay STATUS phase here if the
1158              * request for handling delay STATUS has been queued
1159              * into the list.
1160              */
1161             if (!list_empty(&dep->pending_list)) {
1162                 dwc->delayed_status = false;
1163                 usb_gadget_set_state(dwc->gadget,
1164                              USB_STATE_CONFIGURED);
1165                 dwc3_ep0_do_control_status(dwc, event);
1166             }
1167 
1168             return;
1169         }
1170 
1171         dwc3_ep0_do_control_status(dwc, event);
1172     }
1173 }
1174 
1175 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1176         const struct dwc3_event_depevt *event)
1177 {
1178     struct dwc3_ep  *dep = dwc->eps[event->endpoint_number];
1179     u8      cmd;
1180 
1181     switch (event->endpoint_event) {
1182     case DWC3_DEPEVT_XFERCOMPLETE:
1183         dwc3_ep0_xfer_complete(dwc, event);
1184         break;
1185 
1186     case DWC3_DEPEVT_XFERNOTREADY:
1187         dwc3_ep0_xfernotready(dwc, event);
1188         break;
1189 
1190     case DWC3_DEPEVT_XFERINPROGRESS:
1191     case DWC3_DEPEVT_RXTXFIFOEVT:
1192     case DWC3_DEPEVT_STREAMEVT:
1193         break;
1194     case DWC3_DEPEVT_EPCMDCMPLT:
1195         cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1196 
1197         if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1198             dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1199             dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1200         }
1201         break;
1202     }
1203 }
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