usb/dwc3/dwc3-xilinx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
0004  *
0005  * Authors: Manish Narani <manish.narani@xilinx.com>
0006  *          Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
0007  */
0008
0009 #include <linux/module.h>
0010 #include <linux/kernel.h>
0011 #include <linux/slab.h>
0012 #include <linux/clk.h>
0013 #include <linux/of.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/dma-mapping.h>
0016 #include <linux/of_gpio.h>
0017 #include <linux/of_platform.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/reset.h>
0020 #include <linux/of_address.h>
0021 #include <linux/delay.h>
0022 #include <linux/firmware/xlnx-zynqmp.h>
0023 #include <linux/io.h>
0024
0025 #include <linux/phy/phy.h>
0026
0027 /* USB phy reset mask register */
0028 #define XLNX_USB_PHY_RST_EN         0x001C
0029 #define XLNX_PHY_RST_MASK           0x1
0030
0031 /* Xilinx USB 3.0 IP Register */
0032 #define XLNX_USB_TRAFFIC_ROUTE_CONFIG       0x005C
0033 #define XLNX_USB_TRAFFIC_ROUTE_FPD      0x1
0034
0035 /* Versal USB Reset ID */
0036 #define VERSAL_USB_RESET_ID         0xC104036
0037
0038 #define XLNX_USB_FPD_PIPE_CLK           0x7c
0039 #define PIPE_CLK_DESELECT           1
0040 #define PIPE_CLK_SELECT             0
0041 #define XLNX_USB_FPD_POWER_PRSNT        0x80
0042 #define FPD_POWER_PRSNT_OPTION          BIT(0)
0043
0044 struct dwc3_xlnx {
0045     int             num_clocks;
0046     struct clk_bulk_data        *clks;
0047     struct device           *dev;
0048     void __iomem            *regs;
0049     int             (*pltfm_init)(struct dwc3_xlnx *data);
0050 };
0051
0052 static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask)
0053 {
0054     u32 reg;
0055
0056     /*
0057      * Enable or disable ULPI PHY reset from USB Controller.
0058      * This does not actually reset the phy, but just controls
0059      * whether USB controller can or cannot reset ULPI PHY.
0060      */
0061     reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN);
0062
0063     if (mask)
0064         reg &= ~XLNX_PHY_RST_MASK;
0065     else
0066         reg |= XLNX_PHY_RST_MASK;
0067
0068     writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN);
0069 }
0070
0071 static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
0072 {
0073     struct device       *dev = priv_data->dev;
0074     int         ret;
0075
0076     dwc3_xlnx_mask_phy_rst(priv_data, false);
0077
0078     /* Assert and De-assert reset */
0079     ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
0080                      PM_RESET_ACTION_ASSERT);
0081     if (ret < 0) {
0082         dev_err_probe(dev, ret, "failed to assert Reset\n");
0083         return ret;
0084     }
0085
0086     ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
0087                      PM_RESET_ACTION_RELEASE);
0088     if (ret < 0) {
0089         dev_err_probe(dev, ret, "failed to De-assert Reset\n");
0090         return ret;
0091     }
0092
0093     dwc3_xlnx_mask_phy_rst(priv_data, true);
0094
0095     return 0;
0096 }
0097
0098 static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
0099 {
0100     struct device       *dev = priv_data->dev;
0101     struct reset_control    *crst, *hibrst, *apbrst;
0102     struct gpio_desc    *reset_gpio;
0103     struct phy      *usb3_phy;
0104     int         ret = 0;
0105     u32         reg;
0106
0107     usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
0108     if (IS_ERR(usb3_phy)) {
0109         ret = PTR_ERR(usb3_phy);
0110         dev_err_probe(dev, ret,
0111                   "failed to get USB3 PHY\n");
0112         goto err;
0113     }
0114
0115     /*
0116      * The following core resets are not required unless a USB3 PHY
0117      * is used, and the subsequent register settings are not required
0118      * unless a core reset is performed (they should be set properly
0119      * by the first-stage boot loader, but may be reverted by a core
0120      * reset). They may also break the configuration if USB3 is actually
0121      * in use but the usb3-phy entry is missing from the device tree.
0122      * Therefore, skip these operations in this case.
0123      */
0124     if (!usb3_phy)
0125         goto skip_usb3_phy;
0126
0127     crst = devm_reset_control_get_exclusive(dev, "usb_crst");
0128     if (IS_ERR(crst)) {
0129         ret = PTR_ERR(crst);
0130         dev_err_probe(dev, ret,
0131                   "failed to get core reset signal\n");
0132         goto err;
0133     }
0134
0135     hibrst = devm_reset_control_get_exclusive(dev, "usb_hibrst");
0136     if (IS_ERR(hibrst)) {
0137         ret = PTR_ERR(hibrst);
0138         dev_err_probe(dev, ret,
0139                   "failed to get hibernation reset signal\n");
0140         goto err;
0141     }
0142
0143     apbrst = devm_reset_control_get_exclusive(dev, "usb_apbrst");
0144     if (IS_ERR(apbrst)) {
0145         ret = PTR_ERR(apbrst);
0146         dev_err_probe(dev, ret,
0147                   "failed to get APB reset signal\n");
0148         goto err;
0149     }
0150
0151     ret = reset_control_assert(crst);
0152     if (ret < 0) {
0153         dev_err(dev, "Failed to assert core reset\n");
0154         goto err;
0155     }
0156
0157     ret = reset_control_assert(hibrst);
0158     if (ret < 0) {
0159         dev_err(dev, "Failed to assert hibernation reset\n");
0160         goto err;
0161     }
0162
0163     ret = reset_control_assert(apbrst);
0164     if (ret < 0) {
0165         dev_err(dev, "Failed to assert APB reset\n");
0166         goto err;
0167     }
0168
0169     ret = phy_init(usb3_phy);
0170     if (ret < 0) {
0171         phy_exit(usb3_phy);
0172         goto err;
0173     }
0174
0175     ret = reset_control_deassert(apbrst);
0176     if (ret < 0) {
0177         dev_err(dev, "Failed to release APB reset\n");
0178         goto err;
0179     }
0180
0181     /* Set PIPE Power Present signal in FPD Power Present Register*/
0182     writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT);
0183
0184     /* Set the PIPE Clock Select bit in FPD PIPE Clock register */
0185     writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK);
0186
0187     ret = reset_control_deassert(crst);
0188     if (ret < 0) {
0189         dev_err(dev, "Failed to release core reset\n");
0190         goto err;
0191     }
0192
0193     ret = reset_control_deassert(hibrst);
0194     if (ret < 0) {
0195         dev_err(dev, "Failed to release hibernation reset\n");
0196         goto err;
0197     }
0198
0199     ret = phy_power_on(usb3_phy);
0200     if (ret < 0) {
0201         phy_exit(usb3_phy);
0202         goto err;
0203     }
0204
0205 skip_usb3_phy:
0206     /* ulpi reset via gpio-modepin or gpio-framework driver */
0207     reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
0208     if (IS_ERR(reset_gpio)) {
0209         return dev_err_probe(dev, PTR_ERR(reset_gpio),
0210                      "Failed to request reset GPIO\n");
0211     }
0212
0213     if (reset_gpio) {
0214         /* Toggle ulpi to reset the phy. */
0215         gpiod_set_value_cansleep(reset_gpio, 1);
0216         usleep_range(5000, 10000);
0217         gpiod_set_value_cansleep(reset_gpio, 0);
0218         usleep_range(5000, 10000);
0219     }
0220
0221     /*
0222      * This routes the USB DMA traffic to go through FPD path instead
0223      * of reaching DDR directly. This traffic routing is needed to
0224      * make SMMU and CCI work with USB DMA.
0225      */
0226     if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) {
0227         reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
0228         reg |= XLNX_USB_TRAFFIC_ROUTE_FPD;
0229         writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
0230     }
0231
0232 err:
0233     return ret;
0234 }
0235
0236 static const struct of_device_id dwc3_xlnx_of_match[] = {
0237     {
0238         .compatible = "xlnx,zynqmp-dwc3",
0239         .data = &dwc3_xlnx_init_zynqmp,
0240     },
0241     {
0242         .compatible = "xlnx,versal-dwc3",
0243         .data = &dwc3_xlnx_init_versal,
0244     },
0245     { /* Sentinel */ }
0246 };
0247 MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match);
0248
0249 static int dwc3_xlnx_probe(struct platform_device *pdev)
0250 {
0251     struct dwc3_xlnx        *priv_data;
0252     struct device           *dev = &pdev->dev;
0253     struct device_node      *np = dev->of_node;
0254     const struct of_device_id   *match;
0255     void __iomem            *regs;
0256     int             ret;
0257
0258     priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL);
0259     if (!priv_data)
0260         return -ENOMEM;
0261
0262     regs = devm_platform_ioremap_resource(pdev, 0);
0263     if (IS_ERR(regs)) {
0264         ret = PTR_ERR(regs);
0265         dev_err_probe(dev, ret, "failed to map registers\n");
0266         return ret;
0267     }
0268
0269     match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node);
0270
0271     priv_data->pltfm_init = match->data;
0272     priv_data->regs = regs;
0273     priv_data->dev = dev;
0274
0275     platform_set_drvdata(pdev, priv_data);
0276
0277     ret = devm_clk_bulk_get_all(priv_data->dev, &priv_data->clks);
0278     if (ret < 0)
0279         return ret;
0280
0281     priv_data->num_clocks = ret;
0282
0283     ret = clk_bulk_prepare_enable(priv_data->num_clocks, priv_data->clks);
0284     if (ret)
0285         return ret;
0286
0287     ret = priv_data->pltfm_init(priv_data);
0288     if (ret)
0289         goto err_clk_put;
0290
0291     ret = of_platform_populate(np, NULL, NULL, dev);
0292     if (ret)
0293         goto err_clk_put;
0294
0295     pm_runtime_set_active(dev);
0296     pm_runtime_enable(dev);
0297     pm_suspend_ignore_children(dev, false);
0298     pm_runtime_get_sync(dev);
0299
0300     return 0;
0301
0302 err_clk_put:
0303     clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
0304
0305     return ret;
0306 }
0307
0308 static int dwc3_xlnx_remove(struct platform_device *pdev)
0309 {
0310     struct dwc3_xlnx    *priv_data = platform_get_drvdata(pdev);
0311     struct device       *dev = &pdev->dev;
0312
0313     of_platform_depopulate(dev);
0314
0315     clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
0316     priv_data->num_clocks = 0;
0317
0318     pm_runtime_disable(dev);
0319     pm_runtime_put_noidle(dev);
0320     pm_runtime_set_suspended(dev);
0321
0322     return 0;
0323 }
0324
0325 static int __maybe_unused dwc3_xlnx_suspend_common(struct device *dev)
0326 {
0327     struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
0328
0329     clk_bulk_disable(priv_data->num_clocks, priv_data->clks);
0330
0331     return 0;
0332 }
0333
0334 static int __maybe_unused dwc3_xlnx_resume_common(struct device *dev)
0335 {
0336     struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
0337
0338     return clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
0339 }
0340
0341 static int __maybe_unused dwc3_xlnx_runtime_idle(struct device *dev)
0342 {
0343     pm_runtime_mark_last_busy(dev);
0344     pm_runtime_autosuspend(dev);
0345
0346     return 0;
0347 }
0348
0349 static UNIVERSAL_DEV_PM_OPS(dwc3_xlnx_dev_pm_ops, dwc3_xlnx_suspend_common,
0350                 dwc3_xlnx_resume_common, dwc3_xlnx_runtime_idle);
0351
0352 static struct platform_driver dwc3_xlnx_driver = {
0353     .probe      = dwc3_xlnx_probe,
0354     .remove     = dwc3_xlnx_remove,
0355     .driver     = {
0356         .name       = "dwc3-xilinx",
0357         .of_match_table = dwc3_xlnx_of_match,
0358         .pm     = &dwc3_xlnx_dev_pm_ops,
0359     },
0360 };
0361
0362 module_platform_driver(dwc3_xlnx_driver);
0363
0364 MODULE_LICENSE("GPL v2");
0365 MODULE_DESCRIPTION("Xilinx DWC3 controller specific glue driver");
0366 MODULE_AUTHOR("Manish Narani <manish.narani@xilinx.com>");
0367 MODULE_AUTHOR("Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>");