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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * USB Glue for Amlogic G12A SoCs
0004  *
0005  * Copyright (c) 2019 BayLibre, SAS
0006  * Author: Neil Armstrong <narmstrong@baylibre.com>
0007  */
0008 
0009 /*
0010  * The USB is organized with a glue around the DWC3 Controller IP as :
0011  * - Control registers for each USB2 Ports
0012  * - Control registers for the USB PHY layer
0013  * - SuperSpeed PHY can be enabled only if port is used
0014  * - Dynamic OTG switching with ID change interrupt
0015  */
0016 
0017 #include <linux/module.h>
0018 #include <linux/kernel.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/clk.h>
0021 #include <linux/of.h>
0022 #include <linux/of_platform.h>
0023 #include <linux/pm_runtime.h>
0024 #include <linux/regmap.h>
0025 #include <linux/bitfield.h>
0026 #include <linux/bitops.h>
0027 #include <linux/reset.h>
0028 #include <linux/phy/phy.h>
0029 #include <linux/usb/otg.h>
0030 #include <linux/usb/role.h>
0031 #include <linux/regulator/consumer.h>
0032 
0033 /* USB2 Ports Control Registers, offsets are per-port */
0034 
0035 #define U2P_REG_SIZE                        0x20
0036 
0037 #define U2P_R0                          0x0
0038     #define U2P_R0_HOST_DEVICE              BIT(0)
0039     #define U2P_R0_POWER_OK                 BIT(1)
0040     #define U2P_R0_HAST_MODE                BIT(2)
0041     #define U2P_R0_POWER_ON_RESET               BIT(3)
0042     #define U2P_R0_ID_PULLUP                BIT(4)
0043     #define U2P_R0_DRV_VBUS                 BIT(5)
0044 
0045 #define U2P_R1                          0x4
0046     #define U2P_R1_PHY_READY                BIT(0)
0047     #define U2P_R1_ID_DIG                   BIT(1)
0048     #define U2P_R1_OTG_SESSION_VALID            BIT(2)
0049     #define U2P_R1_VBUS_VALID               BIT(3)
0050 
0051 /* USB Glue Control Registers */
0052 
0053 #define G12A_GLUE_OFFSET                    0x80
0054 
0055 #define USB_R0                          0x00
0056     #define USB_R0_P30_LANE0_TX2RX_LOOPBACK         BIT(17)
0057     #define USB_R0_P30_LANE0_EXT_PCLK_REQ           BIT(18)
0058     #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK     GENMASK(28, 19)
0059     #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK       GENMASK(30, 29)
0060     #define USB_R0_U2D_ACT                  BIT(31)
0061 
0062 #define USB_R1                          0x04
0063     #define USB_R1_U3H_BIGENDIAN_GS             BIT(0)
0064     #define USB_R1_U3H_PME_ENABLE               BIT(1)
0065     #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK        GENMASK(4, 2)
0066     #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK        GENMASK(9, 7)
0067     #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK        GENMASK(13, 12)
0068     #define USB_R1_U3H_HOST_U3_PORT_DISABLE         BIT(16)
0069     #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT  BIT(17)
0070     #define USB_R1_U3H_HOST_MSI_ENABLE          BIT(18)
0071     #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK         GENMASK(24, 19)
0072     #define USB_R1_P30_PCS_TX_SWING_FULL_MASK       GENMASK(31, 25)
0073 
0074 #define USB_R2                          0x08
0075     #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK     GENMASK(25, 20)
0076     #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK       GENMASK(31, 26)
0077 
0078 #define USB_R3                          0x0c
0079     #define USB_R3_P30_SSC_ENABLE               BIT(0)
0080     #define USB_R3_P30_SSC_RANGE_MASK           GENMASK(3, 1)
0081     #define USB_R3_P30_SSC_REF_CLK_SEL_MASK         GENMASK(12, 4)
0082     #define USB_R3_P30_REF_SSP_EN               BIT(13)
0083 
0084 #define USB_R4                          0x10
0085     #define USB_R4_P21_PORT_RESET_0             BIT(0)
0086     #define USB_R4_P21_SLEEP_M0             BIT(1)
0087     #define USB_R4_MEM_PD_MASK              GENMASK(3, 2)
0088     #define USB_R4_P21_ONLY                 BIT(4)
0089 
0090 #define USB_R5                          0x14
0091     #define USB_R5_ID_DIG_SYNC              BIT(0)
0092     #define USB_R5_ID_DIG_REG               BIT(1)
0093     #define USB_R5_ID_DIG_CFG_MASK              GENMASK(3, 2)
0094     #define USB_R5_ID_DIG_EN_0              BIT(4)
0095     #define USB_R5_ID_DIG_EN_1              BIT(5)
0096     #define USB_R5_ID_DIG_CURR              BIT(6)
0097     #define USB_R5_ID_DIG_IRQ               BIT(7)
0098     #define USB_R5_ID_DIG_TH_MASK               GENMASK(15, 8)
0099     #define USB_R5_ID_DIG_CNT_MASK              GENMASK(23, 16)
0100 
0101 #define PHY_COUNT                       3
0102 #define USB2_OTG_PHY                        1
0103 
0104 static struct clk_bulk_data meson_gxl_clocks[] = {
0105     { .id = "usb_ctrl" },
0106     { .id = "ddr" },
0107 };
0108 
0109 static struct clk_bulk_data meson_g12a_clocks[] = {
0110     { .id = NULL },
0111 };
0112 
0113 static struct clk_bulk_data meson_a1_clocks[] = {
0114     { .id = "usb_ctrl" },
0115     { .id = "usb_bus" },
0116     { .id = "xtal_usb_ctrl" },
0117 };
0118 
0119 static const char * const meson_gxm_phy_names[] = {
0120     "usb2-phy0", "usb2-phy1", "usb2-phy2",
0121 };
0122 
0123 static const char * const meson_g12a_phy_names[] = {
0124     "usb2-phy0", "usb2-phy1", "usb3-phy0",
0125 };
0126 
0127 /*
0128  * Amlogic A1 has a single physical PHY, in slot 1, but still has the
0129  * two U2 PHY controls register blocks like G12A.
0130  * AXG has the similar scheme, thus needs the same tweak.
0131  * Handling the first PHY on slot 1 would need a large amount of code
0132  * changes, and the current management is generic enough to handle it
0133  * correctly when only the "usb2-phy1" phy is specified on-par with the
0134  * DT bindings.
0135  */
0136 static const char * const meson_a1_phy_names[] = {
0137     "usb2-phy0", "usb2-phy1"
0138 };
0139 
0140 struct dwc3_meson_g12a;
0141 
0142 struct dwc3_meson_g12a_drvdata {
0143     bool otg_switch_supported;
0144     bool otg_phy_host_port_disable;
0145     struct clk_bulk_data *clks;
0146     int num_clks;
0147     const char * const *phy_names;
0148     int num_phys;
0149     int (*setup_regmaps)(struct dwc3_meson_g12a *priv, void __iomem *base);
0150     int (*usb2_init_phy)(struct dwc3_meson_g12a *priv, int i,
0151                  enum phy_mode mode);
0152     int (*set_phy_mode)(struct dwc3_meson_g12a *priv, int i,
0153                 enum phy_mode mode);
0154     int (*usb_init)(struct dwc3_meson_g12a *priv);
0155     int (*usb_post_init)(struct dwc3_meson_g12a *priv);
0156 };
0157 
0158 static int dwc3_meson_gxl_setup_regmaps(struct dwc3_meson_g12a *priv,
0159                     void __iomem *base);
0160 static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv,
0161                      void __iomem *base);
0162 
0163 static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i,
0164                      enum phy_mode mode);
0165 static int dwc3_meson_gxl_usb2_init_phy(struct dwc3_meson_g12a *priv, int i,
0166                     enum phy_mode mode);
0167 
0168 static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv,
0169                     int i, enum phy_mode mode);
0170 static int dwc3_meson_gxl_set_phy_mode(struct dwc3_meson_g12a *priv,
0171                        int i, enum phy_mode mode);
0172 
0173 static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv);
0174 static int dwc3_meson_gxl_usb_init(struct dwc3_meson_g12a *priv);
0175 
0176 static int dwc3_meson_gxl_usb_post_init(struct dwc3_meson_g12a *priv);
0177 
0178 /*
0179  * For GXL and GXM SoCs:
0180  * USB Phy muxing between the DWC2 Device controller and the DWC3 Host
0181  * controller is buggy when switching from Device to Host when USB port
0182  * is unpopulated, it causes the DWC3 to hard crash.
0183  * When populated (including OTG switching with ID pin), the switch works
0184  * like a charm like on the G12A platforms.
0185  * In order to still switch from Host to Device on an USB Type-A port,
0186  * an U2_PORT_DISABLE bit has been added to disconnect the DWC3 Host
0187  * controller from the port, but when used the DWC3 controller must be
0188  * reset to recover usage of the port.
0189  */
0190 
0191 static const struct dwc3_meson_g12a_drvdata gxl_drvdata = {
0192     .otg_switch_supported = true,
0193     .otg_phy_host_port_disable = true,
0194     .clks = meson_gxl_clocks,
0195     .num_clks = ARRAY_SIZE(meson_g12a_clocks),
0196     .phy_names = meson_a1_phy_names,
0197     .num_phys = ARRAY_SIZE(meson_a1_phy_names),
0198     .setup_regmaps = dwc3_meson_gxl_setup_regmaps,
0199     .usb2_init_phy = dwc3_meson_gxl_usb2_init_phy,
0200     .set_phy_mode = dwc3_meson_gxl_set_phy_mode,
0201     .usb_init = dwc3_meson_gxl_usb_init,
0202     .usb_post_init = dwc3_meson_gxl_usb_post_init,
0203 };
0204 
0205 static const struct dwc3_meson_g12a_drvdata gxm_drvdata = {
0206     .otg_switch_supported = true,
0207     .otg_phy_host_port_disable = true,
0208     .clks = meson_gxl_clocks,
0209     .num_clks = ARRAY_SIZE(meson_g12a_clocks),
0210     .phy_names = meson_gxm_phy_names,
0211     .num_phys = ARRAY_SIZE(meson_gxm_phy_names),
0212     .setup_regmaps = dwc3_meson_gxl_setup_regmaps,
0213     .usb2_init_phy = dwc3_meson_gxl_usb2_init_phy,
0214     .set_phy_mode = dwc3_meson_gxl_set_phy_mode,
0215     .usb_init = dwc3_meson_gxl_usb_init,
0216     .usb_post_init = dwc3_meson_gxl_usb_post_init,
0217 };
0218 
0219 static const struct dwc3_meson_g12a_drvdata axg_drvdata = {
0220     .otg_switch_supported = true,
0221     .clks = meson_gxl_clocks,
0222     .num_clks = ARRAY_SIZE(meson_gxl_clocks),
0223     .phy_names = meson_a1_phy_names,
0224     .num_phys = ARRAY_SIZE(meson_a1_phy_names),
0225     .setup_regmaps = dwc3_meson_gxl_setup_regmaps,
0226     .usb2_init_phy = dwc3_meson_gxl_usb2_init_phy,
0227     .set_phy_mode = dwc3_meson_gxl_set_phy_mode,
0228     .usb_init = dwc3_meson_g12a_usb_init,
0229     .usb_post_init = dwc3_meson_gxl_usb_post_init,
0230 };
0231 
0232 static const struct dwc3_meson_g12a_drvdata g12a_drvdata = {
0233     .otg_switch_supported = true,
0234     .clks = meson_g12a_clocks,
0235     .num_clks = ARRAY_SIZE(meson_g12a_clocks),
0236     .phy_names = meson_g12a_phy_names,
0237     .num_phys = ARRAY_SIZE(meson_g12a_phy_names),
0238     .setup_regmaps = dwc3_meson_g12a_setup_regmaps,
0239     .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy,
0240     .set_phy_mode = dwc3_meson_g12a_set_phy_mode,
0241     .usb_init = dwc3_meson_g12a_usb_init,
0242 };
0243 
0244 static const struct dwc3_meson_g12a_drvdata a1_drvdata = {
0245     .otg_switch_supported = false,
0246     .clks = meson_a1_clocks,
0247     .num_clks = ARRAY_SIZE(meson_a1_clocks),
0248     .phy_names = meson_a1_phy_names,
0249     .num_phys = ARRAY_SIZE(meson_a1_phy_names),
0250     .setup_regmaps = dwc3_meson_g12a_setup_regmaps,
0251     .usb2_init_phy = dwc3_meson_g12a_usb2_init_phy,
0252     .set_phy_mode = dwc3_meson_g12a_set_phy_mode,
0253     .usb_init = dwc3_meson_g12a_usb_init,
0254 };
0255 
0256 struct dwc3_meson_g12a {
0257     struct device       *dev;
0258     struct regmap       *u2p_regmap[PHY_COUNT];
0259     struct regmap       *usb_glue_regmap;
0260     struct reset_control    *reset;
0261     struct phy      *phys[PHY_COUNT];
0262     enum usb_dr_mode    otg_mode;
0263     enum phy_mode       otg_phy_mode;
0264     unsigned int        usb2_ports;
0265     unsigned int        usb3_ports;
0266     struct regulator    *vbus;
0267     struct usb_role_switch_desc switch_desc;
0268     struct usb_role_switch  *role_switch;
0269     const struct dwc3_meson_g12a_drvdata *drvdata;
0270 };
0271 
0272 static int dwc3_meson_gxl_set_phy_mode(struct dwc3_meson_g12a *priv,
0273                      int i, enum phy_mode mode)
0274 {
0275     return phy_set_mode(priv->phys[i], mode);
0276 }
0277 
0278 static int dwc3_meson_gxl_usb2_init_phy(struct dwc3_meson_g12a *priv, int i,
0279                     enum phy_mode mode)
0280 {
0281     /* On GXL PHY must be started in device mode for DWC2 init */
0282     return priv->drvdata->set_phy_mode(priv, i,
0283                 (i == USB2_OTG_PHY) ? PHY_MODE_USB_DEVICE
0284                             : PHY_MODE_USB_HOST);
0285 }
0286 
0287 static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv,
0288                      int i, enum phy_mode mode)
0289 {
0290     if (mode == PHY_MODE_USB_HOST)
0291         regmap_update_bits(priv->u2p_regmap[i], U2P_R0,
0292                 U2P_R0_HOST_DEVICE,
0293                 U2P_R0_HOST_DEVICE);
0294     else
0295         regmap_update_bits(priv->u2p_regmap[i], U2P_R0,
0296                 U2P_R0_HOST_DEVICE, 0);
0297 
0298     return 0;
0299 }
0300 
0301 static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i,
0302                      enum phy_mode mode)
0303 {
0304     int ret;
0305 
0306     regmap_update_bits(priv->u2p_regmap[i], U2P_R0,
0307             U2P_R0_POWER_ON_RESET,
0308             U2P_R0_POWER_ON_RESET);
0309 
0310     if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) {
0311         regmap_update_bits(priv->u2p_regmap[i], U2P_R0,
0312                    U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
0313                    U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS);
0314 
0315         ret = priv->drvdata->set_phy_mode(priv, i, mode);
0316     } else
0317         ret = priv->drvdata->set_phy_mode(priv, i,
0318                           PHY_MODE_USB_HOST);
0319 
0320     if (ret)
0321         return ret;
0322 
0323     regmap_update_bits(priv->u2p_regmap[i], U2P_R0,
0324             U2P_R0_POWER_ON_RESET, 0);
0325 
0326     return 0;
0327 }
0328 
0329 static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv,
0330                      enum phy_mode mode)
0331 {
0332     int i, ret;
0333 
0334     for (i = 0; i < priv->drvdata->num_phys; ++i) {
0335         if (!priv->phys[i])
0336             continue;
0337 
0338         if (!strstr(priv->drvdata->phy_names[i], "usb2"))
0339             continue;
0340 
0341         ret = priv->drvdata->usb2_init_phy(priv, i, mode);
0342         if (ret)
0343             return ret;
0344     }
0345 
0346     return 0;
0347 }
0348 
0349 static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
0350 {
0351     regmap_update_bits(priv->usb_glue_regmap, USB_R3,
0352             USB_R3_P30_SSC_RANGE_MASK |
0353             USB_R3_P30_REF_SSP_EN,
0354             USB_R3_P30_SSC_ENABLE |
0355             FIELD_PREP(USB_R3_P30_SSC_RANGE_MASK, 2) |
0356             USB_R3_P30_REF_SSP_EN);
0357     udelay(2);
0358 
0359     regmap_update_bits(priv->usb_glue_regmap, USB_R2,
0360             USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK,
0361             FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15));
0362 
0363     regmap_update_bits(priv->usb_glue_regmap, USB_R2,
0364             USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK,
0365             FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20));
0366 
0367     udelay(2);
0368 
0369     regmap_update_bits(priv->usb_glue_regmap, USB_R1,
0370             USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT,
0371             USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT);
0372 
0373     regmap_update_bits(priv->usb_glue_regmap, USB_R1,
0374             USB_R1_P30_PCS_TX_SWING_FULL_MASK,
0375             FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
0376 }
0377 
0378 static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv,
0379                            enum phy_mode mode)
0380 {
0381     if (mode == PHY_MODE_USB_DEVICE) {
0382         if (priv->otg_mode != USB_DR_MODE_OTG &&
0383             priv->drvdata->otg_phy_host_port_disable)
0384             /* Isolate the OTG PHY port from the Host Controller */
0385             regmap_update_bits(priv->usb_glue_regmap, USB_R1,
0386                 USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK,
0387                 FIELD_PREP(USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK,
0388                        BIT(USB2_OTG_PHY)));
0389 
0390         regmap_update_bits(priv->usb_glue_regmap, USB_R0,
0391                 USB_R0_U2D_ACT, USB_R0_U2D_ACT);
0392         regmap_update_bits(priv->usb_glue_regmap, USB_R0,
0393                 USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
0394         regmap_update_bits(priv->usb_glue_regmap, USB_R4,
0395                 USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
0396     } else {
0397         if (priv->otg_mode != USB_DR_MODE_OTG &&
0398             priv->drvdata->otg_phy_host_port_disable) {
0399             regmap_update_bits(priv->usb_glue_regmap, USB_R1,
0400                 USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, 0);
0401             msleep(500);
0402         }
0403         regmap_update_bits(priv->usb_glue_regmap, USB_R0,
0404                 USB_R0_U2D_ACT, 0);
0405         regmap_update_bits(priv->usb_glue_regmap, USB_R4,
0406                 USB_R4_P21_SLEEP_M0, 0);
0407     }
0408 }
0409 
0410 static int dwc3_meson_g12a_usb_init_glue(struct dwc3_meson_g12a *priv,
0411                      enum phy_mode mode)
0412 {
0413     int ret;
0414 
0415     ret = dwc3_meson_g12a_usb2_init(priv, mode);
0416     if (ret)
0417         return ret;
0418 
0419     regmap_update_bits(priv->usb_glue_regmap, USB_R1,
0420             USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
0421             FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
0422 
0423     regmap_update_bits(priv->usb_glue_regmap, USB_R5,
0424             USB_R5_ID_DIG_EN_0,
0425             USB_R5_ID_DIG_EN_0);
0426     regmap_update_bits(priv->usb_glue_regmap, USB_R5,
0427             USB_R5_ID_DIG_EN_1,
0428             USB_R5_ID_DIG_EN_1);
0429     regmap_update_bits(priv->usb_glue_regmap, USB_R5,
0430             USB_R5_ID_DIG_TH_MASK,
0431             FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
0432 
0433     /* If we have an actual SuperSpeed port, initialize it */
0434     if (priv->usb3_ports)
0435         dwc3_meson_g12a_usb3_init(priv);
0436 
0437     dwc3_meson_g12a_usb_otg_apply_mode(priv, mode);
0438 
0439     return 0;
0440 }
0441 
0442 static const struct regmap_config phy_meson_g12a_usb_glue_regmap_conf = {
0443     .name = "usb-glue",
0444     .reg_bits = 8,
0445     .val_bits = 32,
0446     .reg_stride = 4,
0447     .max_register = USB_R5,
0448 };
0449 
0450 static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
0451 {
0452     const char *phy_name;
0453     int i;
0454 
0455     for (i = 0 ; i < priv->drvdata->num_phys ; ++i) {
0456         phy_name = priv->drvdata->phy_names[i];
0457         priv->phys[i] = devm_phy_optional_get(priv->dev, phy_name);
0458         if (!priv->phys[i])
0459             continue;
0460 
0461         if (IS_ERR(priv->phys[i]))
0462             return PTR_ERR(priv->phys[i]);
0463 
0464         if (strstr(phy_name, "usb3"))
0465             priv->usb3_ports++;
0466         else
0467             priv->usb2_ports++;
0468     }
0469 
0470     dev_info(priv->dev, "USB2 ports: %d\n", priv->usb2_ports);
0471     dev_info(priv->dev, "USB3 ports: %d\n", priv->usb3_ports);
0472 
0473     return 0;
0474 }
0475 
0476 static enum phy_mode dwc3_meson_g12a_get_id(struct dwc3_meson_g12a *priv)
0477 {
0478     u32 reg;
0479 
0480     regmap_read(priv->usb_glue_regmap, USB_R5, &reg);
0481 
0482     if (reg & (USB_R5_ID_DIG_SYNC | USB_R5_ID_DIG_REG))
0483         return PHY_MODE_USB_DEVICE;
0484 
0485     return PHY_MODE_USB_HOST;
0486 }
0487 
0488 static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv,
0489                     enum phy_mode mode)
0490 {
0491     int ret;
0492 
0493     if (!priv->drvdata->otg_switch_supported || !priv->phys[USB2_OTG_PHY])
0494         return -EINVAL;
0495 
0496     if (mode == PHY_MODE_USB_HOST)
0497         dev_info(priv->dev, "switching to Host Mode\n");
0498     else
0499         dev_info(priv->dev, "switching to Device Mode\n");
0500 
0501     if (priv->vbus) {
0502         if (mode == PHY_MODE_USB_DEVICE)
0503             ret = regulator_disable(priv->vbus);
0504         else
0505             ret = regulator_enable(priv->vbus);
0506         if (ret)
0507             return ret;
0508     }
0509 
0510     priv->otg_phy_mode = mode;
0511 
0512     ret = priv->drvdata->set_phy_mode(priv, USB2_OTG_PHY, mode);
0513     if (ret)
0514         return ret;
0515 
0516     dwc3_meson_g12a_usb_otg_apply_mode(priv, mode);
0517 
0518     return 0;
0519 }
0520 
0521 static int dwc3_meson_g12a_role_set(struct usb_role_switch *sw,
0522                     enum usb_role role)
0523 {
0524     struct dwc3_meson_g12a *priv = usb_role_switch_get_drvdata(sw);
0525     enum phy_mode mode;
0526 
0527     if (role == USB_ROLE_NONE)
0528         return 0;
0529 
0530     mode = (role == USB_ROLE_HOST) ? PHY_MODE_USB_HOST
0531                        : PHY_MODE_USB_DEVICE;
0532 
0533     if (mode == priv->otg_phy_mode)
0534         return 0;
0535 
0536     if (priv->drvdata->otg_phy_host_port_disable)
0537         dev_warn_once(priv->dev, "Broken manual OTG switch\n");
0538 
0539     return dwc3_meson_g12a_otg_mode_set(priv, mode);
0540 }
0541 
0542 static enum usb_role dwc3_meson_g12a_role_get(struct usb_role_switch *sw)
0543 {
0544     struct dwc3_meson_g12a *priv = usb_role_switch_get_drvdata(sw);
0545 
0546     return priv->otg_phy_mode == PHY_MODE_USB_HOST ?
0547         USB_ROLE_HOST : USB_ROLE_DEVICE;
0548 }
0549 
0550 static irqreturn_t dwc3_meson_g12a_irq_thread(int irq, void *data)
0551 {
0552     struct dwc3_meson_g12a *priv = data;
0553     enum phy_mode otg_id;
0554 
0555     otg_id = dwc3_meson_g12a_get_id(priv);
0556     if (otg_id != priv->otg_phy_mode) {
0557         if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
0558             dev_warn(priv->dev, "Failed to switch OTG mode\n");
0559     }
0560 
0561     regmap_update_bits(priv->usb_glue_regmap, USB_R5,
0562                USB_R5_ID_DIG_IRQ, 0);
0563 
0564     return IRQ_HANDLED;
0565 }
0566 
0567 static struct device *dwc3_meson_g12_find_child(struct device *dev,
0568                         const char *compatible)
0569 {
0570     struct platform_device *pdev;
0571     struct device_node *np;
0572 
0573     np = of_get_compatible_child(dev->of_node, compatible);
0574     if (!np)
0575         return NULL;
0576 
0577     pdev = of_find_device_by_node(np);
0578     of_node_put(np);
0579     if (!pdev)
0580         return NULL;
0581 
0582     return &pdev->dev;
0583 }
0584 
0585 static int dwc3_meson_g12a_otg_init(struct platform_device *pdev,
0586                     struct dwc3_meson_g12a *priv)
0587 {
0588     enum phy_mode otg_id;
0589     int ret, irq;
0590     struct device *dev = &pdev->dev;
0591 
0592     if (!priv->drvdata->otg_switch_supported)
0593         return 0;
0594 
0595     if (priv->otg_mode == USB_DR_MODE_OTG) {
0596         /* Ack irq before registering */
0597         regmap_update_bits(priv->usb_glue_regmap, USB_R5,
0598                    USB_R5_ID_DIG_IRQ, 0);
0599 
0600         irq = platform_get_irq(pdev, 0);
0601         if (irq < 0)
0602             return irq;
0603         ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
0604                         dwc3_meson_g12a_irq_thread,
0605                         IRQF_ONESHOT, pdev->name, priv);
0606         if (ret)
0607             return ret;
0608     }
0609 
0610     /* Setup OTG mode corresponding to the ID pin */
0611     if (priv->otg_mode == USB_DR_MODE_OTG) {
0612         otg_id = dwc3_meson_g12a_get_id(priv);
0613         if (otg_id != priv->otg_phy_mode) {
0614             if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
0615                 dev_warn(dev, "Failed to switch OTG mode\n");
0616         }
0617     }
0618 
0619     /* Setup role switcher */
0620     priv->switch_desc.usb2_port = dwc3_meson_g12_find_child(dev,
0621                                 "snps,dwc3");
0622     priv->switch_desc.udc = dwc3_meson_g12_find_child(dev, "snps,dwc2");
0623     priv->switch_desc.allow_userspace_control = true;
0624     priv->switch_desc.set = dwc3_meson_g12a_role_set;
0625     priv->switch_desc.get = dwc3_meson_g12a_role_get;
0626     priv->switch_desc.driver_data = priv;
0627 
0628     priv->role_switch = usb_role_switch_register(dev, &priv->switch_desc);
0629     if (IS_ERR(priv->role_switch))
0630         dev_warn(dev, "Unable to register Role Switch\n");
0631 
0632     return 0;
0633 }
0634 
0635 static int dwc3_meson_gxl_setup_regmaps(struct dwc3_meson_g12a *priv,
0636                     void __iomem *base)
0637 {
0638     /* GXL controls the PHY mode in the PHY registers unlike G12A */
0639     priv->usb_glue_regmap = devm_regmap_init_mmio(priv->dev, base,
0640                     &phy_meson_g12a_usb_glue_regmap_conf);
0641     return PTR_ERR_OR_ZERO(priv->usb_glue_regmap);
0642 }
0643 
0644 static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv,
0645                      void __iomem *base)
0646 {
0647     int i;
0648 
0649     priv->usb_glue_regmap = devm_regmap_init_mmio(priv->dev,
0650                     base + G12A_GLUE_OFFSET,
0651                     &phy_meson_g12a_usb_glue_regmap_conf);
0652     if (IS_ERR(priv->usb_glue_regmap))
0653         return PTR_ERR(priv->usb_glue_regmap);
0654 
0655     /* Create a regmap for each USB2 PHY control register set */
0656     for (i = 0; i < priv->drvdata->num_phys; i++) {
0657         struct regmap_config u2p_regmap_config = {
0658             .reg_bits = 8,
0659             .val_bits = 32,
0660             .reg_stride = 4,
0661             .max_register = U2P_R1,
0662         };
0663 
0664         if (!strstr(priv->drvdata->phy_names[i], "usb2"))
0665             continue;
0666 
0667         u2p_regmap_config.name = devm_kasprintf(priv->dev, GFP_KERNEL,
0668                             "u2p-%d", i);
0669         if (!u2p_regmap_config.name)
0670             return -ENOMEM;
0671 
0672         priv->u2p_regmap[i] = devm_regmap_init_mmio(priv->dev,
0673                         base + (i * U2P_REG_SIZE),
0674                         &u2p_regmap_config);
0675         if (IS_ERR(priv->u2p_regmap[i]))
0676             return PTR_ERR(priv->u2p_regmap[i]);
0677     }
0678 
0679     return 0;
0680 }
0681 
0682 static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
0683 {
0684     return dwc3_meson_g12a_usb_init_glue(priv, priv->otg_phy_mode);
0685 }
0686 
0687 static int dwc3_meson_gxl_usb_init(struct dwc3_meson_g12a *priv)
0688 {
0689     return dwc3_meson_g12a_usb_init_glue(priv, PHY_MODE_USB_DEVICE);
0690 }
0691 
0692 static int dwc3_meson_gxl_usb_post_init(struct dwc3_meson_g12a *priv)
0693 {
0694     int ret;
0695 
0696     ret = priv->drvdata->set_phy_mode(priv, USB2_OTG_PHY,
0697                       priv->otg_phy_mode);
0698     if (ret)
0699         return ret;
0700 
0701     dwc3_meson_g12a_usb_otg_apply_mode(priv, priv->otg_phy_mode);
0702 
0703     return 0;
0704 }
0705 
0706 static int dwc3_meson_g12a_probe(struct platform_device *pdev)
0707 {
0708     struct dwc3_meson_g12a  *priv;
0709     struct device       *dev = &pdev->dev;
0710     struct device_node  *np = dev->of_node;
0711     void __iomem *base;
0712     int ret, i;
0713 
0714     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0715     if (!priv)
0716         return -ENOMEM;
0717 
0718     base = devm_platform_ioremap_resource(pdev, 0);
0719     if (IS_ERR(base))
0720         return PTR_ERR(base);
0721 
0722     priv->drvdata = of_device_get_match_data(&pdev->dev);
0723     priv->dev = dev;
0724 
0725     priv->vbus = devm_regulator_get_optional(dev, "vbus");
0726     if (IS_ERR(priv->vbus)) {
0727         if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
0728             return PTR_ERR(priv->vbus);
0729         priv->vbus = NULL;
0730     }
0731 
0732     ret = devm_clk_bulk_get(dev,
0733                 priv->drvdata->num_clks,
0734                 priv->drvdata->clks);
0735     if (ret)
0736         return ret;
0737 
0738     ret = clk_bulk_prepare_enable(priv->drvdata->num_clks,
0739                       priv->drvdata->clks);
0740     if (ret)
0741         return ret;
0742 
0743     platform_set_drvdata(pdev, priv);
0744 
0745     priv->reset = devm_reset_control_get_shared(dev, NULL);
0746     if (IS_ERR(priv->reset)) {
0747         ret = PTR_ERR(priv->reset);
0748         dev_err(dev, "failed to get device reset, err=%d\n", ret);
0749         goto err_disable_clks;
0750     }
0751 
0752     ret = reset_control_reset(priv->reset);
0753     if (ret)
0754         goto err_disable_clks;
0755 
0756     ret = dwc3_meson_g12a_get_phys(priv);
0757     if (ret)
0758         goto err_rearm;
0759 
0760     ret = priv->drvdata->setup_regmaps(priv, base);
0761     if (ret)
0762         goto err_rearm;
0763 
0764     if (priv->vbus) {
0765         ret = regulator_enable(priv->vbus);
0766         if (ret)
0767             goto err_rearm;
0768     }
0769 
0770     /* Get dr_mode */
0771     priv->otg_mode = usb_get_dr_mode(dev);
0772 
0773     if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
0774         priv->otg_phy_mode = PHY_MODE_USB_DEVICE;
0775     else
0776         priv->otg_phy_mode = PHY_MODE_USB_HOST;
0777 
0778     ret = priv->drvdata->usb_init(priv);
0779     if (ret)
0780         goto err_disable_regulator;
0781 
0782     /* Init PHYs */
0783     for (i = 0 ; i < PHY_COUNT ; ++i) {
0784         ret = phy_init(priv->phys[i]);
0785         if (ret)
0786             goto err_disable_regulator;
0787     }
0788 
0789     /* Set PHY Power */
0790     for (i = 0 ; i < PHY_COUNT ; ++i) {
0791         ret = phy_power_on(priv->phys[i]);
0792         if (ret)
0793             goto err_phys_exit;
0794     }
0795 
0796     if (priv->drvdata->usb_post_init) {
0797         ret = priv->drvdata->usb_post_init(priv);
0798         if (ret)
0799             goto err_phys_power;
0800     }
0801 
0802     ret = of_platform_populate(np, NULL, NULL, dev);
0803     if (ret)
0804         goto err_phys_power;
0805 
0806     ret = dwc3_meson_g12a_otg_init(pdev, priv);
0807     if (ret)
0808         goto err_phys_power;
0809 
0810     pm_runtime_set_active(dev);
0811     pm_runtime_enable(dev);
0812     pm_runtime_get_sync(dev);
0813 
0814     return 0;
0815 
0816 err_phys_power:
0817     for (i = 0 ; i < PHY_COUNT ; ++i)
0818         phy_power_off(priv->phys[i]);
0819 
0820 err_phys_exit:
0821     for (i = 0 ; i < PHY_COUNT ; ++i)
0822         phy_exit(priv->phys[i]);
0823 
0824 err_disable_regulator:
0825     if (priv->vbus)
0826         regulator_disable(priv->vbus);
0827 
0828 err_rearm:
0829     reset_control_rearm(priv->reset);
0830 
0831 err_disable_clks:
0832     clk_bulk_disable_unprepare(priv->drvdata->num_clks,
0833                    priv->drvdata->clks);
0834 
0835     return ret;
0836 }
0837 
0838 static int dwc3_meson_g12a_remove(struct platform_device *pdev)
0839 {
0840     struct dwc3_meson_g12a *priv = platform_get_drvdata(pdev);
0841     struct device *dev = &pdev->dev;
0842     int i;
0843 
0844     if (priv->drvdata->otg_switch_supported)
0845         usb_role_switch_unregister(priv->role_switch);
0846 
0847     of_platform_depopulate(dev);
0848 
0849     for (i = 0 ; i < PHY_COUNT ; ++i) {
0850         phy_power_off(priv->phys[i]);
0851         phy_exit(priv->phys[i]);
0852     }
0853 
0854     pm_runtime_disable(dev);
0855     pm_runtime_put_noidle(dev);
0856     pm_runtime_set_suspended(dev);
0857 
0858     reset_control_rearm(priv->reset);
0859 
0860     clk_bulk_disable_unprepare(priv->drvdata->num_clks,
0861                    priv->drvdata->clks);
0862 
0863     return 0;
0864 }
0865 
0866 static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev)
0867 {
0868     struct dwc3_meson_g12a  *priv = dev_get_drvdata(dev);
0869 
0870     clk_bulk_disable_unprepare(priv->drvdata->num_clks,
0871                    priv->drvdata->clks);
0872 
0873     return 0;
0874 }
0875 
0876 static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev)
0877 {
0878     struct dwc3_meson_g12a  *priv = dev_get_drvdata(dev);
0879 
0880     return clk_bulk_prepare_enable(priv->drvdata->num_clks,
0881                        priv->drvdata->clks);
0882 }
0883 
0884 static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev)
0885 {
0886     struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
0887     int i, ret;
0888 
0889     if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
0890         ret = regulator_disable(priv->vbus);
0891         if (ret)
0892             return ret;
0893     }
0894 
0895     for (i = 0 ; i < PHY_COUNT ; ++i) {
0896         phy_power_off(priv->phys[i]);
0897         phy_exit(priv->phys[i]);
0898     }
0899 
0900     reset_control_rearm(priv->reset);
0901 
0902     return 0;
0903 }
0904 
0905 static int __maybe_unused dwc3_meson_g12a_resume(struct device *dev)
0906 {
0907     struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
0908     int i, ret;
0909 
0910     ret = reset_control_reset(priv->reset);
0911     if (ret)
0912         return ret;
0913 
0914     ret = priv->drvdata->usb_init(priv);
0915     if (ret)
0916         return ret;
0917 
0918     /* Init PHYs */
0919     for (i = 0 ; i < PHY_COUNT ; ++i) {
0920         ret = phy_init(priv->phys[i]);
0921         if (ret)
0922             return ret;
0923     }
0924 
0925     /* Set PHY Power */
0926     for (i = 0 ; i < PHY_COUNT ; ++i) {
0927         ret = phy_power_on(priv->phys[i]);
0928         if (ret)
0929             return ret;
0930     }
0931 
0932     if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
0933         ret = regulator_enable(priv->vbus);
0934         if (ret)
0935             return ret;
0936     }
0937 
0938     return 0;
0939 }
0940 
0941 static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = {
0942     SET_SYSTEM_SLEEP_PM_OPS(dwc3_meson_g12a_suspend, dwc3_meson_g12a_resume)
0943     SET_RUNTIME_PM_OPS(dwc3_meson_g12a_runtime_suspend,
0944                dwc3_meson_g12a_runtime_resume, NULL)
0945 };
0946 
0947 static const struct of_device_id dwc3_meson_g12a_match[] = {
0948     {
0949         .compatible = "amlogic,meson-gxl-usb-ctrl",
0950         .data = &gxl_drvdata,
0951     },
0952     {
0953         .compatible = "amlogic,meson-gxm-usb-ctrl",
0954         .data = &gxm_drvdata,
0955     },
0956     {
0957         .compatible = "amlogic,meson-axg-usb-ctrl",
0958         .data = &axg_drvdata,
0959     },
0960     {
0961         .compatible = "amlogic,meson-g12a-usb-ctrl",
0962         .data = &g12a_drvdata,
0963     },
0964     {
0965         .compatible = "amlogic,meson-a1-usb-ctrl",
0966         .data = &a1_drvdata,
0967     },
0968     { /* Sentinel */ }
0969 };
0970 MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match);
0971 
0972 static struct platform_driver dwc3_meson_g12a_driver = {
0973     .probe      = dwc3_meson_g12a_probe,
0974     .remove     = dwc3_meson_g12a_remove,
0975     .driver     = {
0976         .name   = "dwc3-meson-g12a",
0977         .of_match_table = dwc3_meson_g12a_match,
0978         .pm = &dwc3_meson_g12a_dev_pm_ops,
0979     },
0980 };
0981 
0982 module_platform_driver(dwc3_meson_g12a_driver);
0983 MODULE_LICENSE("GPL v2");
0984 MODULE_DESCRIPTION("Amlogic Meson G12A USB Glue Layer");
0985 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
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