Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * core.c - DesignWare USB3 DRD Controller Core file
0004  *
0005  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
0006  *
0007  * Authors: Felipe Balbi <balbi@ti.com>,
0008  *      Sebastian Andrzej Siewior <bigeasy@linutronix.de>
0009  */
0010 
0011 #include <linux/clk.h>
0012 #include <linux/version.h>
0013 #include <linux/module.h>
0014 #include <linux/kernel.h>
0015 #include <linux/slab.h>
0016 #include <linux/spinlock.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/ioport.h>
0021 #include <linux/io.h>
0022 #include <linux/list.h>
0023 #include <linux/delay.h>
0024 #include <linux/dma-mapping.h>
0025 #include <linux/of.h>
0026 #include <linux/of_graph.h>
0027 #include <linux/acpi.h>
0028 #include <linux/pinctrl/consumer.h>
0029 #include <linux/reset.h>
0030 #include <linux/bitfield.h>
0031 
0032 #include <linux/usb/ch9.h>
0033 #include <linux/usb/gadget.h>
0034 #include <linux/usb/of.h>
0035 #include <linux/usb/otg.h>
0036 
0037 #include "core.h"
0038 #include "gadget.h"
0039 #include "io.h"
0040 
0041 #include "debug.h"
0042 
0043 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
0044 
0045 /**
0046  * dwc3_get_dr_mode - Validates and sets dr_mode
0047  * @dwc: pointer to our context structure
0048  */
0049 static int dwc3_get_dr_mode(struct dwc3 *dwc)
0050 {
0051     enum usb_dr_mode mode;
0052     struct device *dev = dwc->dev;
0053     unsigned int hw_mode;
0054 
0055     if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
0056         dwc->dr_mode = USB_DR_MODE_OTG;
0057 
0058     mode = dwc->dr_mode;
0059     hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
0060 
0061     switch (hw_mode) {
0062     case DWC3_GHWPARAMS0_MODE_GADGET:
0063         if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
0064             dev_err(dev,
0065                 "Controller does not support host mode.\n");
0066             return -EINVAL;
0067         }
0068         mode = USB_DR_MODE_PERIPHERAL;
0069         break;
0070     case DWC3_GHWPARAMS0_MODE_HOST:
0071         if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
0072             dev_err(dev,
0073                 "Controller does not support device mode.\n");
0074             return -EINVAL;
0075         }
0076         mode = USB_DR_MODE_HOST;
0077         break;
0078     default:
0079         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
0080             mode = USB_DR_MODE_HOST;
0081         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
0082             mode = USB_DR_MODE_PERIPHERAL;
0083 
0084         /*
0085          * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
0086          * mode. If the controller supports DRD but the dr_mode is not
0087          * specified or set to OTG, then set the mode to peripheral.
0088          */
0089         if (mode == USB_DR_MODE_OTG && !dwc->edev &&
0090             (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
0091              !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
0092             !DWC3_VER_IS_PRIOR(DWC3, 330A))
0093             mode = USB_DR_MODE_PERIPHERAL;
0094     }
0095 
0096     if (mode != dwc->dr_mode) {
0097         dev_warn(dev,
0098              "Configuration mismatch. dr_mode forced to %s\n",
0099              mode == USB_DR_MODE_HOST ? "host" : "gadget");
0100 
0101         dwc->dr_mode = mode;
0102     }
0103 
0104     return 0;
0105 }
0106 
0107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
0108 {
0109     u32 reg;
0110 
0111     reg = dwc3_readl(dwc->regs, DWC3_GCTL);
0112     reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
0113     reg |= DWC3_GCTL_PRTCAPDIR(mode);
0114     dwc3_writel(dwc->regs, DWC3_GCTL, reg);
0115 
0116     dwc->current_dr_role = mode;
0117 }
0118 
0119 static void __dwc3_set_mode(struct work_struct *work)
0120 {
0121     struct dwc3 *dwc = work_to_dwc(work);
0122     unsigned long flags;
0123     int ret;
0124     u32 reg;
0125 
0126     mutex_lock(&dwc->mutex);
0127 
0128     pm_runtime_get_sync(dwc->dev);
0129 
0130     if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
0131         dwc3_otg_update(dwc, 0);
0132 
0133     if (!dwc->desired_dr_role)
0134         goto out;
0135 
0136     if (dwc->desired_dr_role == dwc->current_dr_role)
0137         goto out;
0138 
0139     if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
0140         goto out;
0141 
0142     switch (dwc->current_dr_role) {
0143     case DWC3_GCTL_PRTCAP_HOST:
0144         dwc3_host_exit(dwc);
0145         break;
0146     case DWC3_GCTL_PRTCAP_DEVICE:
0147         dwc3_gadget_exit(dwc);
0148         dwc3_event_buffers_cleanup(dwc);
0149         break;
0150     case DWC3_GCTL_PRTCAP_OTG:
0151         dwc3_otg_exit(dwc);
0152         spin_lock_irqsave(&dwc->lock, flags);
0153         dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
0154         spin_unlock_irqrestore(&dwc->lock, flags);
0155         dwc3_otg_update(dwc, 1);
0156         break;
0157     default:
0158         break;
0159     }
0160 
0161     /*
0162      * When current_dr_role is not set, there's no role switching.
0163      * Only perform GCTL.CoreSoftReset when there's DRD role switching.
0164      */
0165     if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
0166             DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
0167             dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
0168         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
0169         reg |= DWC3_GCTL_CORESOFTRESET;
0170         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
0171 
0172         /*
0173          * Wait for internal clocks to synchronized. DWC_usb31 and
0174          * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
0175          * keep it consistent across different IPs, let's wait up to
0176          * 100ms before clearing GCTL.CORESOFTRESET.
0177          */
0178         msleep(100);
0179 
0180         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
0181         reg &= ~DWC3_GCTL_CORESOFTRESET;
0182         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
0183     }
0184 
0185     spin_lock_irqsave(&dwc->lock, flags);
0186 
0187     dwc3_set_prtcap(dwc, dwc->desired_dr_role);
0188 
0189     spin_unlock_irqrestore(&dwc->lock, flags);
0190 
0191     switch (dwc->desired_dr_role) {
0192     case DWC3_GCTL_PRTCAP_HOST:
0193         ret = dwc3_host_init(dwc);
0194         if (ret) {
0195             dev_err(dwc->dev, "failed to initialize host\n");
0196         } else {
0197             if (dwc->usb2_phy)
0198                 otg_set_vbus(dwc->usb2_phy->otg, true);
0199             phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
0200             phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
0201             if (dwc->dis_split_quirk) {
0202                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
0203                 reg |= DWC3_GUCTL3_SPLITDISABLE;
0204                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
0205             }
0206         }
0207         break;
0208     case DWC3_GCTL_PRTCAP_DEVICE:
0209         dwc3_core_soft_reset(dwc);
0210 
0211         dwc3_event_buffers_setup(dwc);
0212 
0213         if (dwc->usb2_phy)
0214             otg_set_vbus(dwc->usb2_phy->otg, false);
0215         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
0216         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
0217 
0218         ret = dwc3_gadget_init(dwc);
0219         if (ret)
0220             dev_err(dwc->dev, "failed to initialize peripheral\n");
0221         break;
0222     case DWC3_GCTL_PRTCAP_OTG:
0223         dwc3_otg_init(dwc);
0224         dwc3_otg_update(dwc, 0);
0225         break;
0226     default:
0227         break;
0228     }
0229 
0230 out:
0231     pm_runtime_mark_last_busy(dwc->dev);
0232     pm_runtime_put_autosuspend(dwc->dev);
0233     mutex_unlock(&dwc->mutex);
0234 }
0235 
0236 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
0237 {
0238     unsigned long flags;
0239 
0240     if (dwc->dr_mode != USB_DR_MODE_OTG)
0241         return;
0242 
0243     spin_lock_irqsave(&dwc->lock, flags);
0244     dwc->desired_dr_role = mode;
0245     spin_unlock_irqrestore(&dwc->lock, flags);
0246 
0247     queue_work(system_freezable_wq, &dwc->drd_work);
0248 }
0249 
0250 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
0251 {
0252     struct dwc3     *dwc = dep->dwc;
0253     u32         reg;
0254 
0255     dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
0256             DWC3_GDBGFIFOSPACE_NUM(dep->number) |
0257             DWC3_GDBGFIFOSPACE_TYPE(type));
0258 
0259     reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
0260 
0261     return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
0262 }
0263 
0264 /**
0265  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
0266  * @dwc: pointer to our context structure
0267  */
0268 int dwc3_core_soft_reset(struct dwc3 *dwc)
0269 {
0270     u32     reg;
0271     int     retries = 1000;
0272 
0273     /*
0274      * We're resetting only the device side because, if we're in host mode,
0275      * XHCI driver will reset the host block. If dwc3 was configured for
0276      * host-only mode, then we can return early.
0277      */
0278     if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
0279         return 0;
0280 
0281     reg = dwc3_readl(dwc->regs, DWC3_DCTL);
0282     reg |= DWC3_DCTL_CSFTRST;
0283     reg &= ~DWC3_DCTL_RUN_STOP;
0284     dwc3_gadget_dctl_write_safe(dwc, reg);
0285 
0286     /*
0287      * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
0288      * is cleared only after all the clocks are synchronized. This can
0289      * take a little more than 50ms. Set the polling rate at 20ms
0290      * for 10 times instead.
0291      */
0292     if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
0293         retries = 10;
0294 
0295     do {
0296         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
0297         if (!(reg & DWC3_DCTL_CSFTRST))
0298             goto done;
0299 
0300         if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
0301             msleep(20);
0302         else
0303             udelay(1);
0304     } while (--retries);
0305 
0306     dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
0307     return -ETIMEDOUT;
0308 
0309 done:
0310     /*
0311      * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
0312      * is cleared, we must wait at least 50ms before accessing the PHY
0313      * domain (synchronization delay).
0314      */
0315     if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
0316         msleep(50);
0317 
0318     return 0;
0319 }
0320 
0321 /*
0322  * dwc3_frame_length_adjustment - Adjusts frame length if required
0323  * @dwc3: Pointer to our controller context structure
0324  */
0325 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
0326 {
0327     u32 reg;
0328     u32 dft;
0329 
0330     if (DWC3_VER_IS_PRIOR(DWC3, 250A))
0331         return;
0332 
0333     if (dwc->fladj == 0)
0334         return;
0335 
0336     reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
0337     dft = reg & DWC3_GFLADJ_30MHZ_MASK;
0338     if (dft != dwc->fladj) {
0339         reg &= ~DWC3_GFLADJ_30MHZ_MASK;
0340         reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
0341         dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
0342     }
0343 }
0344 
0345 /**
0346  * dwc3_ref_clk_period - Reference clock period configuration
0347  *      Default reference clock period depends on hardware
0348  *      configuration. For systems with reference clock that differs
0349  *      from the default, this will set clock period in DWC3_GUCTL
0350  *      register.
0351  * @dwc: Pointer to our controller context structure
0352  */
0353 static void dwc3_ref_clk_period(struct dwc3 *dwc)
0354 {
0355     unsigned long period;
0356     unsigned long fladj;
0357     unsigned long decr;
0358     unsigned long rate;
0359     u32 reg;
0360 
0361     if (dwc->ref_clk) {
0362         rate = clk_get_rate(dwc->ref_clk);
0363         if (!rate)
0364             return;
0365         period = NSEC_PER_SEC / rate;
0366     } else if (dwc->ref_clk_per) {
0367         period = dwc->ref_clk_per;
0368         rate = NSEC_PER_SEC / period;
0369     } else {
0370         return;
0371     }
0372 
0373     reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
0374     reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
0375     reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
0376     dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
0377 
0378     if (DWC3_VER_IS_PRIOR(DWC3, 250A))
0379         return;
0380 
0381     /*
0382      * The calculation below is
0383      *
0384      * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
0385      *
0386      * but rearranged for fixed-point arithmetic. The division must be
0387      * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
0388      * neither does rate * period).
0389      *
0390      * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
0391      * nanoseconds of error caused by the truncation which happened during
0392      * the division when calculating rate or period (whichever one was
0393      * derived from the other). We first calculate the relative error, then
0394      * scale it to units of 8 ppm.
0395      */
0396     fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
0397     fladj -= 125000;
0398 
0399     /*
0400      * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
0401      */
0402     decr = 480000000 / rate;
0403 
0404     reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
0405     reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
0406         &  ~DWC3_GFLADJ_240MHZDECR
0407         &  ~DWC3_GFLADJ_240MHZDECR_PLS1;
0408     reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
0409         |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
0410         |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
0411     dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
0412 }
0413 
0414 /**
0415  * dwc3_free_one_event_buffer - Frees one event buffer
0416  * @dwc: Pointer to our controller context structure
0417  * @evt: Pointer to event buffer to be freed
0418  */
0419 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
0420         struct dwc3_event_buffer *evt)
0421 {
0422     dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
0423 }
0424 
0425 /**
0426  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
0427  * @dwc: Pointer to our controller context structure
0428  * @length: size of the event buffer
0429  *
0430  * Returns a pointer to the allocated event buffer structure on success
0431  * otherwise ERR_PTR(errno).
0432  */
0433 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
0434         unsigned int length)
0435 {
0436     struct dwc3_event_buffer    *evt;
0437 
0438     evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
0439     if (!evt)
0440         return ERR_PTR(-ENOMEM);
0441 
0442     evt->dwc    = dwc;
0443     evt->length = length;
0444     evt->cache  = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
0445     if (!evt->cache)
0446         return ERR_PTR(-ENOMEM);
0447 
0448     evt->buf    = dma_alloc_coherent(dwc->sysdev, length,
0449             &evt->dma, GFP_KERNEL);
0450     if (!evt->buf)
0451         return ERR_PTR(-ENOMEM);
0452 
0453     return evt;
0454 }
0455 
0456 /**
0457  * dwc3_free_event_buffers - frees all allocated event buffers
0458  * @dwc: Pointer to our controller context structure
0459  */
0460 static void dwc3_free_event_buffers(struct dwc3 *dwc)
0461 {
0462     struct dwc3_event_buffer    *evt;
0463 
0464     evt = dwc->ev_buf;
0465     if (evt)
0466         dwc3_free_one_event_buffer(dwc, evt);
0467 }
0468 
0469 /**
0470  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
0471  * @dwc: pointer to our controller context structure
0472  * @length: size of event buffer
0473  *
0474  * Returns 0 on success otherwise negative errno. In the error case, dwc
0475  * may contain some buffers allocated but not all which were requested.
0476  */
0477 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
0478 {
0479     struct dwc3_event_buffer *evt;
0480 
0481     evt = dwc3_alloc_one_event_buffer(dwc, length);
0482     if (IS_ERR(evt)) {
0483         dev_err(dwc->dev, "can't allocate event buffer\n");
0484         return PTR_ERR(evt);
0485     }
0486     dwc->ev_buf = evt;
0487 
0488     return 0;
0489 }
0490 
0491 /**
0492  * dwc3_event_buffers_setup - setup our allocated event buffers
0493  * @dwc: pointer to our controller context structure
0494  *
0495  * Returns 0 on success otherwise negative errno.
0496  */
0497 int dwc3_event_buffers_setup(struct dwc3 *dwc)
0498 {
0499     struct dwc3_event_buffer    *evt;
0500 
0501     evt = dwc->ev_buf;
0502     evt->lpos = 0;
0503     dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
0504             lower_32_bits(evt->dma));
0505     dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
0506             upper_32_bits(evt->dma));
0507     dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
0508             DWC3_GEVNTSIZ_SIZE(evt->length));
0509     dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
0510 
0511     return 0;
0512 }
0513 
0514 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
0515 {
0516     struct dwc3_event_buffer    *evt;
0517 
0518     evt = dwc->ev_buf;
0519 
0520     evt->lpos = 0;
0521 
0522     dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
0523     dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
0524     dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
0525             | DWC3_GEVNTSIZ_SIZE(0));
0526     dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
0527 }
0528 
0529 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
0530 {
0531     if (!dwc->has_hibernation)
0532         return 0;
0533 
0534     if (!dwc->nr_scratch)
0535         return 0;
0536 
0537     dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
0538             DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
0539     if (!dwc->scratchbuf)
0540         return -ENOMEM;
0541 
0542     return 0;
0543 }
0544 
0545 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
0546 {
0547     dma_addr_t scratch_addr;
0548     u32 param;
0549     int ret;
0550 
0551     if (!dwc->has_hibernation)
0552         return 0;
0553 
0554     if (!dwc->nr_scratch)
0555         return 0;
0556 
0557      /* should never fall here */
0558     if (!WARN_ON(dwc->scratchbuf))
0559         return 0;
0560 
0561     scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
0562             dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
0563             DMA_BIDIRECTIONAL);
0564     if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
0565         dev_err(dwc->sysdev, "failed to map scratch buffer\n");
0566         ret = -EFAULT;
0567         goto err0;
0568     }
0569 
0570     dwc->scratch_addr = scratch_addr;
0571 
0572     param = lower_32_bits(scratch_addr);
0573 
0574     ret = dwc3_send_gadget_generic_command(dwc,
0575             DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
0576     if (ret < 0)
0577         goto err1;
0578 
0579     param = upper_32_bits(scratch_addr);
0580 
0581     ret = dwc3_send_gadget_generic_command(dwc,
0582             DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
0583     if (ret < 0)
0584         goto err1;
0585 
0586     return 0;
0587 
0588 err1:
0589     dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0590             DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
0591 
0592 err0:
0593     return ret;
0594 }
0595 
0596 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
0597 {
0598     if (!dwc->has_hibernation)
0599         return;
0600 
0601     if (!dwc->nr_scratch)
0602         return;
0603 
0604      /* should never fall here */
0605     if (!WARN_ON(dwc->scratchbuf))
0606         return;
0607 
0608     dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
0609             DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
0610     kfree(dwc->scratchbuf);
0611 }
0612 
0613 static void dwc3_core_num_eps(struct dwc3 *dwc)
0614 {
0615     struct dwc3_hwparams    *parms = &dwc->hwparams;
0616 
0617     dwc->num_eps = DWC3_NUM_EPS(parms);
0618 }
0619 
0620 static void dwc3_cache_hwparams(struct dwc3 *dwc)
0621 {
0622     struct dwc3_hwparams    *parms = &dwc->hwparams;
0623 
0624     parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
0625     parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
0626     parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
0627     parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
0628     parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
0629     parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
0630     parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
0631     parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
0632     parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
0633 
0634     if (DWC3_IP_IS(DWC32))
0635         parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
0636 }
0637 
0638 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
0639 {
0640     int intf;
0641     int ret = 0;
0642 
0643     intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
0644 
0645     if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
0646         (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
0647          dwc->hsphy_interface &&
0648          !strncmp(dwc->hsphy_interface, "ulpi", 4)))
0649         ret = dwc3_ulpi_init(dwc);
0650 
0651     return ret;
0652 }
0653 
0654 /**
0655  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
0656  * @dwc: Pointer to our controller context structure
0657  *
0658  * Returns 0 on success. The USB PHY interfaces are configured but not
0659  * initialized. The PHY interfaces and the PHYs get initialized together with
0660  * the core in dwc3_core_init.
0661  */
0662 static int dwc3_phy_setup(struct dwc3 *dwc)
0663 {
0664     unsigned int hw_mode;
0665     u32 reg;
0666 
0667     hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
0668 
0669     reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
0670 
0671     /*
0672      * Make sure UX_EXIT_PX is cleared as that causes issues with some
0673      * PHYs. Also, this bit is not supposed to be used in normal operation.
0674      */
0675     reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
0676 
0677     /*
0678      * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
0679      * to '0' during coreConsultant configuration. So default value
0680      * will be '0' when the core is reset. Application needs to set it
0681      * to '1' after the core initialization is completed.
0682      */
0683     if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
0684         reg |= DWC3_GUSB3PIPECTL_SUSPHY;
0685 
0686     /*
0687      * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
0688      * power-on reset, and it can be set after core initialization, which is
0689      * after device soft-reset during initialization.
0690      */
0691     if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
0692         reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
0693 
0694     if (dwc->u2ss_inp3_quirk)
0695         reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
0696 
0697     if (dwc->dis_rxdet_inp3_quirk)
0698         reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
0699 
0700     if (dwc->req_p1p2p3_quirk)
0701         reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
0702 
0703     if (dwc->del_p1p2p3_quirk)
0704         reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
0705 
0706     if (dwc->del_phy_power_chg_quirk)
0707         reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
0708 
0709     if (dwc->lfps_filter_quirk)
0710         reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
0711 
0712     if (dwc->rx_detect_poll_quirk)
0713         reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
0714 
0715     if (dwc->tx_de_emphasis_quirk)
0716         reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
0717 
0718     if (dwc->dis_u3_susphy_quirk)
0719         reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
0720 
0721     if (dwc->dis_del_phy_power_chg_quirk)
0722         reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
0723 
0724     dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
0725 
0726     reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
0727 
0728     /* Select the HS PHY interface */
0729     switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
0730     case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
0731         if (dwc->hsphy_interface &&
0732                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
0733             reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
0734             break;
0735         } else if (dwc->hsphy_interface &&
0736                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
0737             reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
0738             dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
0739         } else {
0740             /* Relying on default value. */
0741             if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
0742                 break;
0743         }
0744         fallthrough;
0745     case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
0746     default:
0747         break;
0748     }
0749 
0750     switch (dwc->hsphy_mode) {
0751     case USBPHY_INTERFACE_MODE_UTMI:
0752         reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
0753                DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
0754         reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
0755                DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
0756         break;
0757     case USBPHY_INTERFACE_MODE_UTMIW:
0758         reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
0759                DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
0760         reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
0761                DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
0762         break;
0763     default:
0764         break;
0765     }
0766 
0767     /*
0768      * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
0769      * '0' during coreConsultant configuration. So default value will
0770      * be '0' when the core is reset. Application needs to set it to
0771      * '1' after the core initialization is completed.
0772      */
0773     if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
0774         reg |= DWC3_GUSB2PHYCFG_SUSPHY;
0775 
0776     /*
0777      * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
0778      * power-on reset, and it can be set after core initialization, which is
0779      * after device soft-reset during initialization.
0780      */
0781     if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
0782         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
0783 
0784     if (dwc->dis_u2_susphy_quirk)
0785         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
0786 
0787     if (dwc->dis_enblslpm_quirk)
0788         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
0789     else
0790         reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
0791 
0792     if (dwc->dis_u2_freeclk_exists_quirk)
0793         reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
0794 
0795     dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
0796 
0797     return 0;
0798 }
0799 
0800 static int dwc3_clk_enable(struct dwc3 *dwc)
0801 {
0802     int ret;
0803 
0804     ret = clk_prepare_enable(dwc->bus_clk);
0805     if (ret)
0806         return ret;
0807 
0808     ret = clk_prepare_enable(dwc->ref_clk);
0809     if (ret)
0810         goto disable_bus_clk;
0811 
0812     ret = clk_prepare_enable(dwc->susp_clk);
0813     if (ret)
0814         goto disable_ref_clk;
0815 
0816     return 0;
0817 
0818 disable_ref_clk:
0819     clk_disable_unprepare(dwc->ref_clk);
0820 disable_bus_clk:
0821     clk_disable_unprepare(dwc->bus_clk);
0822     return ret;
0823 }
0824 
0825 static void dwc3_clk_disable(struct dwc3 *dwc)
0826 {
0827     clk_disable_unprepare(dwc->susp_clk);
0828     clk_disable_unprepare(dwc->ref_clk);
0829     clk_disable_unprepare(dwc->bus_clk);
0830 }
0831 
0832 static void dwc3_core_exit(struct dwc3 *dwc)
0833 {
0834     dwc3_event_buffers_cleanup(dwc);
0835 
0836     usb_phy_set_suspend(dwc->usb2_phy, 1);
0837     usb_phy_set_suspend(dwc->usb3_phy, 1);
0838     phy_power_off(dwc->usb2_generic_phy);
0839     phy_power_off(dwc->usb3_generic_phy);
0840 
0841     usb_phy_shutdown(dwc->usb2_phy);
0842     usb_phy_shutdown(dwc->usb3_phy);
0843     phy_exit(dwc->usb2_generic_phy);
0844     phy_exit(dwc->usb3_generic_phy);
0845 
0846     dwc3_clk_disable(dwc);
0847     reset_control_assert(dwc->reset);
0848 }
0849 
0850 static bool dwc3_core_is_valid(struct dwc3 *dwc)
0851 {
0852     u32 reg;
0853 
0854     reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
0855     dwc->ip = DWC3_GSNPS_ID(reg);
0856 
0857     /* This should read as U3 followed by revision number */
0858     if (DWC3_IP_IS(DWC3)) {
0859         dwc->revision = reg;
0860     } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
0861         dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
0862         dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
0863     } else {
0864         return false;
0865     }
0866 
0867     return true;
0868 }
0869 
0870 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
0871 {
0872     u32 hwparams4 = dwc->hwparams.hwparams4;
0873     u32 reg;
0874 
0875     reg = dwc3_readl(dwc->regs, DWC3_GCTL);
0876     reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
0877 
0878     switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
0879     case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
0880         /**
0881          * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
0882          * issue which would cause xHCI compliance tests to fail.
0883          *
0884          * Because of that we cannot enable clock gating on such
0885          * configurations.
0886          *
0887          * Refers to:
0888          *
0889          * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
0890          * SOF/ITP Mode Used
0891          */
0892         if ((dwc->dr_mode == USB_DR_MODE_HOST ||
0893                 dwc->dr_mode == USB_DR_MODE_OTG) &&
0894                 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
0895             reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
0896         else
0897             reg &= ~DWC3_GCTL_DSBLCLKGTNG;
0898         break;
0899     case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
0900         /* enable hibernation here */
0901         dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
0902 
0903         /*
0904          * REVISIT Enabling this bit so that host-mode hibernation
0905          * will work. Device-mode hibernation is not yet implemented.
0906          */
0907         reg |= DWC3_GCTL_GBLHIBERNATIONEN;
0908         break;
0909     default:
0910         /* nothing */
0911         break;
0912     }
0913 
0914     /* check if current dwc3 is on simulation board */
0915     if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
0916         dev_info(dwc->dev, "Running with FPGA optimizations\n");
0917         dwc->is_fpga = true;
0918     }
0919 
0920     WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
0921             "disable_scramble cannot be used on non-FPGA builds\n");
0922 
0923     if (dwc->disable_scramble_quirk && dwc->is_fpga)
0924         reg |= DWC3_GCTL_DISSCRAMBLE;
0925     else
0926         reg &= ~DWC3_GCTL_DISSCRAMBLE;
0927 
0928     if (dwc->u2exit_lfps_quirk)
0929         reg |= DWC3_GCTL_U2EXIT_LFPS;
0930 
0931     /*
0932      * WORKAROUND: DWC3 revisions <1.90a have a bug
0933      * where the device can fail to connect at SuperSpeed
0934      * and falls back to high-speed mode which causes
0935      * the device to enter a Connect/Disconnect loop
0936      */
0937     if (DWC3_VER_IS_PRIOR(DWC3, 190A))
0938         reg |= DWC3_GCTL_U2RSTECN;
0939 
0940     dwc3_writel(dwc->regs, DWC3_GCTL, reg);
0941 }
0942 
0943 static int dwc3_core_get_phy(struct dwc3 *dwc);
0944 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
0945 
0946 /* set global incr burst type configuration registers */
0947 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
0948 {
0949     struct device *dev = dwc->dev;
0950     /* incrx_mode : for INCR burst type. */
0951     bool incrx_mode;
0952     /* incrx_size : for size of INCRX burst. */
0953     u32 incrx_size;
0954     u32 *vals;
0955     u32 cfg;
0956     int ntype;
0957     int ret;
0958     int i;
0959 
0960     cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
0961 
0962     /*
0963      * Handle property "snps,incr-burst-type-adjustment".
0964      * Get the number of value from this property:
0965      * result <= 0, means this property is not supported.
0966      * result = 1, means INCRx burst mode supported.
0967      * result > 1, means undefined length burst mode supported.
0968      */
0969     ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
0970     if (ntype <= 0)
0971         return;
0972 
0973     vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
0974     if (!vals)
0975         return;
0976 
0977     /* Get INCR burst type, and parse it */
0978     ret = device_property_read_u32_array(dev,
0979             "snps,incr-burst-type-adjustment", vals, ntype);
0980     if (ret) {
0981         kfree(vals);
0982         dev_err(dev, "Error to get property\n");
0983         return;
0984     }
0985 
0986     incrx_size = *vals;
0987 
0988     if (ntype > 1) {
0989         /* INCRX (undefined length) burst mode */
0990         incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
0991         for (i = 1; i < ntype; i++) {
0992             if (vals[i] > incrx_size)
0993                 incrx_size = vals[i];
0994         }
0995     } else {
0996         /* INCRX burst mode */
0997         incrx_mode = INCRX_BURST_MODE;
0998     }
0999 
1000     kfree(vals);
1001 
1002     /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1003     cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1004     if (incrx_mode)
1005         cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1006     switch (incrx_size) {
1007     case 256:
1008         cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1009         break;
1010     case 128:
1011         cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1012         break;
1013     case 64:
1014         cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1015         break;
1016     case 32:
1017         cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1018         break;
1019     case 16:
1020         cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1021         break;
1022     case 8:
1023         cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1024         break;
1025     case 4:
1026         cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1027         break;
1028     case 1:
1029         break;
1030     default:
1031         dev_err(dev, "Invalid property\n");
1032         break;
1033     }
1034 
1035     dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1036 }
1037 
1038 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1039 {
1040     u32 scale;
1041     u32 reg;
1042 
1043     if (!dwc->susp_clk)
1044         return;
1045 
1046     /*
1047      * The power down scale field specifies how many suspend_clk
1048      * periods fit into a 16KHz clock period. When performing
1049      * the division, round up the remainder.
1050      *
1051      * The power down scale value is calculated using the fastest
1052      * frequency of the suspend_clk. If it isn't fixed (but within
1053      * the accuracy requirement), the driver may not know the max
1054      * rate of the suspend_clk, so only update the power down scale
1055      * if the default is less than the calculated value from
1056      * clk_get_rate() or if the default is questionably high
1057      * (3x or more) to be within the requirement.
1058      */
1059     scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1060     reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1061     if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1062         (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1063         reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1064         reg |= DWC3_GCTL_PWRDNSCALE(scale);
1065         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1066     }
1067 }
1068 
1069 /**
1070  * dwc3_core_init - Low-level initialization of DWC3 Core
1071  * @dwc: Pointer to our controller context structure
1072  *
1073  * Returns 0 on success otherwise negative errno.
1074  */
1075 static int dwc3_core_init(struct dwc3 *dwc)
1076 {
1077     unsigned int        hw_mode;
1078     u32         reg;
1079     int         ret;
1080 
1081     hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1082 
1083     /*
1084      * Write Linux Version Code to our GUID register so it's easy to figure
1085      * out which kernel version a bug was found.
1086      */
1087     dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1088 
1089     ret = dwc3_phy_setup(dwc);
1090     if (ret)
1091         goto err0;
1092 
1093     if (!dwc->ulpi_ready) {
1094         ret = dwc3_core_ulpi_init(dwc);
1095         if (ret)
1096             goto err0;
1097         dwc->ulpi_ready = true;
1098     }
1099 
1100     if (!dwc->phys_ready) {
1101         ret = dwc3_core_get_phy(dwc);
1102         if (ret)
1103             goto err0a;
1104         dwc->phys_ready = true;
1105     }
1106 
1107     usb_phy_init(dwc->usb2_phy);
1108     usb_phy_init(dwc->usb3_phy);
1109     ret = phy_init(dwc->usb2_generic_phy);
1110     if (ret < 0)
1111         goto err0a;
1112 
1113     ret = phy_init(dwc->usb3_generic_phy);
1114     if (ret < 0) {
1115         phy_exit(dwc->usb2_generic_phy);
1116         goto err0a;
1117     }
1118 
1119     ret = dwc3_core_soft_reset(dwc);
1120     if (ret)
1121         goto err1;
1122 
1123     if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1124         !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1125         if (!dwc->dis_u3_susphy_quirk) {
1126             reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1127             reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1128             dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1129         }
1130 
1131         if (!dwc->dis_u2_susphy_quirk) {
1132             reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1133             reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1134             dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1135         }
1136     }
1137 
1138     dwc3_core_setup_global_control(dwc);
1139     dwc3_core_num_eps(dwc);
1140 
1141     ret = dwc3_setup_scratch_buffers(dwc);
1142     if (ret)
1143         goto err1;
1144 
1145     /* Set power down scale of suspend_clk */
1146     dwc3_set_power_down_clk_scale(dwc);
1147 
1148     /* Adjust Frame Length */
1149     dwc3_frame_length_adjustment(dwc);
1150 
1151     /* Adjust Reference Clock Period */
1152     dwc3_ref_clk_period(dwc);
1153 
1154     dwc3_set_incr_burst_type(dwc);
1155 
1156     usb_phy_set_suspend(dwc->usb2_phy, 0);
1157     usb_phy_set_suspend(dwc->usb3_phy, 0);
1158     ret = phy_power_on(dwc->usb2_generic_phy);
1159     if (ret < 0)
1160         goto err2;
1161 
1162     ret = phy_power_on(dwc->usb3_generic_phy);
1163     if (ret < 0)
1164         goto err3;
1165 
1166     ret = dwc3_event_buffers_setup(dwc);
1167     if (ret) {
1168         dev_err(dwc->dev, "failed to setup event buffers\n");
1169         goto err4;
1170     }
1171 
1172     /*
1173      * ENDXFER polling is available on version 3.10a and later of
1174      * the DWC_usb3 controller. It is NOT available in the
1175      * DWC_usb31 controller.
1176      */
1177     if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1178         reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1179         reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1180         dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1181     }
1182 
1183     if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1184         reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1185 
1186         /*
1187          * Enable hardware control of sending remote wakeup
1188          * in HS when the device is in the L1 state.
1189          */
1190         if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1191             reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1192 
1193         /*
1194          * Decouple USB 2.0 L1 & L2 events which will allow for
1195          * gadget driver to only receive U3/L2 suspend & wakeup
1196          * events and prevent the more frequent L1 LPM transitions
1197          * from interrupting the driver.
1198          */
1199         if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1200             reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1201 
1202         if (dwc->dis_tx_ipgap_linecheck_quirk)
1203             reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1204 
1205         if (dwc->parkmode_disable_ss_quirk)
1206             reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1207 
1208         if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1209             (dwc->maximum_speed == USB_SPEED_HIGH ||
1210              dwc->maximum_speed == USB_SPEED_FULL))
1211             reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1212 
1213         dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1214     }
1215 
1216     if (dwc->dr_mode == USB_DR_MODE_HOST ||
1217         dwc->dr_mode == USB_DR_MODE_OTG) {
1218         reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1219 
1220         /*
1221          * Enable Auto retry Feature to make the controller operating in
1222          * Host mode on seeing transaction errors(CRC errors or internal
1223          * overrun scenerios) on IN transfers to reply to the device
1224          * with a non-terminating retry ACK (i.e, an ACK transcation
1225          * packet with Retry=1 & Nump != 0)
1226          */
1227         reg |= DWC3_GUCTL_HSTINAUTORETRY;
1228 
1229         dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1230     }
1231 
1232     /*
1233      * Must config both number of packets and max burst settings to enable
1234      * RX and/or TX threshold.
1235      */
1236     if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1237         u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1238         u8 rx_maxburst = dwc->rx_max_burst_prd;
1239         u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1240         u8 tx_maxburst = dwc->tx_max_burst_prd;
1241 
1242         if (rx_thr_num && rx_maxburst) {
1243             reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1244             reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1245 
1246             reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1247             reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1248 
1249             reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1250             reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1251 
1252             dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1253         }
1254 
1255         if (tx_thr_num && tx_maxburst) {
1256             reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1257             reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1258 
1259             reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1260             reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1261 
1262             reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1263             reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1264 
1265             dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1266         }
1267     }
1268 
1269     return 0;
1270 
1271 err4:
1272     phy_power_off(dwc->usb3_generic_phy);
1273 
1274 err3:
1275     phy_power_off(dwc->usb2_generic_phy);
1276 
1277 err2:
1278     usb_phy_set_suspend(dwc->usb2_phy, 1);
1279     usb_phy_set_suspend(dwc->usb3_phy, 1);
1280 
1281 err1:
1282     usb_phy_shutdown(dwc->usb2_phy);
1283     usb_phy_shutdown(dwc->usb3_phy);
1284     phy_exit(dwc->usb2_generic_phy);
1285     phy_exit(dwc->usb3_generic_phy);
1286 
1287 err0a:
1288     dwc3_ulpi_exit(dwc);
1289 
1290 err0:
1291     return ret;
1292 }
1293 
1294 static int dwc3_core_get_phy(struct dwc3 *dwc)
1295 {
1296     struct device       *dev = dwc->dev;
1297     struct device_node  *node = dev->of_node;
1298     int ret;
1299 
1300     if (node) {
1301         dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1302         dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1303     } else {
1304         dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1305         dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1306     }
1307 
1308     if (IS_ERR(dwc->usb2_phy)) {
1309         ret = PTR_ERR(dwc->usb2_phy);
1310         if (ret == -ENXIO || ret == -ENODEV)
1311             dwc->usb2_phy = NULL;
1312         else
1313             return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1314     }
1315 
1316     if (IS_ERR(dwc->usb3_phy)) {
1317         ret = PTR_ERR(dwc->usb3_phy);
1318         if (ret == -ENXIO || ret == -ENODEV)
1319             dwc->usb3_phy = NULL;
1320         else
1321             return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1322     }
1323 
1324     dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1325     if (IS_ERR(dwc->usb2_generic_phy)) {
1326         ret = PTR_ERR(dwc->usb2_generic_phy);
1327         if (ret == -ENOSYS || ret == -ENODEV)
1328             dwc->usb2_generic_phy = NULL;
1329         else
1330             return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1331     }
1332 
1333     dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1334     if (IS_ERR(dwc->usb3_generic_phy)) {
1335         ret = PTR_ERR(dwc->usb3_generic_phy);
1336         if (ret == -ENOSYS || ret == -ENODEV)
1337             dwc->usb3_generic_phy = NULL;
1338         else
1339             return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1340     }
1341 
1342     return 0;
1343 }
1344 
1345 static int dwc3_core_init_mode(struct dwc3 *dwc)
1346 {
1347     struct device *dev = dwc->dev;
1348     int ret;
1349 
1350     switch (dwc->dr_mode) {
1351     case USB_DR_MODE_PERIPHERAL:
1352         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1353 
1354         if (dwc->usb2_phy)
1355             otg_set_vbus(dwc->usb2_phy->otg, false);
1356         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1357         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1358 
1359         ret = dwc3_gadget_init(dwc);
1360         if (ret)
1361             return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1362         break;
1363     case USB_DR_MODE_HOST:
1364         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1365 
1366         if (dwc->usb2_phy)
1367             otg_set_vbus(dwc->usb2_phy->otg, true);
1368         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1369         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1370 
1371         ret = dwc3_host_init(dwc);
1372         if (ret)
1373             return dev_err_probe(dev, ret, "failed to initialize host\n");
1374         break;
1375     case USB_DR_MODE_OTG:
1376         INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1377         ret = dwc3_drd_init(dwc);
1378         if (ret)
1379             return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1380         break;
1381     default:
1382         dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1383         return -EINVAL;
1384     }
1385 
1386     return 0;
1387 }
1388 
1389 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1390 {
1391     switch (dwc->dr_mode) {
1392     case USB_DR_MODE_PERIPHERAL:
1393         dwc3_gadget_exit(dwc);
1394         break;
1395     case USB_DR_MODE_HOST:
1396         dwc3_host_exit(dwc);
1397         break;
1398     case USB_DR_MODE_OTG:
1399         dwc3_drd_exit(dwc);
1400         break;
1401     default:
1402         /* do nothing */
1403         break;
1404     }
1405 
1406     /* de-assert DRVVBUS for HOST and OTG mode */
1407     dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1408 }
1409 
1410 static void dwc3_get_properties(struct dwc3 *dwc)
1411 {
1412     struct device       *dev = dwc->dev;
1413     u8          lpm_nyet_threshold;
1414     u8          tx_de_emphasis;
1415     u8          hird_threshold;
1416     u8          rx_thr_num_pkt_prd = 0;
1417     u8          rx_max_burst_prd = 0;
1418     u8          tx_thr_num_pkt_prd = 0;
1419     u8          tx_max_burst_prd = 0;
1420     u8          tx_fifo_resize_max_num;
1421     const char      *usb_psy_name;
1422     int         ret;
1423 
1424     /* default to highest possible threshold */
1425     lpm_nyet_threshold = 0xf;
1426 
1427     /* default to -3.5dB de-emphasis */
1428     tx_de_emphasis = 1;
1429 
1430     /*
1431      * default to assert utmi_sleep_n and use maximum allowed HIRD
1432      * threshold value of 0b1100
1433      */
1434     hird_threshold = 12;
1435 
1436     /*
1437      * default to a TXFIFO size large enough to fit 6 max packets.  This
1438      * allows for systems with larger bus latencies to have some headroom
1439      * for endpoints that have a large bMaxBurst value.
1440      */
1441     tx_fifo_resize_max_num = 6;
1442 
1443     dwc->maximum_speed = usb_get_maximum_speed(dev);
1444     dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1445     dwc->dr_mode = usb_get_dr_mode(dev);
1446     dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1447 
1448     dwc->sysdev_is_parent = device_property_read_bool(dev,
1449                 "linux,sysdev_is_parent");
1450     if (dwc->sysdev_is_parent)
1451         dwc->sysdev = dwc->dev->parent;
1452     else
1453         dwc->sysdev = dwc->dev;
1454 
1455     ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1456     if (ret >= 0) {
1457         dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1458         if (!dwc->usb_psy)
1459             dev_err(dev, "couldn't get usb power supply\n");
1460     }
1461 
1462     dwc->has_lpm_erratum = device_property_read_bool(dev,
1463                 "snps,has-lpm-erratum");
1464     device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1465                 &lpm_nyet_threshold);
1466     dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1467                 "snps,is-utmi-l1-suspend");
1468     device_property_read_u8(dev, "snps,hird-threshold",
1469                 &hird_threshold);
1470     dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1471                 "snps,dis-start-transfer-quirk");
1472     dwc->usb3_lpm_capable = device_property_read_bool(dev,
1473                 "snps,usb3_lpm_capable");
1474     dwc->usb2_lpm_disable = device_property_read_bool(dev,
1475                 "snps,usb2-lpm-disable");
1476     dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1477                 "snps,usb2-gadget-lpm-disable");
1478     device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1479                 &rx_thr_num_pkt_prd);
1480     device_property_read_u8(dev, "snps,rx-max-burst-prd",
1481                 &rx_max_burst_prd);
1482     device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1483                 &tx_thr_num_pkt_prd);
1484     device_property_read_u8(dev, "snps,tx-max-burst-prd",
1485                 &tx_max_burst_prd);
1486     dwc->do_fifo_resize = device_property_read_bool(dev,
1487                             "tx-fifo-resize");
1488     if (dwc->do_fifo_resize)
1489         device_property_read_u8(dev, "tx-fifo-max-num",
1490                     &tx_fifo_resize_max_num);
1491 
1492     dwc->disable_scramble_quirk = device_property_read_bool(dev,
1493                 "snps,disable_scramble_quirk");
1494     dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1495                 "snps,u2exit_lfps_quirk");
1496     dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1497                 "snps,u2ss_inp3_quirk");
1498     dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1499                 "snps,req_p1p2p3_quirk");
1500     dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1501                 "snps,del_p1p2p3_quirk");
1502     dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1503                 "snps,del_phy_power_chg_quirk");
1504     dwc->lfps_filter_quirk = device_property_read_bool(dev,
1505                 "snps,lfps_filter_quirk");
1506     dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1507                 "snps,rx_detect_poll_quirk");
1508     dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1509                 "snps,dis_u3_susphy_quirk");
1510     dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1511                 "snps,dis_u2_susphy_quirk");
1512     dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1513                 "snps,dis_enblslpm_quirk");
1514     dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1515                 "snps,dis-u1-entry-quirk");
1516     dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1517                 "snps,dis-u2-entry-quirk");
1518     dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1519                 "snps,dis_rxdet_inp3_quirk");
1520     dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1521                 "snps,dis-u2-freeclk-exists-quirk");
1522     dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1523                 "snps,dis-del-phy-power-chg-quirk");
1524     dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1525                 "snps,dis-tx-ipgap-linecheck-quirk");
1526     dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1527                 "snps,parkmode-disable-ss-quirk");
1528 
1529     dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1530                 "snps,tx_de_emphasis_quirk");
1531     device_property_read_u8(dev, "snps,tx_de_emphasis",
1532                 &tx_de_emphasis);
1533     device_property_read_string(dev, "snps,hsphy_interface",
1534                     &dwc->hsphy_interface);
1535     device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1536                  &dwc->fladj);
1537     device_property_read_u32(dev, "snps,ref-clock-period-ns",
1538                  &dwc->ref_clk_per);
1539 
1540     dwc->dis_metastability_quirk = device_property_read_bool(dev,
1541                 "snps,dis_metastability_quirk");
1542 
1543     dwc->dis_split_quirk = device_property_read_bool(dev,
1544                 "snps,dis-split-quirk");
1545 
1546     dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1547     dwc->tx_de_emphasis = tx_de_emphasis;
1548 
1549     dwc->hird_threshold = hird_threshold;
1550 
1551     dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1552     dwc->rx_max_burst_prd = rx_max_burst_prd;
1553 
1554     dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1555     dwc->tx_max_burst_prd = tx_max_burst_prd;
1556 
1557     dwc->imod_interval = 0;
1558 
1559     dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1560 }
1561 
1562 /* check whether the core supports IMOD */
1563 bool dwc3_has_imod(struct dwc3 *dwc)
1564 {
1565     return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1566         DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1567         DWC3_IP_IS(DWC32);
1568 }
1569 
1570 static void dwc3_check_params(struct dwc3 *dwc)
1571 {
1572     struct device *dev = dwc->dev;
1573     unsigned int hwparam_gen =
1574         DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1575 
1576     /* Check for proper value of imod_interval */
1577     if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1578         dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1579         dwc->imod_interval = 0;
1580     }
1581 
1582     /*
1583      * Workaround for STAR 9000961433 which affects only version
1584      * 3.00a of the DWC_usb3 core. This prevents the controller
1585      * interrupt from being masked while handling events. IMOD
1586      * allows us to work around this issue. Enable it for the
1587      * affected version.
1588      */
1589     if (!dwc->imod_interval &&
1590         DWC3_VER_IS(DWC3, 300A))
1591         dwc->imod_interval = 1;
1592 
1593     /* Check the maximum_speed parameter */
1594     switch (dwc->maximum_speed) {
1595     case USB_SPEED_FULL:
1596     case USB_SPEED_HIGH:
1597         break;
1598     case USB_SPEED_SUPER:
1599         if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1600             dev_warn(dev, "UDC doesn't support Gen 1\n");
1601         break;
1602     case USB_SPEED_SUPER_PLUS:
1603         if ((DWC3_IP_IS(DWC32) &&
1604              hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1605             (!DWC3_IP_IS(DWC32) &&
1606              hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1607             dev_warn(dev, "UDC doesn't support SSP\n");
1608         break;
1609     default:
1610         dev_err(dev, "invalid maximum_speed parameter %d\n",
1611             dwc->maximum_speed);
1612         fallthrough;
1613     case USB_SPEED_UNKNOWN:
1614         switch (hwparam_gen) {
1615         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1616             dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1617             break;
1618         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1619             if (DWC3_IP_IS(DWC32))
1620                 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1621             else
1622                 dwc->maximum_speed = USB_SPEED_SUPER;
1623             break;
1624         case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1625             dwc->maximum_speed = USB_SPEED_HIGH;
1626             break;
1627         default:
1628             dwc->maximum_speed = USB_SPEED_SUPER;
1629             break;
1630         }
1631         break;
1632     }
1633 
1634     /*
1635      * Currently the controller does not have visibility into the HW
1636      * parameter to determine the maximum number of lanes the HW supports.
1637      * If the number of lanes is not specified in the device property, then
1638      * set the default to support dual-lane for DWC_usb32 and single-lane
1639      * for DWC_usb31 for super-speed-plus.
1640      */
1641     if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1642         switch (dwc->max_ssp_rate) {
1643         case USB_SSP_GEN_2x1:
1644             if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1645                 dev_warn(dev, "UDC only supports Gen 1\n");
1646             break;
1647         case USB_SSP_GEN_1x2:
1648         case USB_SSP_GEN_2x2:
1649             if (DWC3_IP_IS(DWC31))
1650                 dev_warn(dev, "UDC only supports single lane\n");
1651             break;
1652         case USB_SSP_GEN_UNKNOWN:
1653         default:
1654             switch (hwparam_gen) {
1655             case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1656                 if (DWC3_IP_IS(DWC32))
1657                     dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1658                 else
1659                     dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1660                 break;
1661             case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1662                 if (DWC3_IP_IS(DWC32))
1663                     dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1664                 break;
1665             }
1666             break;
1667         }
1668     }
1669 }
1670 
1671 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1672 {
1673     struct device *dev = dwc->dev;
1674     struct device_node *np_phy;
1675     struct extcon_dev *edev = NULL;
1676     const char *name;
1677 
1678     if (device_property_read_bool(dev, "extcon"))
1679         return extcon_get_edev_by_phandle(dev, 0);
1680 
1681     /*
1682      * Device tree platforms should get extcon via phandle.
1683      * On ACPI platforms, we get the name from a device property.
1684      * This device property is for kernel internal use only and
1685      * is expected to be set by the glue code.
1686      */
1687     if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1688         return extcon_get_extcon_dev(name);
1689 
1690     /*
1691      * Try to get an extcon device from the USB PHY controller's "port"
1692      * node. Check if it has the "port" node first, to avoid printing the
1693      * error message from underlying code, as it's a valid case: extcon
1694      * device (and "port" node) may be missing in case of "usb-role-switch"
1695      * or OTG mode.
1696      */
1697     np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1698     if (of_graph_is_present(np_phy)) {
1699         struct device_node *np_conn;
1700 
1701         np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1702         if (np_conn)
1703             edev = extcon_find_edev_by_node(np_conn);
1704         of_node_put(np_conn);
1705     }
1706     of_node_put(np_phy);
1707 
1708     return edev;
1709 }
1710 
1711 static int dwc3_probe(struct platform_device *pdev)
1712 {
1713     struct device       *dev = &pdev->dev;
1714     struct resource     *res, dwc_res;
1715     struct dwc3     *dwc;
1716 
1717     int         ret;
1718 
1719     void __iomem        *regs;
1720 
1721     dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1722     if (!dwc)
1723         return -ENOMEM;
1724 
1725     dwc->dev = dev;
1726 
1727     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1728     if (!res) {
1729         dev_err(dev, "missing memory resource\n");
1730         return -ENODEV;
1731     }
1732 
1733     dwc->xhci_resources[0].start = res->start;
1734     dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1735                     DWC3_XHCI_REGS_END;
1736     dwc->xhci_resources[0].flags = res->flags;
1737     dwc->xhci_resources[0].name = res->name;
1738 
1739     /*
1740      * Request memory region but exclude xHCI regs,
1741      * since it will be requested by the xhci-plat driver.
1742      */
1743     dwc_res = *res;
1744     dwc_res.start += DWC3_GLOBALS_REGS_START;
1745 
1746     regs = devm_ioremap_resource(dev, &dwc_res);
1747     if (IS_ERR(regs))
1748         return PTR_ERR(regs);
1749 
1750     dwc->regs   = regs;
1751     dwc->regs_size  = resource_size(&dwc_res);
1752 
1753     dwc3_get_properties(dwc);
1754 
1755     dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1756     if (IS_ERR(dwc->reset))
1757         return PTR_ERR(dwc->reset);
1758 
1759     if (dev->of_node) {
1760         /*
1761          * Clocks are optional, but new DT platforms should support all
1762          * clocks as required by the DT-binding.
1763          * Some devices have different clock names in legacy device trees,
1764          * check for them to retain backwards compatibility.
1765          */
1766         dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1767         if (IS_ERR(dwc->bus_clk))
1768             return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1769                          "could not get bus clock\n");
1770 
1771         if (dwc->bus_clk == NULL) {
1772             dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1773             if (IS_ERR(dwc->bus_clk))
1774                 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1775                              "could not get bus clock\n");
1776         }
1777 
1778         dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1779         if (IS_ERR(dwc->ref_clk))
1780             return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1781                          "could not get ref clock\n");
1782 
1783         if (dwc->ref_clk == NULL) {
1784             dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1785             if (IS_ERR(dwc->ref_clk))
1786                 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1787                              "could not get ref clock\n");
1788         }
1789 
1790         dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1791         if (IS_ERR(dwc->susp_clk))
1792             return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1793                          "could not get suspend clock\n");
1794 
1795         if (dwc->susp_clk == NULL) {
1796             dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1797             if (IS_ERR(dwc->susp_clk))
1798                 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1799                              "could not get suspend clock\n");
1800         }
1801     }
1802 
1803     ret = reset_control_deassert(dwc->reset);
1804     if (ret)
1805         return ret;
1806 
1807     ret = dwc3_clk_enable(dwc);
1808     if (ret)
1809         goto assert_reset;
1810 
1811     if (!dwc3_core_is_valid(dwc)) {
1812         dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1813         ret = -ENODEV;
1814         goto disable_clks;
1815     }
1816 
1817     platform_set_drvdata(pdev, dwc);
1818     dwc3_cache_hwparams(dwc);
1819 
1820     if (!dwc->sysdev_is_parent &&
1821         DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1822         ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1823         if (ret)
1824             goto disable_clks;
1825     }
1826 
1827     spin_lock_init(&dwc->lock);
1828     mutex_init(&dwc->mutex);
1829 
1830     pm_runtime_set_active(dev);
1831     pm_runtime_use_autosuspend(dev);
1832     pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1833     pm_runtime_enable(dev);
1834     ret = pm_runtime_get_sync(dev);
1835     if (ret < 0)
1836         goto err1;
1837 
1838     pm_runtime_forbid(dev);
1839 
1840     ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1841     if (ret) {
1842         dev_err(dwc->dev, "failed to allocate event buffers\n");
1843         ret = -ENOMEM;
1844         goto err2;
1845     }
1846 
1847     dwc->edev = dwc3_get_extcon(dwc);
1848     if (IS_ERR(dwc->edev)) {
1849         ret = PTR_ERR(dwc->edev);
1850         dev_err_probe(dwc->dev, ret, "failed to get extcon\n");
1851         goto err3;
1852     }
1853 
1854     ret = dwc3_get_dr_mode(dwc);
1855     if (ret)
1856         goto err3;
1857 
1858     ret = dwc3_alloc_scratch_buffers(dwc);
1859     if (ret)
1860         goto err3;
1861 
1862     ret = dwc3_core_init(dwc);
1863     if (ret) {
1864         dev_err_probe(dev, ret, "failed to initialize core\n");
1865         goto err4;
1866     }
1867 
1868     dwc3_check_params(dwc);
1869     dwc3_debugfs_init(dwc);
1870 
1871     ret = dwc3_core_init_mode(dwc);
1872     if (ret)
1873         goto err5;
1874 
1875     pm_runtime_put(dev);
1876 
1877     return 0;
1878 
1879 err5:
1880     dwc3_debugfs_exit(dwc);
1881     dwc3_event_buffers_cleanup(dwc);
1882 
1883     usb_phy_set_suspend(dwc->usb2_phy, 1);
1884     usb_phy_set_suspend(dwc->usb3_phy, 1);
1885     phy_power_off(dwc->usb2_generic_phy);
1886     phy_power_off(dwc->usb3_generic_phy);
1887 
1888     usb_phy_shutdown(dwc->usb2_phy);
1889     usb_phy_shutdown(dwc->usb3_phy);
1890     phy_exit(dwc->usb2_generic_phy);
1891     phy_exit(dwc->usb3_generic_phy);
1892 
1893     dwc3_ulpi_exit(dwc);
1894 
1895 err4:
1896     dwc3_free_scratch_buffers(dwc);
1897 
1898 err3:
1899     dwc3_free_event_buffers(dwc);
1900 
1901 err2:
1902     pm_runtime_allow(&pdev->dev);
1903 
1904 err1:
1905     pm_runtime_put_sync(&pdev->dev);
1906     pm_runtime_disable(&pdev->dev);
1907 
1908 disable_clks:
1909     dwc3_clk_disable(dwc);
1910 assert_reset:
1911     reset_control_assert(dwc->reset);
1912 
1913     if (dwc->usb_psy)
1914         power_supply_put(dwc->usb_psy);
1915 
1916     return ret;
1917 }
1918 
1919 static int dwc3_remove(struct platform_device *pdev)
1920 {
1921     struct dwc3 *dwc = platform_get_drvdata(pdev);
1922 
1923     pm_runtime_get_sync(&pdev->dev);
1924 
1925     dwc3_core_exit_mode(dwc);
1926     dwc3_debugfs_exit(dwc);
1927 
1928     dwc3_core_exit(dwc);
1929     dwc3_ulpi_exit(dwc);
1930 
1931     pm_runtime_disable(&pdev->dev);
1932     pm_runtime_put_noidle(&pdev->dev);
1933     pm_runtime_set_suspended(&pdev->dev);
1934 
1935     dwc3_free_event_buffers(dwc);
1936     dwc3_free_scratch_buffers(dwc);
1937 
1938     if (dwc->usb_psy)
1939         power_supply_put(dwc->usb_psy);
1940 
1941     return 0;
1942 }
1943 
1944 #ifdef CONFIG_PM
1945 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1946 {
1947     int ret;
1948 
1949     ret = reset_control_deassert(dwc->reset);
1950     if (ret)
1951         return ret;
1952 
1953     ret = dwc3_clk_enable(dwc);
1954     if (ret)
1955         goto assert_reset;
1956 
1957     ret = dwc3_core_init(dwc);
1958     if (ret)
1959         goto disable_clks;
1960 
1961     return 0;
1962 
1963 disable_clks:
1964     dwc3_clk_disable(dwc);
1965 assert_reset:
1966     reset_control_assert(dwc->reset);
1967 
1968     return ret;
1969 }
1970 
1971 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1972 {
1973     unsigned long   flags;
1974     u32 reg;
1975 
1976     switch (dwc->current_dr_role) {
1977     case DWC3_GCTL_PRTCAP_DEVICE:
1978         if (pm_runtime_suspended(dwc->dev))
1979             break;
1980         spin_lock_irqsave(&dwc->lock, flags);
1981         dwc3_gadget_suspend(dwc);
1982         spin_unlock_irqrestore(&dwc->lock, flags);
1983         synchronize_irq(dwc->irq_gadget);
1984         dwc3_core_exit(dwc);
1985         break;
1986     case DWC3_GCTL_PRTCAP_HOST:
1987         if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
1988             dwc3_core_exit(dwc);
1989             break;
1990         }
1991 
1992         /* Let controller to suspend HSPHY before PHY driver suspends */
1993         if (dwc->dis_u2_susphy_quirk ||
1994             dwc->dis_enblslpm_quirk) {
1995             reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1996             reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1997                 DWC3_GUSB2PHYCFG_SUSPHY;
1998             dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1999 
2000             /* Give some time for USB2 PHY to suspend */
2001             usleep_range(5000, 6000);
2002         }
2003 
2004         phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2005         phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
2006         break;
2007     case DWC3_GCTL_PRTCAP_OTG:
2008         /* do nothing during runtime_suspend */
2009         if (PMSG_IS_AUTO(msg))
2010             break;
2011 
2012         if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2013             spin_lock_irqsave(&dwc->lock, flags);
2014             dwc3_gadget_suspend(dwc);
2015             spin_unlock_irqrestore(&dwc->lock, flags);
2016             synchronize_irq(dwc->irq_gadget);
2017         }
2018 
2019         dwc3_otg_exit(dwc);
2020         dwc3_core_exit(dwc);
2021         break;
2022     default:
2023         /* do nothing */
2024         break;
2025     }
2026 
2027     return 0;
2028 }
2029 
2030 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2031 {
2032     unsigned long   flags;
2033     int     ret;
2034     u32     reg;
2035 
2036     switch (dwc->current_dr_role) {
2037     case DWC3_GCTL_PRTCAP_DEVICE:
2038         ret = dwc3_core_init_for_resume(dwc);
2039         if (ret)
2040             return ret;
2041 
2042         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2043         spin_lock_irqsave(&dwc->lock, flags);
2044         dwc3_gadget_resume(dwc);
2045         spin_unlock_irqrestore(&dwc->lock, flags);
2046         break;
2047     case DWC3_GCTL_PRTCAP_HOST:
2048         if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2049             ret = dwc3_core_init_for_resume(dwc);
2050             if (ret)
2051                 return ret;
2052             dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2053             break;
2054         }
2055         /* Restore GUSB2PHYCFG bits that were modified in suspend */
2056         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2057         if (dwc->dis_u2_susphy_quirk)
2058             reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2059 
2060         if (dwc->dis_enblslpm_quirk)
2061             reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2062 
2063         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2064 
2065         phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2066         phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2067         break;
2068     case DWC3_GCTL_PRTCAP_OTG:
2069         /* nothing to do on runtime_resume */
2070         if (PMSG_IS_AUTO(msg))
2071             break;
2072 
2073         ret = dwc3_core_init_for_resume(dwc);
2074         if (ret)
2075             return ret;
2076 
2077         dwc3_set_prtcap(dwc, dwc->current_dr_role);
2078 
2079         dwc3_otg_init(dwc);
2080         if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2081             dwc3_otg_host_init(dwc);
2082         } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2083             spin_lock_irqsave(&dwc->lock, flags);
2084             dwc3_gadget_resume(dwc);
2085             spin_unlock_irqrestore(&dwc->lock, flags);
2086         }
2087 
2088         break;
2089     default:
2090         /* do nothing */
2091         break;
2092     }
2093 
2094     return 0;
2095 }
2096 
2097 static int dwc3_runtime_checks(struct dwc3 *dwc)
2098 {
2099     switch (dwc->current_dr_role) {
2100     case DWC3_GCTL_PRTCAP_DEVICE:
2101         if (dwc->connected)
2102             return -EBUSY;
2103         break;
2104     case DWC3_GCTL_PRTCAP_HOST:
2105     default:
2106         /* do nothing */
2107         break;
2108     }
2109 
2110     return 0;
2111 }
2112 
2113 static int dwc3_runtime_suspend(struct device *dev)
2114 {
2115     struct dwc3     *dwc = dev_get_drvdata(dev);
2116     int     ret;
2117 
2118     if (dwc3_runtime_checks(dwc))
2119         return -EBUSY;
2120 
2121     ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2122     if (ret)
2123         return ret;
2124 
2125     return 0;
2126 }
2127 
2128 static int dwc3_runtime_resume(struct device *dev)
2129 {
2130     struct dwc3     *dwc = dev_get_drvdata(dev);
2131     int     ret;
2132 
2133     ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2134     if (ret)
2135         return ret;
2136 
2137     switch (dwc->current_dr_role) {
2138     case DWC3_GCTL_PRTCAP_DEVICE:
2139         dwc3_gadget_process_pending_events(dwc);
2140         break;
2141     case DWC3_GCTL_PRTCAP_HOST:
2142     default:
2143         /* do nothing */
2144         break;
2145     }
2146 
2147     pm_runtime_mark_last_busy(dev);
2148 
2149     return 0;
2150 }
2151 
2152 static int dwc3_runtime_idle(struct device *dev)
2153 {
2154     struct dwc3     *dwc = dev_get_drvdata(dev);
2155 
2156     switch (dwc->current_dr_role) {
2157     case DWC3_GCTL_PRTCAP_DEVICE:
2158         if (dwc3_runtime_checks(dwc))
2159             return -EBUSY;
2160         break;
2161     case DWC3_GCTL_PRTCAP_HOST:
2162     default:
2163         /* do nothing */
2164         break;
2165     }
2166 
2167     pm_runtime_mark_last_busy(dev);
2168     pm_runtime_autosuspend(dev);
2169 
2170     return 0;
2171 }
2172 #endif /* CONFIG_PM */
2173 
2174 #ifdef CONFIG_PM_SLEEP
2175 static int dwc3_suspend(struct device *dev)
2176 {
2177     struct dwc3 *dwc = dev_get_drvdata(dev);
2178     int     ret;
2179 
2180     ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2181     if (ret)
2182         return ret;
2183 
2184     pinctrl_pm_select_sleep_state(dev);
2185 
2186     return 0;
2187 }
2188 
2189 static int dwc3_resume(struct device *dev)
2190 {
2191     struct dwc3 *dwc = dev_get_drvdata(dev);
2192     int     ret;
2193 
2194     pinctrl_pm_select_default_state(dev);
2195 
2196     ret = dwc3_resume_common(dwc, PMSG_RESUME);
2197     if (ret)
2198         return ret;
2199 
2200     pm_runtime_disable(dev);
2201     pm_runtime_set_active(dev);
2202     pm_runtime_enable(dev);
2203 
2204     return 0;
2205 }
2206 
2207 static void dwc3_complete(struct device *dev)
2208 {
2209     struct dwc3 *dwc = dev_get_drvdata(dev);
2210     u32     reg;
2211 
2212     if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2213             dwc->dis_split_quirk) {
2214         reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2215         reg |= DWC3_GUCTL3_SPLITDISABLE;
2216         dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2217     }
2218 }
2219 #else
2220 #define dwc3_complete NULL
2221 #endif /* CONFIG_PM_SLEEP */
2222 
2223 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2224     SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2225     .complete = dwc3_complete,
2226     SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2227             dwc3_runtime_idle)
2228 };
2229 
2230 #ifdef CONFIG_OF
2231 static const struct of_device_id of_dwc3_match[] = {
2232     {
2233         .compatible = "snps,dwc3"
2234     },
2235     {
2236         .compatible = "synopsys,dwc3"
2237     },
2238     { },
2239 };
2240 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2241 #endif
2242 
2243 #ifdef CONFIG_ACPI
2244 
2245 #define ACPI_ID_INTEL_BSW   "808622B7"
2246 
2247 static const struct acpi_device_id dwc3_acpi_match[] = {
2248     { ACPI_ID_INTEL_BSW, 0 },
2249     { },
2250 };
2251 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2252 #endif
2253 
2254 static struct platform_driver dwc3_driver = {
2255     .probe      = dwc3_probe,
2256     .remove     = dwc3_remove,
2257     .driver     = {
2258         .name   = "dwc3",
2259         .of_match_table = of_match_ptr(of_dwc3_match),
2260         .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2261         .pm = &dwc3_dev_pm_ops,
2262     },
2263 };
2264 
2265 module_platform_driver(dwc3_driver);
2266 
2267 MODULE_ALIAS("platform:dwc3");
2268 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2269 MODULE_LICENSE("GPL v2");
2270 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!