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0001 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
0002 /*
0003  * platform.c - DesignWare HS OTG Controller platform driver
0004  *
0005  * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
0006  *
0007  * Redistribution and use in source and binary forms, with or without
0008  * modification, are permitted provided that the following conditions
0009  * are met:
0010  * 1. Redistributions of source code must retain the above copyright
0011  *    notice, this list of conditions, and the following disclaimer,
0012  *    without modification.
0013  * 2. Redistributions in binary form must reproduce the above copyright
0014  *    notice, this list of conditions and the following disclaimer in the
0015  *    documentation and/or other materials provided with the distribution.
0016  * 3. The names of the above-listed copyright holders may not be used
0017  *    to endorse or promote products derived from this software without
0018  *    specific prior written permission.
0019  *
0020  * ALTERNATIVELY, this software may be distributed under the terms of the
0021  * GNU General Public License ("GPL") as published by the Free Software
0022  * Foundation; either version 2 of the License, or (at your option) any
0023  * later version.
0024  *
0025  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
0026  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
0027  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
0028  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
0029  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0030  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
0031  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
0032  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
0033  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
0034  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0035  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0036  */
0037 
0038 #include <linux/kernel.h>
0039 #include <linux/module.h>
0040 #include <linux/slab.h>
0041 #include <linux/clk.h>
0042 #include <linux/device.h>
0043 #include <linux/dma-mapping.h>
0044 #include <linux/of_device.h>
0045 #include <linux/mutex.h>
0046 #include <linux/platform_device.h>
0047 #include <linux/phy/phy.h>
0048 #include <linux/platform_data/s3c-hsotg.h>
0049 #include <linux/reset.h>
0050 
0051 #include <linux/usb/of.h>
0052 
0053 #include "core.h"
0054 #include "hcd.h"
0055 #include "debug.h"
0056 
0057 static const char dwc2_driver_name[] = "dwc2";
0058 
0059 /*
0060  * Check the dr_mode against the module configuration and hardware
0061  * capabilities.
0062  *
0063  * The hardware, module, and dr_mode, can each be set to host, device,
0064  * or otg. Check that all these values are compatible and adjust the
0065  * value of dr_mode if possible.
0066  *
0067  *                      actual
0068  *    HW  MOD dr_mode   dr_mode
0069  *  ------------------------------
0070  *   HST  HST  any    :  HST
0071  *   HST  DEV  any    :  ---
0072  *   HST  OTG  any    :  HST
0073  *
0074  *   DEV  HST  any    :  ---
0075  *   DEV  DEV  any    :  DEV
0076  *   DEV  OTG  any    :  DEV
0077  *
0078  *   OTG  HST  any    :  HST
0079  *   OTG  DEV  any    :  DEV
0080  *   OTG  OTG  any    :  dr_mode
0081  */
0082 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
0083 {
0084     enum usb_dr_mode mode;
0085 
0086     hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
0087     if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
0088         hsotg->dr_mode = USB_DR_MODE_OTG;
0089 
0090     mode = hsotg->dr_mode;
0091 
0092     if (dwc2_hw_is_device(hsotg)) {
0093         if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
0094             dev_err(hsotg->dev,
0095                 "Controller does not support host mode.\n");
0096             return -EINVAL;
0097         }
0098         mode = USB_DR_MODE_PERIPHERAL;
0099     } else if (dwc2_hw_is_host(hsotg)) {
0100         if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
0101             dev_err(hsotg->dev,
0102                 "Controller does not support device mode.\n");
0103             return -EINVAL;
0104         }
0105         mode = USB_DR_MODE_HOST;
0106     } else {
0107         if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
0108             mode = USB_DR_MODE_HOST;
0109         else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
0110             mode = USB_DR_MODE_PERIPHERAL;
0111     }
0112 
0113     if (mode != hsotg->dr_mode) {
0114         dev_warn(hsotg->dev,
0115              "Configuration mismatch. dr_mode forced to %s\n",
0116             mode == USB_DR_MODE_HOST ? "host" : "device");
0117 
0118         hsotg->dr_mode = mode;
0119     }
0120 
0121     return 0;
0122 }
0123 
0124 static void __dwc2_disable_regulators(void *data)
0125 {
0126     struct dwc2_hsotg *hsotg = data;
0127 
0128     regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
0129 }
0130 
0131 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
0132 {
0133     struct platform_device *pdev = to_platform_device(hsotg->dev);
0134     int ret;
0135 
0136     ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
0137                     hsotg->supplies);
0138     if (ret)
0139         return ret;
0140 
0141     ret = devm_add_action_or_reset(&pdev->dev,
0142                        __dwc2_disable_regulators, hsotg);
0143     if (ret)
0144         return ret;
0145 
0146     if (hsotg->clk) {
0147         ret = clk_prepare_enable(hsotg->clk);
0148         if (ret)
0149             return ret;
0150     }
0151 
0152     if (hsotg->uphy) {
0153         ret = usb_phy_init(hsotg->uphy);
0154     } else if (hsotg->plat && hsotg->plat->phy_init) {
0155         ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
0156     } else {
0157         ret = phy_init(hsotg->phy);
0158         if (ret == 0)
0159             ret = phy_power_on(hsotg->phy);
0160     }
0161 
0162     return ret;
0163 }
0164 
0165 /**
0166  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
0167  * @hsotg: The driver state
0168  *
0169  * A wrapper for platform code responsible for controlling
0170  * low-level USB platform resources (phy, clock, regulators)
0171  */
0172 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
0173 {
0174     int ret = __dwc2_lowlevel_hw_enable(hsotg);
0175 
0176     if (ret == 0)
0177         hsotg->ll_hw_enabled = true;
0178     return ret;
0179 }
0180 
0181 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
0182 {
0183     struct platform_device *pdev = to_platform_device(hsotg->dev);
0184     int ret = 0;
0185 
0186     if (hsotg->uphy) {
0187         usb_phy_shutdown(hsotg->uphy);
0188     } else if (hsotg->plat && hsotg->plat->phy_exit) {
0189         ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
0190     } else {
0191         ret = phy_power_off(hsotg->phy);
0192         if (ret == 0)
0193             ret = phy_exit(hsotg->phy);
0194     }
0195     if (ret)
0196         return ret;
0197 
0198     if (hsotg->clk)
0199         clk_disable_unprepare(hsotg->clk);
0200 
0201     return 0;
0202 }
0203 
0204 /**
0205  * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
0206  * @hsotg: The driver state
0207  *
0208  * A wrapper for platform code responsible for controlling
0209  * low-level USB platform resources (phy, clock, regulators)
0210  */
0211 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
0212 {
0213     int ret = __dwc2_lowlevel_hw_disable(hsotg);
0214 
0215     if (ret == 0)
0216         hsotg->ll_hw_enabled = false;
0217     return ret;
0218 }
0219 
0220 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
0221 {
0222     int i, ret;
0223 
0224     hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
0225     if (IS_ERR(hsotg->reset))
0226         return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset),
0227                      "error getting reset control\n");
0228 
0229     reset_control_deassert(hsotg->reset);
0230 
0231     hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
0232     if (IS_ERR(hsotg->reset_ecc))
0233         return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset_ecc),
0234                      "error getting reset control for ecc\n");
0235 
0236     reset_control_deassert(hsotg->reset_ecc);
0237 
0238     /*
0239      * Attempt to find a generic PHY, then look for an old style
0240      * USB PHY and then fall back to pdata
0241      */
0242     hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
0243     if (IS_ERR(hsotg->phy)) {
0244         ret = PTR_ERR(hsotg->phy);
0245         switch (ret) {
0246         case -ENODEV:
0247         case -ENOSYS:
0248             hsotg->phy = NULL;
0249             break;
0250         default:
0251             return dev_err_probe(hsotg->dev, ret, "error getting phy\n");
0252         }
0253     }
0254 
0255     if (!hsotg->phy) {
0256         hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
0257         if (IS_ERR(hsotg->uphy)) {
0258             ret = PTR_ERR(hsotg->uphy);
0259             switch (ret) {
0260             case -ENODEV:
0261             case -ENXIO:
0262                 hsotg->uphy = NULL;
0263                 break;
0264             default:
0265                 return dev_err_probe(hsotg->dev, ret, "error getting usb phy\n");
0266             }
0267         }
0268     }
0269 
0270     hsotg->plat = dev_get_platdata(hsotg->dev);
0271 
0272     /* Clock */
0273     hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
0274     if (IS_ERR(hsotg->clk))
0275         return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->clk), "cannot get otg clock\n");
0276 
0277     /* Regulators */
0278     for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
0279         hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
0280 
0281     ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
0282                       hsotg->supplies);
0283     if (ret)
0284         return dev_err_probe(hsotg->dev, ret, "failed to request supplies\n");
0285 
0286     return 0;
0287 }
0288 
0289 /**
0290  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
0291  * DWC_otg driver
0292  *
0293  * @dev: Platform device
0294  *
0295  * This routine is called, for example, when the rmmod command is executed. The
0296  * device may or may not be electrically present. If it is present, the driver
0297  * stops device processing. Any resources used on behalf of this device are
0298  * freed.
0299  */
0300 static int dwc2_driver_remove(struct platform_device *dev)
0301 {
0302     struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
0303     struct dwc2_gregs_backup *gr;
0304     int ret = 0;
0305 
0306     gr = &hsotg->gr_backup;
0307 
0308     /* Exit Hibernation when driver is removed. */
0309     if (hsotg->hibernated) {
0310         if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
0311             ret = dwc2_exit_hibernation(hsotg, 0, 0, 1);
0312         else
0313             ret = dwc2_exit_hibernation(hsotg, 0, 0, 0);
0314 
0315         if (ret)
0316             dev_err(hsotg->dev,
0317                 "exit hibernation failed.\n");
0318     }
0319 
0320     /* Exit Partial Power Down when driver is removed. */
0321     if (hsotg->in_ppd) {
0322         ret = dwc2_exit_partial_power_down(hsotg, 0, true);
0323         if (ret)
0324             dev_err(hsotg->dev,
0325                 "exit partial_power_down failed\n");
0326     }
0327 
0328     /* Exit clock gating when driver is removed. */
0329     if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE &&
0330         hsotg->bus_suspended) {
0331         if (dwc2_is_device_mode(hsotg))
0332             dwc2_gadget_exit_clock_gating(hsotg, 0);
0333         else
0334             dwc2_host_exit_clock_gating(hsotg, 0);
0335     }
0336 
0337     dwc2_debugfs_exit(hsotg);
0338     if (hsotg->hcd_enabled)
0339         dwc2_hcd_remove(hsotg);
0340     if (hsotg->gadget_enabled)
0341         dwc2_hsotg_remove(hsotg);
0342 
0343     dwc2_drd_exit(hsotg);
0344 
0345     if (hsotg->params.activate_stm_id_vb_detection)
0346         regulator_disable(hsotg->usb33d);
0347 
0348     if (hsotg->ll_hw_enabled)
0349         dwc2_lowlevel_hw_disable(hsotg);
0350 
0351     reset_control_assert(hsotg->reset);
0352     reset_control_assert(hsotg->reset_ecc);
0353 
0354     return ret;
0355 }
0356 
0357 /**
0358  * dwc2_driver_shutdown() - Called on device shutdown
0359  *
0360  * @dev: Platform device
0361  *
0362  * In specific conditions (involving usb hubs) dwc2 devices can create a
0363  * lot of interrupts, even to the point of overwhelming devices running
0364  * at low frequencies. Some devices need to do special clock handling
0365  * at shutdown-time which may bring the system clock below the threshold
0366  * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
0367  * prevents reboots/poweroffs from getting stuck in such cases.
0368  */
0369 static void dwc2_driver_shutdown(struct platform_device *dev)
0370 {
0371     struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
0372 
0373     dwc2_disable_global_interrupts(hsotg);
0374     synchronize_irq(hsotg->irq);
0375 }
0376 
0377 /**
0378  * dwc2_check_core_endianness() - Returns true if core and AHB have
0379  * opposite endianness.
0380  * @hsotg:  Programming view of the DWC_otg controller.
0381  */
0382 static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
0383 {
0384     u32 snpsid;
0385 
0386     snpsid = ioread32(hsotg->regs + GSNPSID);
0387     if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
0388         (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
0389         (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
0390         return false;
0391     return true;
0392 }
0393 
0394 /**
0395  * dwc2_check_core_version() - Check core version
0396  *
0397  * @hsotg: Programming view of the DWC_otg controller
0398  *
0399  */
0400 int dwc2_check_core_version(struct dwc2_hsotg *hsotg)
0401 {
0402     struct dwc2_hw_params *hw = &hsotg->hw_params;
0403 
0404     /*
0405      * Attempt to ensure this device is really a DWC_otg Controller.
0406      * Read and verify the GSNPSID register contents. The value should be
0407      * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
0408      */
0409 
0410     hw->snpsid = dwc2_readl(hsotg, GSNPSID);
0411     if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
0412         (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
0413         (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
0414         dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
0415             hw->snpsid);
0416         return -ENODEV;
0417     }
0418 
0419     dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
0420         hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
0421         hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
0422     return 0;
0423 }
0424 
0425 /**
0426  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
0427  * driver
0428  *
0429  * @dev: Platform device
0430  *
0431  * This routine creates the driver components required to control the device
0432  * (core, HCD, and PCD) and initializes the device. The driver components are
0433  * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
0434  * in the device private data. This allows the driver to access the dwc2_hsotg
0435  * structure on subsequent calls to driver methods for this device.
0436  */
0437 static int dwc2_driver_probe(struct platform_device *dev)
0438 {
0439     struct dwc2_hsotg *hsotg;
0440     struct resource *res;
0441     int retval;
0442 
0443     hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
0444     if (!hsotg)
0445         return -ENOMEM;
0446 
0447     hsotg->dev = &dev->dev;
0448 
0449     /*
0450      * Use reasonable defaults so platforms don't have to provide these.
0451      */
0452     if (!dev->dev.dma_mask)
0453         dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
0454     retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
0455     if (retval) {
0456         dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
0457         return retval;
0458     }
0459 
0460     hsotg->regs = devm_platform_get_and_ioremap_resource(dev, 0, &res);
0461     if (IS_ERR(hsotg->regs))
0462         return PTR_ERR(hsotg->regs);
0463 
0464     dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
0465         (unsigned long)res->start, hsotg->regs);
0466 
0467     retval = dwc2_lowlevel_hw_init(hsotg);
0468     if (retval)
0469         return retval;
0470 
0471     spin_lock_init(&hsotg->lock);
0472 
0473     hsotg->irq = platform_get_irq(dev, 0);
0474     if (hsotg->irq < 0)
0475         return hsotg->irq;
0476 
0477     dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
0478         hsotg->irq);
0479     retval = devm_request_irq(hsotg->dev, hsotg->irq,
0480                   dwc2_handle_common_intr, IRQF_SHARED,
0481                   dev_name(hsotg->dev), hsotg);
0482     if (retval)
0483         return retval;
0484 
0485     hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
0486     if (IS_ERR(hsotg->vbus_supply)) {
0487         retval = PTR_ERR(hsotg->vbus_supply);
0488         hsotg->vbus_supply = NULL;
0489         if (retval != -ENODEV)
0490             return retval;
0491     }
0492 
0493     retval = dwc2_lowlevel_hw_enable(hsotg);
0494     if (retval)
0495         return retval;
0496 
0497     hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
0498 
0499     retval = dwc2_get_dr_mode(hsotg);
0500     if (retval)
0501         goto error;
0502 
0503     hsotg->need_phy_for_wake =
0504         of_property_read_bool(dev->dev.of_node,
0505                       "snps,need-phy-for-wake");
0506 
0507     /*
0508      * Before performing any core related operations
0509      * check core version.
0510      */
0511     retval = dwc2_check_core_version(hsotg);
0512     if (retval)
0513         goto error;
0514 
0515     /*
0516      * Reset before dwc2_get_hwparams() then it could get power-on real
0517      * reset value form registers.
0518      */
0519     retval = dwc2_core_reset(hsotg, false);
0520     if (retval)
0521         goto error;
0522 
0523     /* Detect config values from hardware */
0524     retval = dwc2_get_hwparams(hsotg);
0525     if (retval)
0526         goto error;
0527 
0528     /*
0529      * For OTG cores, set the force mode bits to reflect the value
0530      * of dr_mode. Force mode bits should not be touched at any
0531      * other time after this.
0532      */
0533     dwc2_force_dr_mode(hsotg);
0534 
0535     retval = dwc2_init_params(hsotg);
0536     if (retval)
0537         goto error;
0538 
0539     if (hsotg->params.activate_stm_id_vb_detection) {
0540         u32 ggpio;
0541 
0542         hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d");
0543         if (IS_ERR(hsotg->usb33d)) {
0544             retval = PTR_ERR(hsotg->usb33d);
0545             dev_err_probe(hsotg->dev, retval, "failed to request usb33d supply\n");
0546             goto error;
0547         }
0548         retval = regulator_enable(hsotg->usb33d);
0549         if (retval) {
0550             dev_err_probe(hsotg->dev, retval, "failed to enable usb33d supply\n");
0551             goto error;
0552         }
0553 
0554         ggpio = dwc2_readl(hsotg, GGPIO);
0555         ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
0556         ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
0557         dwc2_writel(hsotg, ggpio, GGPIO);
0558 
0559         /* ID/VBUS detection startup time */
0560         usleep_range(5000, 7000);
0561     }
0562 
0563     retval = dwc2_drd_init(hsotg);
0564     if (retval) {
0565         dev_err_probe(hsotg->dev, retval, "failed to initialize dual-role\n");
0566         goto error_init;
0567     }
0568 
0569     if (hsotg->dr_mode != USB_DR_MODE_HOST) {
0570         retval = dwc2_gadget_init(hsotg);
0571         if (retval)
0572             goto error_drd;
0573         hsotg->gadget_enabled = 1;
0574     }
0575 
0576     /*
0577      * If we need PHY for wakeup we must be wakeup capable.
0578      * When we have a device that can wake without the PHY we
0579      * can adjust this condition.
0580      */
0581     if (hsotg->need_phy_for_wake)
0582         device_set_wakeup_capable(&dev->dev, true);
0583 
0584     hsotg->reset_phy_on_wake =
0585         of_property_read_bool(dev->dev.of_node,
0586                       "snps,reset-phy-on-wake");
0587     if (hsotg->reset_phy_on_wake && !hsotg->phy) {
0588         dev_warn(hsotg->dev,
0589              "Quirk reset-phy-on-wake only supports generic PHYs\n");
0590         hsotg->reset_phy_on_wake = false;
0591     }
0592 
0593     if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
0594         retval = dwc2_hcd_init(hsotg);
0595         if (retval) {
0596             if (hsotg->gadget_enabled)
0597                 dwc2_hsotg_remove(hsotg);
0598             goto error_drd;
0599         }
0600         hsotg->hcd_enabled = 1;
0601     }
0602 
0603     platform_set_drvdata(dev, hsotg);
0604     hsotg->hibernated = 0;
0605 
0606     dwc2_debugfs_init(hsotg);
0607 
0608     /* Gadget code manages lowlevel hw on its own */
0609     if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
0610         dwc2_lowlevel_hw_disable(hsotg);
0611 
0612 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
0613     IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
0614     /* Postponed adding a new gadget to the udc class driver list */
0615     if (hsotg->gadget_enabled) {
0616         retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget);
0617         if (retval) {
0618             hsotg->gadget.udc = NULL;
0619             dwc2_hsotg_remove(hsotg);
0620             goto error_debugfs;
0621         }
0622     }
0623 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
0624     return 0;
0625 
0626 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
0627     IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
0628 error_debugfs:
0629     dwc2_debugfs_exit(hsotg);
0630     if (hsotg->hcd_enabled)
0631         dwc2_hcd_remove(hsotg);
0632 #endif
0633 error_drd:
0634     dwc2_drd_exit(hsotg);
0635 
0636 error_init:
0637     if (hsotg->params.activate_stm_id_vb_detection)
0638         regulator_disable(hsotg->usb33d);
0639 error:
0640     if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL)
0641         dwc2_lowlevel_hw_disable(hsotg);
0642     return retval;
0643 }
0644 
0645 static int __maybe_unused dwc2_suspend(struct device *dev)
0646 {
0647     struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
0648     bool is_device_mode = dwc2_is_device_mode(dwc2);
0649     int ret = 0;
0650 
0651     if (is_device_mode)
0652         dwc2_hsotg_suspend(dwc2);
0653 
0654     dwc2_drd_suspend(dwc2);
0655 
0656     if (dwc2->params.activate_stm_id_vb_detection) {
0657         unsigned long flags;
0658         u32 ggpio, gotgctl;
0659 
0660         /*
0661          * Need to force the mode to the current mode to avoid Mode
0662          * Mismatch Interrupt when ID detection will be disabled.
0663          */
0664         dwc2_force_mode(dwc2, !is_device_mode);
0665 
0666         spin_lock_irqsave(&dwc2->lock, flags);
0667         gotgctl = dwc2_readl(dwc2, GOTGCTL);
0668         /* bypass debounce filter, enable overrides */
0669         gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS;
0670         gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN;
0671         /* Force A / B session if needed */
0672         if (gotgctl & GOTGCTL_ASESVLD)
0673             gotgctl |= GOTGCTL_AVALOVAL;
0674         if (gotgctl & GOTGCTL_BSESVLD)
0675             gotgctl |= GOTGCTL_BVALOVAL;
0676         dwc2_writel(dwc2, gotgctl, GOTGCTL);
0677         spin_unlock_irqrestore(&dwc2->lock, flags);
0678 
0679         ggpio = dwc2_readl(dwc2, GGPIO);
0680         ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN;
0681         ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN;
0682         dwc2_writel(dwc2, ggpio, GGPIO);
0683 
0684         regulator_disable(dwc2->usb33d);
0685     }
0686 
0687     if (dwc2->ll_hw_enabled &&
0688         (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
0689         ret = __dwc2_lowlevel_hw_disable(dwc2);
0690         dwc2->phy_off_for_suspend = true;
0691     }
0692 
0693     return ret;
0694 }
0695 
0696 static int __maybe_unused dwc2_resume(struct device *dev)
0697 {
0698     struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
0699     int ret = 0;
0700 
0701     if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
0702         ret = __dwc2_lowlevel_hw_enable(dwc2);
0703         if (ret)
0704             return ret;
0705     }
0706     dwc2->phy_off_for_suspend = false;
0707 
0708     if (dwc2->params.activate_stm_id_vb_detection) {
0709         unsigned long flags;
0710         u32 ggpio, gotgctl;
0711 
0712         ret = regulator_enable(dwc2->usb33d);
0713         if (ret)
0714             return ret;
0715 
0716         ggpio = dwc2_readl(dwc2, GGPIO);
0717         ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
0718         ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
0719         dwc2_writel(dwc2, ggpio, GGPIO);
0720 
0721         /* ID/VBUS detection startup time */
0722         usleep_range(5000, 7000);
0723 
0724         spin_lock_irqsave(&dwc2->lock, flags);
0725         gotgctl = dwc2_readl(dwc2, GOTGCTL);
0726         gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS;
0727         gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN |
0728                  GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL);
0729         dwc2_writel(dwc2, gotgctl, GOTGCTL);
0730         spin_unlock_irqrestore(&dwc2->lock, flags);
0731     }
0732 
0733     if (!dwc2->role_sw) {
0734         /* Need to restore FORCEDEVMODE/FORCEHOSTMODE */
0735         dwc2_force_dr_mode(dwc2);
0736     } else {
0737         dwc2_drd_resume(dwc2);
0738     }
0739 
0740     if (dwc2_is_device_mode(dwc2))
0741         ret = dwc2_hsotg_resume(dwc2);
0742 
0743     return ret;
0744 }
0745 
0746 static const struct dev_pm_ops dwc2_dev_pm_ops = {
0747     SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
0748 };
0749 
0750 static struct platform_driver dwc2_platform_driver = {
0751     .driver = {
0752         .name = dwc2_driver_name,
0753         .of_match_table = dwc2_of_match_table,
0754         .acpi_match_table = ACPI_PTR(dwc2_acpi_match),
0755         .pm = &dwc2_dev_pm_ops,
0756     },
0757     .probe = dwc2_driver_probe,
0758     .remove = dwc2_driver_remove,
0759     .shutdown = dwc2_driver_shutdown,
0760 };
0761 
0762 module_platform_driver(dwc2_platform_driver);
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