usb/dwc2/params.c

0001 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
0002 /*
0003  * Copyright (C) 2004-2016 Synopsys, Inc.
0004  *
0005  * Redistribution and use in source and binary forms, with or without
0006  * modification, are permitted provided that the following conditions
0007  * are met:
0008  * 1. Redistributions of source code must retain the above copyright
0009  *    notice, this list of conditions, and the following disclaimer,
0010  *    without modification.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  * 3. The names of the above-listed copyright holders may not be used
0015  *    to endorse or promote products derived from this software without
0016  *    specific prior written permission.
0017  *
0018  * ALTERNATIVELY, this software may be distributed under the terms of the
0019  * GNU General Public License ("GPL") as published by the Free Software
0020  * Foundation; either version 2 of the License, or (at your option) any
0021  * later version.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
0024  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
0025  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
0026  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
0027  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0028  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
0029  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
0030  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
0031  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
0032  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0033  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <linux/kernel.h>
0037 #include <linux/module.h>
0038 #include <linux/of_device.h>
0039 #include <linux/usb/of.h>
0040
0041 #include "core.h"
0042
0043 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
0044 {
0045     struct dwc2_core_params *p = &hsotg->params;
0046
0047     p->host_rx_fifo_size = 774;
0048     p->max_transfer_size = 65535;
0049     p->max_packet_count = 511;
0050     p->ahbcfg = 0x10;
0051 }
0052
0053 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
0054 {
0055     struct dwc2_core_params *p = &hsotg->params;
0056
0057     p->otg_caps.hnp_support = false;
0058     p->otg_caps.srp_support = false;
0059     p->speed = DWC2_SPEED_PARAM_HIGH;
0060     p->host_rx_fifo_size = 512;
0061     p->host_nperio_tx_fifo_size = 512;
0062     p->host_perio_tx_fifo_size = 512;
0063     p->max_transfer_size = 65535;
0064     p->max_packet_count = 511;
0065     p->host_channels = 16;
0066     p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
0067     p->phy_utmi_width = 8;
0068     p->i2c_enable = false;
0069     p->reload_ctl = false;
0070     p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
0071         GAHBCFG_HBSTLEN_SHIFT;
0072     p->change_speed_quirk = true;
0073     p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
0074 }
0075
0076 static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg)
0077 {
0078     struct dwc2_core_params *p = &hsotg->params;
0079
0080     p->otg_caps.hnp_support = false;
0081     p->speed = DWC2_SPEED_PARAM_HIGH;
0082     p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
0083     p->phy_utmi_width = 16;
0084     p->activate_ingenic_overcurrent_detection =
0085         !device_property_read_bool(hsotg->dev, "disable-over-current");
0086 }
0087
0088 static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg)
0089 {
0090     struct dwc2_core_params *p = &hsotg->params;
0091
0092     p->otg_caps.hnp_support = false;
0093     p->speed = DWC2_SPEED_PARAM_HIGH;
0094     p->host_channels = 16;
0095     p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
0096     p->phy_utmi_width = 16;
0097     p->activate_ingenic_overcurrent_detection =
0098         !device_property_read_bool(hsotg->dev, "disable-over-current");
0099 }
0100
0101 static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg)
0102 {
0103     struct dwc2_core_params *p = &hsotg->params;
0104
0105     p->otg_caps.hnp_support = false;
0106     p->speed = DWC2_SPEED_PARAM_HIGH;
0107     p->host_rx_fifo_size = 1024;
0108     p->host_nperio_tx_fifo_size = 1024;
0109     p->host_perio_tx_fifo_size = 1024;
0110     p->host_channels = 16;
0111     p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
0112     p->phy_utmi_width = 16;
0113     p->activate_ingenic_overcurrent_detection =
0114         !device_property_read_bool(hsotg->dev, "disable-over-current");
0115 }
0116
0117 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
0118 {
0119     struct dwc2_core_params *p = &hsotg->params;
0120
0121     p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
0122     p->no_clock_gating = true;
0123     p->phy_utmi_width = 8;
0124 }
0125
0126 static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg)
0127 {
0128     struct dwc2_core_params *p = &hsotg->params;
0129
0130     p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
0131     p->no_clock_gating = true;
0132 }
0133
0134 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
0135 {
0136     struct dwc2_core_params *p = &hsotg->params;
0137
0138     p->otg_caps.hnp_support = false;
0139     p->otg_caps.srp_support = false;
0140     p->host_rx_fifo_size = 525;
0141     p->host_nperio_tx_fifo_size = 128;
0142     p->host_perio_tx_fifo_size = 256;
0143     p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
0144         GAHBCFG_HBSTLEN_SHIFT;
0145     p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
0146 }
0147
0148 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
0149 {
0150     struct dwc2_core_params *p = &hsotg->params;
0151
0152     p->otg_caps.hnp_support = false;
0153     p->otg_caps.srp_support = false;
0154     p->host_rx_fifo_size = 288;
0155     p->host_nperio_tx_fifo_size = 128;
0156     p->host_perio_tx_fifo_size = 96;
0157     p->max_transfer_size = 65535;
0158     p->max_packet_count = 511;
0159     p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
0160         GAHBCFG_HBSTLEN_SHIFT;
0161 }
0162
0163 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
0164 {
0165     struct dwc2_core_params *p = &hsotg->params;
0166
0167     p->otg_caps.hnp_support = false;
0168     p->otg_caps.srp_support = false;
0169     p->speed = DWC2_SPEED_PARAM_HIGH;
0170     p->host_rx_fifo_size = 512;
0171     p->host_nperio_tx_fifo_size = 500;
0172     p->host_perio_tx_fifo_size = 500;
0173     p->host_channels = 16;
0174     p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
0175     p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
0176         GAHBCFG_HBSTLEN_SHIFT;
0177     p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
0178 }
0179
0180 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
0181 {
0182     struct dwc2_core_params *p = &hsotg->params;
0183
0184     p->lpm = false;
0185     p->lpm_clock_gating = false;
0186     p->besl = false;
0187     p->hird_threshold_en = false;
0188 }
0189
0190 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
0191 {
0192     struct dwc2_core_params *p = &hsotg->params;
0193
0194     p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
0195 }
0196
0197 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
0198 {
0199     struct dwc2_core_params *p = &hsotg->params;
0200
0201     p->otg_caps.hnp_support = false;
0202     p->otg_caps.srp_support = false;
0203     p->speed = DWC2_SPEED_PARAM_FULL;
0204     p->host_rx_fifo_size = 128;
0205     p->host_nperio_tx_fifo_size = 96;
0206     p->host_perio_tx_fifo_size = 96;
0207     p->max_packet_count = 256;
0208     p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
0209     p->i2c_enable = false;
0210     p->activate_stm_fs_transceiver = true;
0211 }
0212
0213 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
0214 {
0215     struct dwc2_core_params *p = &hsotg->params;
0216
0217     p->host_rx_fifo_size = 622;
0218     p->host_nperio_tx_fifo_size = 128;
0219     p->host_perio_tx_fifo_size = 256;
0220 }
0221
0222 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
0223 {
0224     struct dwc2_core_params *p = &hsotg->params;
0225
0226     p->otg_caps.hnp_support = false;
0227     p->otg_caps.srp_support = false;
0228     p->otg_caps.otg_rev = 0x200;
0229     p->speed = DWC2_SPEED_PARAM_FULL;
0230     p->host_rx_fifo_size = 128;
0231     p->host_nperio_tx_fifo_size = 96;
0232     p->host_perio_tx_fifo_size = 96;
0233     p->max_packet_count = 256;
0234     p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
0235     p->i2c_enable = false;
0236     p->activate_stm_fs_transceiver = true;
0237     p->activate_stm_id_vb_detection = true;
0238     p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
0239     p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
0240     p->host_support_fs_ls_low_power = true;
0241     p->host_ls_low_power_phy_clk = true;
0242 }
0243
0244 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
0245 {
0246     struct dwc2_core_params *p = &hsotg->params;
0247
0248     p->otg_caps.hnp_support = false;
0249     p->otg_caps.srp_support = false;
0250     p->otg_caps.otg_rev = 0x200;
0251     p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
0252     p->host_rx_fifo_size = 440;
0253     p->host_nperio_tx_fifo_size = 256;
0254     p->host_perio_tx_fifo_size = 256;
0255     p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
0256     p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
0257     p->lpm = false;
0258     p->lpm_clock_gating = false;
0259     p->besl = false;
0260     p->hird_threshold_en = false;
0261 }
0262
0263 const struct of_device_id dwc2_of_match_table[] = {
0264     { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
0265     { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
0266     { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params },
0267     { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params },
0268     { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params },
0269     { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params },
0270     { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params },
0271     { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
0272     { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
0273     { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
0274     { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
0275     { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
0276     { .compatible = "snps,dwc2" },
0277     { .compatible = "samsung,s3c6400-hsotg",
0278       .data = dwc2_set_s3c6400_params },
0279     { .compatible = "amlogic,meson8-usb",
0280       .data = dwc2_set_amlogic_params },
0281     { .compatible = "amlogic,meson8b-usb",
0282       .data = dwc2_set_amlogic_params },
0283     { .compatible = "amlogic,meson-gxbb-usb",
0284       .data = dwc2_set_amlogic_params },
0285     { .compatible = "amlogic,meson-g12a-usb",
0286       .data = dwc2_set_amlogic_g12a_params },
0287     { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
0288     { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
0289     { .compatible = "st,stm32f4x9-fsotg",
0290       .data = dwc2_set_stm32f4x9_fsotg_params },
0291     { .compatible = "st,stm32f4x9-hsotg" },
0292     { .compatible = "st,stm32f7-hsotg",
0293       .data = dwc2_set_stm32f7_hsotg_params },
0294     { .compatible = "st,stm32mp15-fsotg",
0295       .data = dwc2_set_stm32mp15_fsotg_params },
0296     { .compatible = "st,stm32mp15-hsotg",
0297       .data = dwc2_set_stm32mp15_hsotg_params },
0298     { .compatible = "intel,socfpga-agilex-hsotg",
0299       .data = dwc2_set_socfpga_agilex_params },
0300     {},
0301 };
0302 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
0303
0304 const struct acpi_device_id dwc2_acpi_match[] = {
0305     { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params },
0306     { },
0307 };
0308 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match);
0309
0310 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
0311 {
0312     switch (hsotg->hw_params.op_mode) {
0313     case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
0314         hsotg->params.otg_caps.hnp_support = true;
0315         hsotg->params.otg_caps.srp_support = true;
0316         break;
0317     case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
0318     case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
0319     case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
0320         hsotg->params.otg_caps.hnp_support = false;
0321         hsotg->params.otg_caps.srp_support = true;
0322         break;
0323     default:
0324         hsotg->params.otg_caps.hnp_support = false;
0325         hsotg->params.otg_caps.srp_support = false;
0326         break;
0327     }
0328 }
0329
0330 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
0331 {
0332     int val;
0333     u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
0334
0335     val = DWC2_PHY_TYPE_PARAM_FS;
0336     if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
0337         if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
0338             hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
0339             val = DWC2_PHY_TYPE_PARAM_UTMI;
0340         else
0341             val = DWC2_PHY_TYPE_PARAM_ULPI;
0342     }
0343
0344     if (dwc2_is_fs_iot(hsotg))
0345         hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
0346
0347     hsotg->params.phy_type = val;
0348 }
0349
0350 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
0351 {
0352     int val;
0353
0354     val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
0355         DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
0356
0357     if (dwc2_is_fs_iot(hsotg))
0358         val = DWC2_SPEED_PARAM_FULL;
0359
0360     if (dwc2_is_hs_iot(hsotg))
0361         val = DWC2_SPEED_PARAM_HIGH;
0362
0363     hsotg->params.speed = val;
0364 }
0365
0366 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
0367 {
0368     int val;
0369
0370     val = (hsotg->hw_params.utmi_phy_data_width ==
0371            GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
0372
0373     if (hsotg->phy) {
0374         /*
0375          * If using the generic PHY framework, check if the PHY bus
0376          * width is 8-bit and set the phyif appropriately.
0377          */
0378         if (phy_get_bus_width(hsotg->phy) == 8)
0379             val = 8;
0380     }
0381
0382     hsotg->params.phy_utmi_width = val;
0383 }
0384
0385 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
0386 {
0387     struct dwc2_core_params *p = &hsotg->params;
0388     int depth_average;
0389     int fifo_count;
0390     int i;
0391
0392     fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
0393
0394     memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
0395     depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
0396     for (i = 1; i <= fifo_count; i++)
0397         p->g_tx_fifo_size[i] = depth_average;
0398 }
0399
0400 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
0401 {
0402     int val;
0403
0404     if (hsotg->hw_params.hibernation)
0405         val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
0406     else if (hsotg->hw_params.power_optimized)
0407         val = DWC2_POWER_DOWN_PARAM_PARTIAL;
0408     else
0409         val = DWC2_POWER_DOWN_PARAM_NONE;
0410
0411     hsotg->params.power_down = val;
0412 }
0413
0414 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
0415 {
0416     struct dwc2_core_params *p = &hsotg->params;
0417
0418     p->lpm = hsotg->hw_params.lpm_mode;
0419     if (p->lpm) {
0420         p->lpm_clock_gating = true;
0421         p->besl = true;
0422         p->hird_threshold_en = true;
0423         p->hird_threshold = 4;
0424     } else {
0425         p->lpm_clock_gating = false;
0426         p->besl = false;
0427         p->hird_threshold_en = false;
0428     }
0429 }
0430
0431 /**
0432  * dwc2_set_default_params() - Set all core parameters to their
0433  * auto-detected default values.
0434  *
0435  * @hsotg: Programming view of the DWC_otg controller
0436  *
0437  */
0438 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
0439 {
0440     struct dwc2_hw_params *hw = &hsotg->hw_params;
0441     struct dwc2_core_params *p = &hsotg->params;
0442     bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
0443
0444     dwc2_set_param_otg_cap(hsotg);
0445     dwc2_set_param_phy_type(hsotg);
0446     dwc2_set_param_speed(hsotg);
0447     dwc2_set_param_phy_utmi_width(hsotg);
0448     dwc2_set_param_power_down(hsotg);
0449     dwc2_set_param_lpm(hsotg);
0450     p->phy_ulpi_ddr = false;
0451     p->phy_ulpi_ext_vbus = false;
0452
0453     p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
0454     p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
0455     p->i2c_enable = hw->i2c_enable;
0456     p->acg_enable = hw->acg_enable;
0457     p->ulpi_fs_ls = false;
0458     p->ts_dline = false;
0459     p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
0460     p->uframe_sched = true;
0461     p->external_id_pin_ctl = false;
0462     p->ipg_isoc_en = false;
0463     p->service_interval = false;
0464     p->max_packet_count = hw->max_packet_count;
0465     p->max_transfer_size = hw->max_transfer_size;
0466     p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
0467     p->ref_clk_per = 33333;
0468     p->sof_cnt_wkup_alert = 100;
0469
0470     if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
0471         (hsotg->dr_mode == USB_DR_MODE_OTG)) {
0472         p->host_dma = dma_capable;
0473         p->dma_desc_enable = false;
0474         p->dma_desc_fs_enable = false;
0475         p->host_support_fs_ls_low_power = false;
0476         p->host_ls_low_power_phy_clk = false;
0477         p->host_channels = hw->host_channels;
0478         p->host_rx_fifo_size = hw->rx_fifo_size;
0479         p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
0480         p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
0481     }
0482
0483     if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
0484         (hsotg->dr_mode == USB_DR_MODE_OTG)) {
0485         p->g_dma = dma_capable;
0486         p->g_dma_desc = hw->dma_desc_enable;
0487
0488         /*
0489          * The values for g_rx_fifo_size (2048) and
0490          * g_np_tx_fifo_size (1024) come from the legacy s3c
0491          * gadget driver. These defaults have been hard-coded
0492          * for some time so many platforms depend on these
0493          * values. Leave them as defaults for now and only
0494          * auto-detect if the hardware does not support the
0495          * default.
0496          */
0497         p->g_rx_fifo_size = 2048;
0498         p->g_np_tx_fifo_size = 1024;
0499         dwc2_set_param_tx_fifo_sizes(hsotg);
0500     }
0501 }
0502
0503 /**
0504  * dwc2_get_device_properties() - Read in device properties.
0505  *
0506  * @hsotg: Programming view of the DWC_otg controller
0507  *
0508  * Read in the device properties and adjust core parameters if needed.
0509  */
0510 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
0511 {
0512     struct dwc2_core_params *p = &hsotg->params;
0513     int num;
0514
0515     if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
0516         (hsotg->dr_mode == USB_DR_MODE_OTG)) {
0517         device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
0518                      &p->g_rx_fifo_size);
0519
0520         device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
0521                      &p->g_np_tx_fifo_size);
0522
0523         num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
0524         if (num > 0) {
0525             num = min(num, 15);
0526             memset(p->g_tx_fifo_size, 0,
0527                    sizeof(p->g_tx_fifo_size));
0528             device_property_read_u32_array(hsotg->dev,
0529                                "g-tx-fifo-size",
0530                                &p->g_tx_fifo_size[1],
0531                                num);
0532         }
0533
0534         of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps);
0535     }
0536
0537     if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
0538         p->oc_disable = true;
0539 }
0540
0541 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
0542 {
0543     int valid = 1;
0544
0545     if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) {
0546         /* check HNP && SRP capable */
0547         if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
0548             valid = 0;
0549     } else if (!hsotg->params.otg_caps.hnp_support) {
0550         /* check SRP only capable */
0551         if (hsotg->params.otg_caps.srp_support) {
0552             switch (hsotg->hw_params.op_mode) {
0553             case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
0554             case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
0555             case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
0556             case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
0557                 break;
0558             default:
0559                 valid = 0;
0560                 break;
0561             }
0562         }
0563         /* else: NO HNP && NO SRP capable: always valid */
0564     } else {
0565         valid = 0;
0566     }
0567
0568     if (!valid)
0569         dwc2_set_param_otg_cap(hsotg);
0570 }
0571
0572 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
0573 {
0574     int valid = 0;
0575     u32 hs_phy_type;
0576     u32 fs_phy_type;
0577
0578     hs_phy_type = hsotg->hw_params.hs_phy_type;
0579     fs_phy_type = hsotg->hw_params.fs_phy_type;
0580
0581     switch (hsotg->params.phy_type) {
0582     case DWC2_PHY_TYPE_PARAM_FS:
0583         if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
0584             valid = 1;
0585         break;
0586     case DWC2_PHY_TYPE_PARAM_UTMI:
0587         if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
0588             (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
0589             valid = 1;
0590         break;
0591     case DWC2_PHY_TYPE_PARAM_ULPI:
0592         if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
0593             (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
0594             valid = 1;
0595         break;
0596     default:
0597         break;
0598     }
0599
0600     if (!valid)
0601         dwc2_set_param_phy_type(hsotg);
0602 }
0603
0604 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
0605 {
0606     int valid = 1;
0607     int phy_type = hsotg->params.phy_type;
0608     int speed = hsotg->params.speed;
0609
0610     switch (speed) {
0611     case DWC2_SPEED_PARAM_HIGH:
0612         if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
0613             (phy_type == DWC2_PHY_TYPE_PARAM_FS))
0614             valid = 0;
0615         break;
0616     case DWC2_SPEED_PARAM_FULL:
0617     case DWC2_SPEED_PARAM_LOW:
0618         break;
0619     default:
0620         valid = 0;
0621         break;
0622     }
0623
0624     if (!valid)
0625         dwc2_set_param_speed(hsotg);
0626 }
0627
0628 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
0629 {
0630     int valid = 0;
0631     int param = hsotg->params.phy_utmi_width;
0632     int width = hsotg->hw_params.utmi_phy_data_width;
0633
0634     switch (width) {
0635     case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
0636         valid = (param == 8);
0637         break;
0638     case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
0639         valid = (param == 16);
0640         break;
0641     case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
0642         valid = (param == 8 || param == 16);
0643         break;
0644     }
0645
0646     if (!valid)
0647         dwc2_set_param_phy_utmi_width(hsotg);
0648 }
0649
0650 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
0651 {
0652     int param = hsotg->params.power_down;
0653
0654     switch (param) {
0655     case DWC2_POWER_DOWN_PARAM_NONE:
0656         break;
0657     case DWC2_POWER_DOWN_PARAM_PARTIAL:
0658         if (hsotg->hw_params.power_optimized)
0659             break;
0660         dev_dbg(hsotg->dev,
0661             "Partial power down isn't supported by HW\n");
0662         param = DWC2_POWER_DOWN_PARAM_NONE;
0663         break;
0664     case DWC2_POWER_DOWN_PARAM_HIBERNATION:
0665         if (hsotg->hw_params.hibernation)
0666             break;
0667         dev_dbg(hsotg->dev,
0668             "Hibernation isn't supported by HW\n");
0669         param = DWC2_POWER_DOWN_PARAM_NONE;
0670         break;
0671     default:
0672         dev_err(hsotg->dev,
0673             "%s: Invalid parameter power_down=%d\n",
0674             __func__, param);
0675         param = DWC2_POWER_DOWN_PARAM_NONE;
0676         break;
0677     }
0678
0679     hsotg->params.power_down = param;
0680 }
0681
0682 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
0683 {
0684     int fifo_count;
0685     int fifo;
0686     int min;
0687     u32 total = 0;
0688     u32 dptxfszn;
0689
0690     fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
0691     min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
0692
0693     for (fifo = 1; fifo <= fifo_count; fifo++)
0694         total += hsotg->params.g_tx_fifo_size[fifo];
0695
0696     if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
0697         dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
0698              __func__);
0699         dwc2_set_param_tx_fifo_sizes(hsotg);
0700     }
0701
0702     for (fifo = 1; fifo <= fifo_count; fifo++) {
0703         dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
0704
0705         if (hsotg->params.g_tx_fifo_size[fifo] < min ||
0706             hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
0707             dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
0708                  __func__, fifo,
0709                  hsotg->params.g_tx_fifo_size[fifo]);
0710             hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
0711         }
0712     }
0713 }
0714
0715 #define CHECK_RANGE(_param, _min, _max, _def) do {          \
0716         if ((int)(hsotg->params._param) < (_min) ||     \
0717             (hsotg->params._param) > (_max)) {          \
0718             dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
0719                  __func__, #_param, hsotg->params._param); \
0720             hsotg->params._param = (_def);          \
0721         }                           \
0722     } while (0)
0723
0724 #define CHECK_BOOL(_param, _check) do {                 \
0725         if (hsotg->params._param && !(_check)) {        \
0726             dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
0727                  __func__, #_param, hsotg->params._param); \
0728             hsotg->params._param = false;           \
0729         }                           \
0730     } while (0)
0731
0732 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
0733 {
0734     struct dwc2_hw_params *hw = &hsotg->hw_params;
0735     struct dwc2_core_params *p = &hsotg->params;
0736     bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
0737
0738     dwc2_check_param_otg_cap(hsotg);
0739     dwc2_check_param_phy_type(hsotg);
0740     dwc2_check_param_speed(hsotg);
0741     dwc2_check_param_phy_utmi_width(hsotg);
0742     dwc2_check_param_power_down(hsotg);
0743     CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
0744     CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
0745     CHECK_BOOL(i2c_enable, hw->i2c_enable);
0746     CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
0747     CHECK_BOOL(acg_enable, hw->acg_enable);
0748     CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
0749     CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
0750     CHECK_BOOL(lpm, hw->lpm_mode);
0751     CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
0752     CHECK_BOOL(besl, hsotg->params.lpm);
0753     CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
0754     CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
0755     CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
0756     CHECK_BOOL(service_interval, hw->service_interval_mode);
0757     CHECK_RANGE(max_packet_count,
0758             15, hw->max_packet_count,
0759             hw->max_packet_count);
0760     CHECK_RANGE(max_transfer_size,
0761             2047, hw->max_transfer_size,
0762             hw->max_transfer_size);
0763
0764     if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
0765         (hsotg->dr_mode == USB_DR_MODE_OTG)) {
0766         CHECK_BOOL(host_dma, dma_capable);
0767         CHECK_BOOL(dma_desc_enable, p->host_dma);
0768         CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
0769         CHECK_BOOL(host_ls_low_power_phy_clk,
0770                p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
0771         CHECK_RANGE(host_channels,
0772                 1, hw->host_channels,
0773                 hw->host_channels);
0774         CHECK_RANGE(host_rx_fifo_size,
0775                 16, hw->rx_fifo_size,
0776                 hw->rx_fifo_size);
0777         CHECK_RANGE(host_nperio_tx_fifo_size,
0778                 16, hw->host_nperio_tx_fifo_size,
0779                 hw->host_nperio_tx_fifo_size);
0780         CHECK_RANGE(host_perio_tx_fifo_size,
0781                 16, hw->host_perio_tx_fifo_size,
0782                 hw->host_perio_tx_fifo_size);
0783     }
0784
0785     if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
0786         (hsotg->dr_mode == USB_DR_MODE_OTG)) {
0787         CHECK_BOOL(g_dma, dma_capable);
0788         CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
0789         CHECK_RANGE(g_rx_fifo_size,
0790                 16, hw->rx_fifo_size,
0791                 hw->rx_fifo_size);
0792         CHECK_RANGE(g_np_tx_fifo_size,
0793                 16, hw->dev_nperio_tx_fifo_size,
0794                 hw->dev_nperio_tx_fifo_size);
0795         dwc2_check_param_tx_fifo_sizes(hsotg);
0796     }
0797 }
0798
0799 /*
0800  * Gets host hardware parameters. Forces host mode if not currently in
0801  * host mode. Should be called immediately after a core soft reset in
0802  * order to get the reset values.
0803  */
0804 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
0805 {
0806     struct dwc2_hw_params *hw = &hsotg->hw_params;
0807     u32 gnptxfsiz;
0808     u32 hptxfsiz;
0809
0810     if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
0811         return;
0812
0813     dwc2_force_mode(hsotg, true);
0814
0815     gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
0816     hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
0817
0818     hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
0819                        FIFOSIZE_DEPTH_SHIFT;
0820     hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
0821                       FIFOSIZE_DEPTH_SHIFT;
0822 }
0823
0824 /*
0825  * Gets device hardware parameters. Forces device mode if not
0826  * currently in device mode. Should be called immediately after a core
0827  * soft reset in order to get the reset values.
0828  */
0829 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
0830 {
0831     struct dwc2_hw_params *hw = &hsotg->hw_params;
0832     u32 gnptxfsiz;
0833     int fifo, fifo_count;
0834
0835     if (hsotg->dr_mode == USB_DR_MODE_HOST)
0836         return;
0837
0838     dwc2_force_mode(hsotg, false);
0839
0840     gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
0841
0842     fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
0843
0844     for (fifo = 1; fifo <= fifo_count; fifo++) {
0845         hw->g_tx_fifo_size[fifo] =
0846             (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
0847              FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
0848     }
0849
0850     hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
0851                        FIFOSIZE_DEPTH_SHIFT;
0852 }
0853
0854 /**
0855  * dwc2_get_hwparams() - During device initialization, read various hardware
0856  *                       configuration registers and interpret the contents.
0857  *
0858  * @hsotg: Programming view of the DWC_otg controller
0859  *
0860  */
0861 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
0862 {
0863     struct dwc2_hw_params *hw = &hsotg->hw_params;
0864     unsigned int width;
0865     u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
0866     u32 grxfsiz;
0867
0868     hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
0869     hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
0870     hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
0871     hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
0872     grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
0873
0874     /* hwcfg1 */
0875     hw->dev_ep_dirs = hwcfg1;
0876
0877     /* hwcfg2 */
0878     hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
0879               GHWCFG2_OP_MODE_SHIFT;
0880     hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
0881            GHWCFG2_ARCHITECTURE_SHIFT;
0882     hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
0883     hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
0884                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
0885     hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
0886               GHWCFG2_HS_PHY_TYPE_SHIFT;
0887     hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
0888               GHWCFG2_FS_PHY_TYPE_SHIFT;
0889     hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
0890              GHWCFG2_NUM_DEV_EP_SHIFT;
0891     hw->nperio_tx_q_depth =
0892         (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
0893         GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
0894     hw->host_perio_tx_q_depth =
0895         (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
0896         GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
0897     hw->dev_token_q_depth =
0898         (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
0899         GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
0900
0901     /* hwcfg3 */
0902     width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
0903         GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
0904     hw->max_transfer_size = (1 << (width + 11)) - 1;
0905     width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
0906         GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
0907     hw->max_packet_count = (1 << (width + 4)) - 1;
0908     hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
0909     hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
0910                   GHWCFG3_DFIFO_DEPTH_SHIFT;
0911     hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
0912
0913     /* hwcfg4 */
0914     hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
0915     hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
0916                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
0917     hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
0918                  GHWCFG4_NUM_IN_EPS_SHIFT;
0919     hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
0920     hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
0921     hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
0922     hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
0923                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
0924     hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
0925     hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
0926     hw->service_interval_mode = !!(hwcfg4 &
0927                        GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
0928
0929     /* fifo sizes */
0930     hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
0931                 GRXFSIZ_DEPTH_SHIFT;
0932     /*
0933      * Host specific hardware parameters. Reading these parameters
0934      * requires the controller to be in host mode. The mode will
0935      * be forced, if necessary, to read these values.
0936      */
0937     dwc2_get_host_hwparams(hsotg);
0938     dwc2_get_dev_hwparams(hsotg);
0939
0940     return 0;
0941 }
0942
0943 typedef void (*set_params_cb)(struct dwc2_hsotg *data);
0944
0945 int dwc2_init_params(struct dwc2_hsotg *hsotg)
0946 {
0947     const struct of_device_id *match;
0948     set_params_cb set_params;
0949
0950     dwc2_set_default_params(hsotg);
0951     dwc2_get_device_properties(hsotg);
0952
0953     match = of_match_device(dwc2_of_match_table, hsotg->dev);
0954     if (match && match->data) {
0955         set_params = match->data;
0956         set_params(hsotg);
0957     } else {
0958         const struct acpi_device_id *amatch;
0959
0960         amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev);
0961         if (amatch && amatch->driver_data) {
0962             set_params = (set_params_cb)amatch->driver_data;
0963             set_params(hsotg);
0964         }
0965     }
0966
0967     dwc2_check_params(hsotg);
0968
0969     return 0;
0970 }