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0001 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 0002 /* 0003 * hcd.h - DesignWare HS OTG Controller host-mode declarations 0004 * 0005 * Copyright (C) 2004-2013 Synopsys, Inc. 0006 * 0007 * Redistribution and use in source and binary forms, with or without 0008 * modification, are permitted provided that the following conditions 0009 * are met: 0010 * 1. Redistributions of source code must retain the above copyright 0011 * notice, this list of conditions, and the following disclaimer, 0012 * without modification. 0013 * 2. Redistributions in binary form must reproduce the above copyright 0014 * notice, this list of conditions and the following disclaimer in the 0015 * documentation and/or other materials provided with the distribution. 0016 * 3. The names of the above-listed copyright holders may not be used 0017 * to endorse or promote products derived from this software without 0018 * specific prior written permission. 0019 * 0020 * ALTERNATIVELY, this software may be distributed under the terms of the 0021 * GNU General Public License ("GPL") as published by the Free Software 0022 * Foundation; either version 2 of the License, or (at your option) any 0023 * later version. 0024 * 0025 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 0026 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 0027 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 0028 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 0029 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 0030 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 0031 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 0032 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 0033 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 0034 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 0035 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0036 */ 0037 #ifndef __DWC2_HCD_H__ 0038 #define __DWC2_HCD_H__ 0039 0040 /* 0041 * This file contains the structures, constants, and interfaces for the 0042 * Host Contoller Driver (HCD) 0043 * 0044 * The Host Controller Driver (HCD) is responsible for translating requests 0045 * from the USB Driver into the appropriate actions on the DWC_otg controller. 0046 * It isolates the USBD from the specifics of the controller by providing an 0047 * API to the USBD. 0048 */ 0049 0050 struct dwc2_qh; 0051 0052 /** 0053 * struct dwc2_host_chan - Software host channel descriptor 0054 * 0055 * @hc_num: Host channel number, used for register address lookup 0056 * @dev_addr: Address of the device 0057 * @ep_num: Endpoint of the device 0058 * @ep_is_in: Endpoint direction 0059 * @speed: Device speed. One of the following values: 0060 * - USB_SPEED_LOW 0061 * - USB_SPEED_FULL 0062 * - USB_SPEED_HIGH 0063 * @ep_type: Endpoint type. One of the following values: 0064 * - USB_ENDPOINT_XFER_CONTROL: 0 0065 * - USB_ENDPOINT_XFER_ISOC: 1 0066 * - USB_ENDPOINT_XFER_BULK: 2 0067 * - USB_ENDPOINT_XFER_INTR: 3 0068 * @max_packet: Max packet size in bytes 0069 * @data_pid_start: PID for initial transaction. 0070 * 0: DATA0 0071 * 1: DATA2 0072 * 2: DATA1 0073 * 3: MDATA (non-Control EP), 0074 * SETUP (Control EP) 0075 * @multi_count: Number of additional periodic transactions per 0076 * (micro)frame 0077 * @xfer_buf: Pointer to current transfer buffer position 0078 * @xfer_dma: DMA address of xfer_buf 0079 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not 0080 * DWORD aligned 0081 * @xfer_len: Total number of bytes to transfer 0082 * @xfer_count: Number of bytes transferred so far 0083 * @start_pkt_count: Packet count at start of transfer 0084 * @xfer_started: True if the transfer has been started 0085 * @do_ping: True if a PING request should be issued on this channel 0086 * @error_state: True if the error count for this transaction is non-zero 0087 * @halt_on_queue: True if this channel should be halted the next time a 0088 * request is queued for the channel. This is necessary in 0089 * slave mode if no request queue space is available when 0090 * an attempt is made to halt the channel. 0091 * @halt_pending: True if the host channel has been halted, but the core 0092 * is not finished flushing queued requests 0093 * @do_split: Enable split for the channel 0094 * @complete_split: Enable complete split 0095 * @hub_addr: Address of high speed hub for the split 0096 * @hub_port: Port of the low/full speed device for the split 0097 * @xact_pos: Split transaction position. One of the following values: 0098 * - DWC2_HCSPLT_XACTPOS_MID 0099 * - DWC2_HCSPLT_XACTPOS_BEGIN 0100 * - DWC2_HCSPLT_XACTPOS_END 0101 * - DWC2_HCSPLT_XACTPOS_ALL 0102 * @requests: Number of requests issued for this channel since it was 0103 * assigned to the current transfer (not counting PINGs) 0104 * @schinfo: Scheduling micro-frame bitmap 0105 * @ntd: Number of transfer descriptors for the transfer 0106 * @halt_status: Reason for halting the host channel 0107 * @hcint: Contents of the HCINT register when the interrupt came 0108 * @qh: QH for the transfer being processed by this channel 0109 * @hc_list_entry: For linking to list of host channels 0110 * @desc_list_addr: Current QH's descriptor list DMA address 0111 * @desc_list_sz: Current QH's descriptor list size 0112 * @split_order_list_entry: List entry for keeping track of the order of splits 0113 * 0114 * This structure represents the state of a single host channel when acting in 0115 * host mode. It contains the data items needed to transfer packets to an 0116 * endpoint via a host channel. 0117 */ 0118 struct dwc2_host_chan { 0119 u8 hc_num; 0120 0121 unsigned dev_addr:7; 0122 unsigned ep_num:4; 0123 unsigned ep_is_in:1; 0124 unsigned speed:4; 0125 unsigned ep_type:2; 0126 unsigned max_packet:11; 0127 unsigned data_pid_start:2; 0128 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 0129 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 0130 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 0131 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 0132 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 0133 0134 unsigned multi_count:2; 0135 0136 u8 *xfer_buf; 0137 dma_addr_t xfer_dma; 0138 dma_addr_t align_buf; 0139 u32 xfer_len; 0140 u32 xfer_count; 0141 u16 start_pkt_count; 0142 u8 xfer_started; 0143 u8 do_ping; 0144 u8 error_state; 0145 u8 halt_on_queue; 0146 u8 halt_pending; 0147 u8 do_split; 0148 u8 complete_split; 0149 u8 hub_addr; 0150 u8 hub_port; 0151 u8 xact_pos; 0152 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 0153 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 0154 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 0155 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 0156 0157 u8 requests; 0158 u8 schinfo; 0159 u16 ntd; 0160 enum dwc2_halt_status halt_status; 0161 u32 hcint; 0162 struct dwc2_qh *qh; 0163 struct list_head hc_list_entry; 0164 dma_addr_t desc_list_addr; 0165 u32 desc_list_sz; 0166 struct list_head split_order_list_entry; 0167 }; 0168 0169 struct dwc2_hcd_pipe_info { 0170 u8 dev_addr; 0171 u8 ep_num; 0172 u8 pipe_type; 0173 u8 pipe_dir; 0174 u16 maxp; 0175 u16 maxp_mult; 0176 }; 0177 0178 struct dwc2_hcd_iso_packet_desc { 0179 u32 offset; 0180 u32 length; 0181 u32 actual_length; 0182 u32 status; 0183 }; 0184 0185 struct dwc2_qtd; 0186 0187 struct dwc2_hcd_urb { 0188 void *priv; 0189 struct dwc2_qtd *qtd; 0190 void *buf; 0191 dma_addr_t dma; 0192 void *setup_packet; 0193 dma_addr_t setup_dma; 0194 u32 length; 0195 u32 actual_length; 0196 u32 status; 0197 u32 error_count; 0198 u32 packet_count; 0199 u32 flags; 0200 u16 interval; 0201 struct dwc2_hcd_pipe_info pipe_info; 0202 struct dwc2_hcd_iso_packet_desc iso_descs[]; 0203 }; 0204 0205 /* Phases for control transfers */ 0206 enum dwc2_control_phase { 0207 DWC2_CONTROL_SETUP, 0208 DWC2_CONTROL_DATA, 0209 DWC2_CONTROL_STATUS, 0210 }; 0211 0212 /* Transaction types */ 0213 enum dwc2_transaction_type { 0214 DWC2_TRANSACTION_NONE, 0215 DWC2_TRANSACTION_PERIODIC, 0216 DWC2_TRANSACTION_NON_PERIODIC, 0217 DWC2_TRANSACTION_ALL, 0218 }; 0219 0220 /* The number of elements per LS bitmap (per port on multi_tt) */ 0221 #define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \ 0222 BITS_PER_LONG) 0223 0224 /** 0225 * struct dwc2_tt - dwc2 data associated with a usb_tt 0226 * 0227 * @refcount: Number of Queue Heads (QHs) holding a reference. 0228 * @usb_tt: Pointer back to the official usb_tt. 0229 * @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted 0230 * for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP 0231 * elements (so sizeof(long) times that in bytes). 0232 * 0233 * This structure is stored in the hcpriv of the official usb_tt. 0234 */ 0235 struct dwc2_tt { 0236 int refcount; 0237 struct usb_tt *usb_tt; 0238 unsigned long periodic_bitmaps[]; 0239 }; 0240 0241 /** 0242 * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus. 0243 * 0244 * @start_schedule_us: The start time on the main bus schedule. Note that 0245 * the main bus schedule is tightly packed and this 0246 * time should be interpreted as tightly packed (so 0247 * uFrame 0 starts at 0 us, uFrame 1 starts at 100 us 0248 * instead of 125 us). 0249 * @duration_us: How long this transfer goes. 0250 */ 0251 0252 struct dwc2_hs_transfer_time { 0253 u32 start_schedule_us; 0254 u16 duration_us; 0255 }; 0256 0257 /** 0258 * struct dwc2_qh - Software queue head structure 0259 * 0260 * @hsotg: The HCD state structure for the DWC OTG controller 0261 * @ep_type: Endpoint type. One of the following values: 0262 * - USB_ENDPOINT_XFER_CONTROL 0263 * - USB_ENDPOINT_XFER_BULK 0264 * - USB_ENDPOINT_XFER_INT 0265 * - USB_ENDPOINT_XFER_ISOC 0266 * @ep_is_in: Endpoint direction 0267 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 0268 * @maxp_mult: Multiplier for maxp 0269 * @dev_speed: Device speed. One of the following values: 0270 * - USB_SPEED_LOW 0271 * - USB_SPEED_FULL 0272 * - USB_SPEED_HIGH 0273 * @data_toggle: Determines the PID of the next data packet for 0274 * non-controltransfers. Ignored for control transfers. 0275 * One of the following values: 0276 * - DWC2_HC_PID_DATA0 0277 * - DWC2_HC_PID_DATA1 0278 * @ping_state: Ping state 0279 * @do_split: Full/low speed endpoint on high-speed hub requires split 0280 * @td_first: Index of first activated isochronous transfer descriptor 0281 * @td_last: Index of last activated isochronous transfer descriptor 0282 * @host_us: Bandwidth in microseconds per transfer as seen by host 0283 * @device_us: Bandwidth in microseconds per transfer as seen by device 0284 * @host_interval: Interval between transfers as seen by the host. If 0285 * the host is high speed and the device is low speed this 0286 * will be 8 times device interval. 0287 * @device_interval: Interval between transfers as seen by the device. 0288 * interval. 0289 * @next_active_frame: (Micro)frame _before_ we next need to put something on 0290 * the bus. We'll move the qh to active here. If the 0291 * host is in high speed mode this will be a uframe. If 0292 * the host is in low speed mode this will be a full frame. 0293 * @start_active_frame: If we are partway through a split transfer, this will be 0294 * what next_active_frame was when we started. Otherwise 0295 * it should always be the same as next_active_frame. 0296 * @num_hs_transfers: Number of transfers in hs_transfers. 0297 * Normally this is 1 but can be more than one for splits. 0298 * Always >= 1 unless the host is in low/full speed mode. 0299 * @hs_transfers: Transfers that are scheduled as seen by the high speed 0300 * bus. Not used if host is in low or full speed mode (but 0301 * note that it IS USED if the device is low or full speed 0302 * as long as the HOST is in high speed mode). 0303 * @ls_start_schedule_slice: Start time (in slices) on the low speed bus 0304 * schedule that's being used by this device. This 0305 * will be on the periodic_bitmap in a 0306 * "struct dwc2_tt". Not used if this device is high 0307 * speed. Note that this is in "schedule slice" which 0308 * is tightly packed. 0309 * @ntd: Actual number of transfer descriptors in a list 0310 * @dw_align_buf: Used instead of original buffer if its physical address 0311 * is not dword-aligned 0312 * @dw_align_buf_dma: DMA address for dw_align_buf 0313 * @qtd_list: List of QTDs for this QH 0314 * @channel: Host channel currently processing transfers for this QH 0315 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 0316 * schedule 0317 * @desc_list: List of transfer descriptors 0318 * @desc_list_dma: Physical address of desc_list 0319 * @desc_list_sz: Size of descriptors list 0320 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 0321 * descriptor and indicates original XferSize value for the 0322 * descriptor 0323 * @unreserve_timer: Timer for releasing periodic reservation. 0324 * @wait_timer: Timer used to wait before re-queuing. 0325 * @dwc_tt: Pointer to our tt info (or NULL if no tt). 0326 * @ttport: Port number within our tt. 0327 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 0328 * @unreserve_pending: True if we planned to unreserve but haven't yet. 0329 * @schedule_low_speed: True if we have a low/full speed component (either the 0330 * host is in low/full speed mode or do_split). 0331 * @want_wait: We should wait before re-queuing; only matters for non- 0332 * periodic transfers and is ignored for periodic ones. 0333 * @wait_timer_cancel: Set to true to cancel the wait_timer. 0334 * 0335 * @tt_buffer_dirty: True if EP's TT buffer is not clean. 0336 * A Queue Head (QH) holds the static characteristics of an endpoint and 0337 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 0338 * be entered in either the non-periodic or periodic schedule. 0339 */ 0340 struct dwc2_qh { 0341 struct dwc2_hsotg *hsotg; 0342 u8 ep_type; 0343 u8 ep_is_in; 0344 u16 maxp; 0345 u16 maxp_mult; 0346 u8 dev_speed; 0347 u8 data_toggle; 0348 u8 ping_state; 0349 u8 do_split; 0350 u8 td_first; 0351 u8 td_last; 0352 u16 host_us; 0353 u16 device_us; 0354 u16 host_interval; 0355 u16 device_interval; 0356 u16 next_active_frame; 0357 u16 start_active_frame; 0358 s16 num_hs_transfers; 0359 struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES]; 0360 u32 ls_start_schedule_slice; 0361 u16 ntd; 0362 u8 *dw_align_buf; 0363 dma_addr_t dw_align_buf_dma; 0364 struct list_head qtd_list; 0365 struct dwc2_host_chan *channel; 0366 struct list_head qh_list_entry; 0367 struct dwc2_dma_desc *desc_list; 0368 dma_addr_t desc_list_dma; 0369 u32 desc_list_sz; 0370 u32 *n_bytes; 0371 struct timer_list unreserve_timer; 0372 struct hrtimer wait_timer; 0373 struct dwc2_tt *dwc_tt; 0374 int ttport; 0375 unsigned tt_buffer_dirty:1; 0376 unsigned unreserve_pending:1; 0377 unsigned schedule_low_speed:1; 0378 unsigned want_wait:1; 0379 unsigned wait_timer_cancel:1; 0380 }; 0381 0382 /** 0383 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 0384 * 0385 * @control_phase: Current phase for control transfers (Setup, Data, or 0386 * Status) 0387 * @in_process: Indicates if this QTD is currently processed by HW 0388 * @data_toggle: Determines the PID of the next data packet for the 0389 * data phase of control transfers. Ignored for other 0390 * transfer types. One of the following values: 0391 * - DWC2_HC_PID_DATA0 0392 * - DWC2_HC_PID_DATA1 0393 * @complete_split: Keeps track of the current split type for FS/LS 0394 * endpoints on a HS Hub 0395 * @isoc_split_pos: Position of the ISOC split in full/low speed 0396 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 0397 * transfer. A frame descriptor describes the buffer 0398 * position and length of the data to be transferred in the 0399 * next scheduled (micro)frame of an isochronous transfer. 0400 * It also holds status for that transaction. The frame 0401 * index starts at 0. 0402 * @isoc_split_offset: Position of the ISOC split in the buffer for the 0403 * current frame 0404 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 0405 * @error_count: Holds the number of bus errors that have occurred for 0406 * a transaction within this transfer 0407 * @n_desc: Number of DMA descriptors for this QTD 0408 * @isoc_frame_index_last: Last activated frame (packet) index, used in 0409 * descriptor DMA mode only 0410 * @num_naks: Number of NAKs received on this QTD. 0411 * @urb: URB for this transfer 0412 * @qh: Queue head for this QTD 0413 * @qtd_list_entry: For linking to the QH's list of QTDs 0414 * @isoc_td_first: Index of first activated isochronous transfer 0415 * descriptor in Descriptor DMA mode 0416 * @isoc_td_last: Index of last activated isochronous transfer 0417 * descriptor in Descriptor DMA mode 0418 * 0419 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 0420 * interrupt, or isochronous transfer. A single QTD is created for each URB 0421 * (of one of these types) submitted to the HCD. The transfer associated with 0422 * a QTD may require one or multiple transactions. 0423 * 0424 * A QTD is linked to a Queue Head, which is entered in either the 0425 * non-periodic or periodic schedule for execution. When a QTD is chosen for 0426 * execution, some or all of its transactions may be executed. After 0427 * execution, the state of the QTD is updated. The QTD may be retired if all 0428 * its transactions are complete or if an error occurred. Otherwise, it 0429 * remains in the schedule so more transactions can be executed later. 0430 */ 0431 struct dwc2_qtd { 0432 enum dwc2_control_phase control_phase; 0433 u8 in_process; 0434 u8 data_toggle; 0435 u8 complete_split; 0436 u8 isoc_split_pos; 0437 u16 isoc_frame_index; 0438 u16 isoc_split_offset; 0439 u16 isoc_td_last; 0440 u16 isoc_td_first; 0441 u32 ssplit_out_xfer_count; 0442 u8 error_count; 0443 u8 n_desc; 0444 u16 isoc_frame_index_last; 0445 u16 num_naks; 0446 struct dwc2_hcd_urb *urb; 0447 struct dwc2_qh *qh; 0448 struct list_head qtd_list_entry; 0449 }; 0450 0451 #ifdef DEBUG 0452 struct hc_xfer_info { 0453 struct dwc2_hsotg *hsotg; 0454 struct dwc2_host_chan *chan; 0455 }; 0456 #endif 0457 0458 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 0459 0460 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 0461 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 0462 { 0463 return (struct usb_hcd *)hsotg->priv; 0464 } 0465 0466 /* 0467 * Inline used to disable one channel interrupt. Channel interrupts are 0468 * disabled when the channel is halted or released by the interrupt handler. 0469 * There is no need to handle further interrupts of that type until the 0470 * channel is re-assigned. In fact, subsequent handling may cause crashes 0471 * because the channel structures are cleaned up when the channel is released. 0472 */ 0473 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 0474 { 0475 u32 mask = dwc2_readl(hsotg, HCINTMSK(chnum)); 0476 0477 mask &= ~intr; 0478 dwc2_writel(hsotg, mask, HCINTMSK(chnum)); 0479 } 0480 0481 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 0482 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 0483 enum dwc2_halt_status halt_status); 0484 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 0485 struct dwc2_host_chan *chan); 0486 0487 /* 0488 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 0489 * are read as 1, they won't clear when written back. 0490 */ 0491 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 0492 { 0493 u32 hprt0 = dwc2_readl(hsotg, HPRT0); 0494 0495 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 0496 return hprt0; 0497 } 0498 0499 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 0500 { 0501 return pipe->ep_num; 0502 } 0503 0504 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 0505 { 0506 return pipe->pipe_type; 0507 } 0508 0509 static inline u16 dwc2_hcd_get_maxp(struct dwc2_hcd_pipe_info *pipe) 0510 { 0511 return pipe->maxp; 0512 } 0513 0514 static inline u16 dwc2_hcd_get_maxp_mult(struct dwc2_hcd_pipe_info *pipe) 0515 { 0516 return pipe->maxp_mult; 0517 } 0518 0519 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 0520 { 0521 return pipe->dev_addr; 0522 } 0523 0524 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 0525 { 0526 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 0527 } 0528 0529 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 0530 { 0531 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 0532 } 0533 0534 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 0535 { 0536 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 0537 } 0538 0539 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 0540 { 0541 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 0542 } 0543 0544 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 0545 { 0546 return pipe->pipe_dir == USB_DIR_IN; 0547 } 0548 0549 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 0550 { 0551 return !dwc2_hcd_is_pipe_in(pipe); 0552 } 0553 0554 int dwc2_hcd_init(struct dwc2_hsotg *hsotg); 0555 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 0556 0557 /* Transaction Execution Functions */ 0558 enum dwc2_transaction_type dwc2_hcd_select_transactions( 0559 struct dwc2_hsotg *hsotg); 0560 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 0561 enum dwc2_transaction_type tr_type); 0562 0563 /* Schedule Queue Functions */ 0564 /* Implemented in hcd_queue.c */ 0565 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 0566 struct dwc2_hcd_urb *urb, 0567 gfp_t mem_flags); 0568 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 0569 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 0570 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 0571 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 0572 int sched_csplit); 0573 0574 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 0575 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 0576 struct dwc2_qh *qh); 0577 0578 /* Unlinks and frees a QTD */ 0579 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 0580 struct dwc2_qtd *qtd, 0581 struct dwc2_qh *qh) 0582 { 0583 list_del(&qtd->qtd_list_entry); 0584 kfree(qtd); 0585 } 0586 0587 /* Descriptor DMA support functions */ 0588 void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 0589 struct dwc2_qh *qh); 0590 void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 0591 struct dwc2_host_chan *chan, int chnum, 0592 enum dwc2_halt_status halt_status); 0593 0594 int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 0595 gfp_t mem_flags); 0596 void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 0597 0598 /* Check if QH is non-periodic */ 0599 #define dwc2_qh_is_non_per(_qh_ptr_) \ 0600 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 0601 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 0602 0603 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 0604 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 0605 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 0606 static inline bool dbg_urb(struct urb *urb) { return true; } 0607 static inline bool dbg_perio(void) { return true; } 0608 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 0609 static inline bool dbg_hc(struct dwc2_host_chan *hc) 0610 { 0611 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 0612 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 0613 } 0614 0615 static inline bool dbg_qh(struct dwc2_qh *qh) 0616 { 0617 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 0618 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 0619 } 0620 0621 static inline bool dbg_urb(struct urb *urb) 0622 { 0623 return usb_pipetype(urb->pipe) == PIPE_BULK || 0624 usb_pipetype(urb->pipe) == PIPE_CONTROL; 0625 } 0626 0627 static inline bool dbg_perio(void) { return false; } 0628 #endif 0629 0630 /* 0631 * Returns true if frame1 index is greater than frame2 index. The comparison 0632 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the 0633 * frame number when the max index frame number is reached. 0634 */ 0635 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2) 0636 { 0637 u16 diff = fr_idx1 - fr_idx2; 0638 u16 sign = diff & (FRLISTEN_64_SIZE >> 1); 0639 0640 return diff && !sign; 0641 } 0642 0643 /* 0644 * Returns true if frame1 is less than or equal to frame2. The comparison is 0645 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 0646 * frame number when the max frame number is reached. 0647 */ 0648 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 0649 { 0650 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 0651 } 0652 0653 /* 0654 * Returns true if frame1 is greater than frame2. The comparison is done 0655 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 0656 * number when the max frame number is reached. 0657 */ 0658 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 0659 { 0660 return (frame1 != frame2) && 0661 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 0662 } 0663 0664 /* 0665 * Increments frame by the amount specified by inc. The addition is done 0666 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 0667 */ 0668 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 0669 { 0670 return (frame + inc) & HFNUM_MAX_FRNUM; 0671 } 0672 0673 static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec) 0674 { 0675 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM; 0676 } 0677 0678 static inline u16 dwc2_full_frame_num(u16 frame) 0679 { 0680 return (frame & HFNUM_MAX_FRNUM) >> 3; 0681 } 0682 0683 static inline u16 dwc2_micro_frame_num(u16 frame) 0684 { 0685 return frame & 0x7; 0686 } 0687 0688 /* 0689 * Returns the Core Interrupt Status register contents, ANDed with the Core 0690 * Interrupt Mask register contents 0691 */ 0692 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 0693 { 0694 return dwc2_readl(hsotg, GINTSTS) & 0695 dwc2_readl(hsotg, GINTMSK); 0696 } 0697 0698 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 0699 { 0700 return dwc2_urb->status; 0701 } 0702 0703 static inline u32 dwc2_hcd_urb_get_actual_length( 0704 struct dwc2_hcd_urb *dwc2_urb) 0705 { 0706 return dwc2_urb->actual_length; 0707 } 0708 0709 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 0710 { 0711 return dwc2_urb->error_count; 0712 } 0713 0714 static inline void dwc2_hcd_urb_set_iso_desc_params( 0715 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 0716 u32 length) 0717 { 0718 dwc2_urb->iso_descs[desc_num].offset = offset; 0719 dwc2_urb->iso_descs[desc_num].length = length; 0720 } 0721 0722 static inline u32 dwc2_hcd_urb_get_iso_desc_status( 0723 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 0724 { 0725 return dwc2_urb->iso_descs[desc_num].status; 0726 } 0727 0728 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 0729 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 0730 { 0731 return dwc2_urb->iso_descs[desc_num].actual_length; 0732 } 0733 0734 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 0735 struct usb_host_endpoint *ep) 0736 { 0737 struct dwc2_qh *qh = ep->hcpriv; 0738 0739 if (qh && !list_empty(&qh->qh_list_entry)) 0740 return 1; 0741 0742 return 0; 0743 } 0744 0745 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 0746 struct usb_host_endpoint *ep) 0747 { 0748 struct dwc2_qh *qh = ep->hcpriv; 0749 0750 if (!qh) { 0751 WARN_ON(1); 0752 return 0; 0753 } 0754 0755 return qh->host_us; 0756 } 0757 0758 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 0759 struct dwc2_host_chan *chan, int chnum, 0760 struct dwc2_qtd *qtd); 0761 0762 /* HCD Core API */ 0763 0764 /** 0765 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 0766 * 0767 * @hsotg: The DWC2 HCD 0768 * 0769 * Returns IRQ_HANDLED if interrupt is handled 0770 * Return IRQ_NONE if interrupt is not handled 0771 */ 0772 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 0773 0774 /** 0775 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 0776 * 0777 * @hsotg: The DWC2 HCD 0778 */ 0779 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 0780 0781 /** 0782 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 0783 * and 0 otherwise 0784 * 0785 * @hsotg: The DWC2 HCD 0786 */ 0787 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 0788 0789 /** 0790 * dwc2_hcd_dump_state() - Dumps hsotg state 0791 * 0792 * @hsotg: The DWC2 HCD 0793 * 0794 * NOTE: This function will be removed once the peripheral controller code 0795 * is integrated and the driver is stable 0796 */ 0797 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 0798 0799 /* URB interface */ 0800 0801 /* Transfer flags */ 0802 #define URB_GIVEBACK_ASAP 0x1 0803 #define URB_SEND_ZERO_PACKET 0x2 0804 0805 /* Host driver callbacks */ 0806 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, 0807 void *context, gfp_t mem_flags, 0808 int *ttport); 0809 0810 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, 0811 struct dwc2_tt *dwc_tt); 0812 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 0813 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 0814 int status); 0815 0816 #endif /* __DWC2_HCD_H__ */
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