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0001 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
0002 /*
0003  * core.c - DesignWare HS OTG Controller common routines
0004  *
0005  * Copyright (C) 2004-2013 Synopsys, Inc.
0006  *
0007  * Redistribution and use in source and binary forms, with or without
0008  * modification, are permitted provided that the following conditions
0009  * are met:
0010  * 1. Redistributions of source code must retain the above copyright
0011  *    notice, this list of conditions, and the following disclaimer,
0012  *    without modification.
0013  * 2. Redistributions in binary form must reproduce the above copyright
0014  *    notice, this list of conditions and the following disclaimer in the
0015  *    documentation and/or other materials provided with the distribution.
0016  * 3. The names of the above-listed copyright holders may not be used
0017  *    to endorse or promote products derived from this software without
0018  *    specific prior written permission.
0019  *
0020  * ALTERNATIVELY, this software may be distributed under the terms of the
0021  * GNU General Public License ("GPL") as published by the Free Software
0022  * Foundation; either version 2 of the License, or (at your option) any
0023  * later version.
0024  *
0025  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
0026  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
0027  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
0028  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
0029  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0030  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
0031  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
0032  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
0033  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
0034  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0035  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0036  */
0037 
0038 /*
0039  * The Core code provides basic services for accessing and managing the
0040  * DWC_otg hardware. These services are used by both the Host Controller
0041  * Driver and the Peripheral Controller Driver.
0042  */
0043 #include <linux/kernel.h>
0044 #include <linux/module.h>
0045 #include <linux/moduleparam.h>
0046 #include <linux/spinlock.h>
0047 #include <linux/interrupt.h>
0048 #include <linux/dma-mapping.h>
0049 #include <linux/delay.h>
0050 #include <linux/io.h>
0051 #include <linux/slab.h>
0052 #include <linux/usb.h>
0053 
0054 #include <linux/usb/hcd.h>
0055 #include <linux/usb/ch11.h>
0056 
0057 #include "core.h"
0058 #include "hcd.h"
0059 
0060 /**
0061  * dwc2_backup_global_registers() - Backup global controller registers.
0062  * When suspending usb bus, registers needs to be backuped
0063  * if controller power is disabled once suspended.
0064  *
0065  * @hsotg: Programming view of the DWC_otg controller
0066  */
0067 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
0068 {
0069     struct dwc2_gregs_backup *gr;
0070 
0071     dev_dbg(hsotg->dev, "%s\n", __func__);
0072 
0073     /* Backup global regs */
0074     gr = &hsotg->gr_backup;
0075 
0076     gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
0077     gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
0078     gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
0079     gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
0080     gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
0081     gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
0082     gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
0083     gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
0084     gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
0085     gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
0086     gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
0087 
0088     gr->valid = true;
0089     return 0;
0090 }
0091 
0092 /**
0093  * dwc2_restore_global_registers() - Restore controller global registers.
0094  * When resuming usb bus, device registers needs to be restored
0095  * if controller power were disabled.
0096  *
0097  * @hsotg: Programming view of the DWC_otg controller
0098  */
0099 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
0100 {
0101     struct dwc2_gregs_backup *gr;
0102 
0103     dev_dbg(hsotg->dev, "%s\n", __func__);
0104 
0105     /* Restore global regs */
0106     gr = &hsotg->gr_backup;
0107     if (!gr->valid) {
0108         dev_err(hsotg->dev, "%s: no global registers to restore\n",
0109             __func__);
0110         return -EINVAL;
0111     }
0112     gr->valid = false;
0113 
0114     dwc2_writel(hsotg, 0xffffffff, GINTSTS);
0115     dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
0116     dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
0117     dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
0118     dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
0119     dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
0120     dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
0121     dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
0122     dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
0123     dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
0124     dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
0125     dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
0126 
0127     return 0;
0128 }
0129 
0130 /**
0131  * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
0132  *
0133  * @hsotg: Programming view of the DWC_otg controller
0134  * @rem_wakeup: indicates whether resume is initiated by Reset.
0135  * @restore: Controller registers need to be restored
0136  */
0137 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
0138                  bool restore)
0139 {
0140     struct dwc2_gregs_backup *gr;
0141 
0142     gr = &hsotg->gr_backup;
0143 
0144     /*
0145      * Restore host or device regisers with the same mode core enterted
0146      * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup
0147      * value of the "gotgctl" register.
0148      */
0149     if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
0150         return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup,
0151                              restore);
0152     else
0153         return dwc2_gadget_exit_partial_power_down(hsotg, restore);
0154 }
0155 
0156 /**
0157  * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
0158  *
0159  * @hsotg: Programming view of the DWC_otg controller
0160  */
0161 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
0162 {
0163     if (dwc2_is_host_mode(hsotg))
0164         return dwc2_host_enter_partial_power_down(hsotg);
0165     else
0166         return dwc2_gadget_enter_partial_power_down(hsotg);
0167 }
0168 
0169 /**
0170  * dwc2_restore_essential_regs() - Restore essiential regs of core.
0171  *
0172  * @hsotg: Programming view of the DWC_otg controller
0173  * @rmode: Restore mode, enabled in case of remote-wakeup.
0174  * @is_host: Host or device mode.
0175  */
0176 static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
0177                     int is_host)
0178 {
0179     u32 pcgcctl;
0180     struct dwc2_gregs_backup *gr;
0181     struct dwc2_dregs_backup *dr;
0182     struct dwc2_hregs_backup *hr;
0183 
0184     gr = &hsotg->gr_backup;
0185     dr = &hsotg->dr_backup;
0186     hr = &hsotg->hr_backup;
0187 
0188     dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
0189 
0190     /* Load restore values for [31:14] bits */
0191     pcgcctl = (gr->pcgcctl & 0xffffc000);
0192     /* If High Speed */
0193     if (is_host) {
0194         if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
0195             pcgcctl |= BIT(17);
0196     } else {
0197         if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
0198             pcgcctl |= BIT(17);
0199     }
0200     dwc2_writel(hsotg, pcgcctl, PCGCTL);
0201 
0202     /* Umnask global Interrupt in GAHBCFG and restore it */
0203     dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
0204 
0205     /* Clear all pending interupts */
0206     dwc2_writel(hsotg, 0xffffffff, GINTSTS);
0207 
0208     /* Unmask restore done interrupt */
0209     dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
0210 
0211     /* Restore GUSBCFG and HCFG/DCFG */
0212     dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
0213 
0214     if (is_host) {
0215         dwc2_writel(hsotg, hr->hcfg, HCFG);
0216         if (rmode)
0217             pcgcctl |= PCGCTL_RESTOREMODE;
0218         dwc2_writel(hsotg, pcgcctl, PCGCTL);
0219         udelay(10);
0220 
0221         pcgcctl |= PCGCTL_ESS_REG_RESTORED;
0222         dwc2_writel(hsotg, pcgcctl, PCGCTL);
0223         udelay(10);
0224     } else {
0225         dwc2_writel(hsotg, dr->dcfg, DCFG);
0226         if (!rmode)
0227             pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
0228         dwc2_writel(hsotg, pcgcctl, PCGCTL);
0229         udelay(10);
0230 
0231         pcgcctl |= PCGCTL_ESS_REG_RESTORED;
0232         dwc2_writel(hsotg, pcgcctl, PCGCTL);
0233         udelay(10);
0234     }
0235 }
0236 
0237 /**
0238  * dwc2_hib_restore_common() - Common part of restore routine.
0239  *
0240  * @hsotg: Programming view of the DWC_otg controller
0241  * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
0242  * @is_host: Host or device mode.
0243  */
0244 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
0245                  int is_host)
0246 {
0247     u32 gpwrdn;
0248 
0249     /* Switch-on voltage to the core */
0250     gpwrdn = dwc2_readl(hsotg, GPWRDN);
0251     gpwrdn &= ~GPWRDN_PWRDNSWTCH;
0252     dwc2_writel(hsotg, gpwrdn, GPWRDN);
0253     udelay(10);
0254 
0255     /* Reset core */
0256     gpwrdn = dwc2_readl(hsotg, GPWRDN);
0257     gpwrdn &= ~GPWRDN_PWRDNRSTN;
0258     dwc2_writel(hsotg, gpwrdn, GPWRDN);
0259     udelay(10);
0260 
0261     /* Enable restore from PMU */
0262     gpwrdn = dwc2_readl(hsotg, GPWRDN);
0263     gpwrdn |= GPWRDN_RESTORE;
0264     dwc2_writel(hsotg, gpwrdn, GPWRDN);
0265     udelay(10);
0266 
0267     /* Disable Power Down Clamp */
0268     gpwrdn = dwc2_readl(hsotg, GPWRDN);
0269     gpwrdn &= ~GPWRDN_PWRDNCLMP;
0270     dwc2_writel(hsotg, gpwrdn, GPWRDN);
0271     udelay(50);
0272 
0273     if (!is_host && rem_wakeup)
0274         udelay(70);
0275 
0276     /* Deassert reset core */
0277     gpwrdn = dwc2_readl(hsotg, GPWRDN);
0278     gpwrdn |= GPWRDN_PWRDNRSTN;
0279     dwc2_writel(hsotg, gpwrdn, GPWRDN);
0280     udelay(10);
0281 
0282     /* Disable PMU interrupt */
0283     gpwrdn = dwc2_readl(hsotg, GPWRDN);
0284     gpwrdn &= ~GPWRDN_PMUINTSEL;
0285     dwc2_writel(hsotg, gpwrdn, GPWRDN);
0286     udelay(10);
0287 
0288     /* Set Restore Essential Regs bit in PCGCCTL register */
0289     dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
0290 
0291     /*
0292      * Wait For Restore_done Interrupt. This mechanism of polling the
0293      * interrupt is introduced to avoid any possible race conditions
0294      */
0295     if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
0296                     20000)) {
0297         dev_dbg(hsotg->dev,
0298             "%s: Restore Done wasn't generated here\n",
0299             __func__);
0300     } else {
0301         dev_dbg(hsotg->dev, "restore done  generated here\n");
0302 
0303         /*
0304          * To avoid restore done interrupt storm after restore is
0305          * generated clear GINTSTS_RESTOREDONE bit.
0306          */
0307         dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS);
0308     }
0309 }
0310 
0311 /**
0312  * dwc2_wait_for_mode() - Waits for the controller mode.
0313  * @hsotg:  Programming view of the DWC_otg controller.
0314  * @host_mode:  If true, waits for host mode, otherwise device mode.
0315  */
0316 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
0317                    bool host_mode)
0318 {
0319     ktime_t start;
0320     ktime_t end;
0321     unsigned int timeout = 110;
0322 
0323     dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
0324          host_mode ? "host" : "device");
0325 
0326     start = ktime_get();
0327 
0328     while (1) {
0329         s64 ms;
0330 
0331         if (dwc2_is_host_mode(hsotg) == host_mode) {
0332             dev_vdbg(hsotg->dev, "%s mode set\n",
0333                  host_mode ? "Host" : "Device");
0334             break;
0335         }
0336 
0337         end = ktime_get();
0338         ms = ktime_to_ms(ktime_sub(end, start));
0339 
0340         if (ms >= (s64)timeout) {
0341             dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
0342                  __func__, host_mode ? "host" : "device");
0343             break;
0344         }
0345 
0346         usleep_range(1000, 2000);
0347     }
0348 }
0349 
0350 /**
0351  * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
0352  * filter is enabled.
0353  *
0354  * @hsotg: Programming view of DWC_otg controller
0355  */
0356 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
0357 {
0358     u32 gsnpsid;
0359     u32 ghwcfg4;
0360 
0361     if (!dwc2_hw_is_otg(hsotg))
0362         return false;
0363 
0364     /* Check if core configuration includes the IDDIG filter. */
0365     ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
0366     if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
0367         return false;
0368 
0369     /*
0370      * Check if the IDDIG debounce filter is bypassed. Available
0371      * in core version >= 3.10a.
0372      */
0373     gsnpsid = dwc2_readl(hsotg, GSNPSID);
0374     if (gsnpsid >= DWC2_CORE_REV_3_10a) {
0375         u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
0376 
0377         if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
0378             return false;
0379     }
0380 
0381     return true;
0382 }
0383 
0384 /*
0385  * dwc2_enter_hibernation() - Common function to enter hibernation.
0386  *
0387  * @hsotg: Programming view of the DWC_otg controller
0388  * @is_host: True if core is in host mode.
0389  *
0390  * Return: 0 if successful, negative error code otherwise
0391  */
0392 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
0393 {
0394     if (is_host)
0395         return dwc2_host_enter_hibernation(hsotg);
0396     else
0397         return dwc2_gadget_enter_hibernation(hsotg);
0398 }
0399 
0400 /*
0401  * dwc2_exit_hibernation() - Common function to exit from hibernation.
0402  *
0403  * @hsotg: Programming view of the DWC_otg controller
0404  * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
0405  * @reset: Enabled in case of restore with reset.
0406  * @is_host: True if core is in host mode.
0407  *
0408  * Return: 0 if successful, negative error code otherwise
0409  */
0410 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
0411               int reset, int is_host)
0412 {
0413     if (is_host)
0414         return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
0415     else
0416         return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
0417 }
0418 
0419 /*
0420  * Do core a soft reset of the core.  Be careful with this because it
0421  * resets all the internal state machines of the core.
0422  */
0423 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
0424 {
0425     u32 greset;
0426     bool wait_for_host_mode = false;
0427 
0428     dev_vdbg(hsotg->dev, "%s()\n", __func__);
0429 
0430     /*
0431      * If the current mode is host, either due to the force mode
0432      * bit being set (which persists after core reset) or the
0433      * connector id pin, a core soft reset will temporarily reset
0434      * the mode to device. A delay from the IDDIG debounce filter
0435      * will occur before going back to host mode.
0436      *
0437      * Determine whether we will go back into host mode after a
0438      * reset and account for this delay after the reset.
0439      */
0440     if (dwc2_iddig_filter_enabled(hsotg)) {
0441         u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
0442         u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
0443 
0444         if (!(gotgctl & GOTGCTL_CONID_B) ||
0445             (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
0446             wait_for_host_mode = true;
0447         }
0448     }
0449 
0450     /* Core Soft Reset */
0451     greset = dwc2_readl(hsotg, GRSTCTL);
0452     greset |= GRSTCTL_CSFTRST;
0453     dwc2_writel(hsotg, greset, GRSTCTL);
0454 
0455     if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
0456         (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
0457         if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
0458                           GRSTCTL_CSFTRST, 10000)) {
0459             dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
0460                  __func__);
0461             return -EBUSY;
0462         }
0463     } else {
0464         if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
0465                         GRSTCTL_CSFTRST_DONE, 10000)) {
0466             dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",
0467                  __func__);
0468             return -EBUSY;
0469         }
0470         greset = dwc2_readl(hsotg, GRSTCTL);
0471         greset &= ~GRSTCTL_CSFTRST;
0472         greset |= GRSTCTL_CSFTRST_DONE;
0473         dwc2_writel(hsotg, greset, GRSTCTL);
0474     }
0475 
0476     /*
0477      * Switching from device mode to host mode by disconnecting
0478      * device cable core enters and exits form hibernation.
0479      * However, the fifo map remains not cleared. It results
0480      * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/
0481      * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2])
0482      * if in host mode we disconnect the micro a to b host
0483      * cable. Because core reset occurs.
0484      * To avoid the WARNING, fifo_map should be cleared
0485      * in dwc2_core_reset() function by taking into account configs.
0486      * fifo_map must be cleared only if driver is configured in
0487      * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE"
0488      * mode.
0489      */
0490     dwc2_clear_fifo_map(hsotg);
0491 
0492     /* Wait for AHB master IDLE state */
0493     if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
0494         dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
0495              __func__);
0496         return -EBUSY;
0497     }
0498 
0499     if (wait_for_host_mode && !skip_wait)
0500         dwc2_wait_for_mode(hsotg, true);
0501 
0502     return 0;
0503 }
0504 
0505 /**
0506  * dwc2_force_mode() - Force the mode of the controller.
0507  *
0508  * Forcing the mode is needed for two cases:
0509  *
0510  * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
0511  * controller to stay in a particular mode regardless of ID pin
0512  * changes. We do this once during probe.
0513  *
0514  * 2) During probe we want to read reset values of the hw
0515  * configuration registers that are only available in either host or
0516  * device mode. We may need to force the mode if the current mode does
0517  * not allow us to access the register in the mode that we want.
0518  *
0519  * In either case it only makes sense to force the mode if the
0520  * controller hardware is OTG capable.
0521  *
0522  * Checks are done in this function to determine whether doing a force
0523  * would be valid or not.
0524  *
0525  * If a force is done, it requires a IDDIG debounce filter delay if
0526  * the filter is configured and enabled. We poll the current mode of
0527  * the controller to account for this delay.
0528  *
0529  * @hsotg: Programming view of DWC_otg controller
0530  * @host: Host mode flag
0531  */
0532 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
0533 {
0534     u32 gusbcfg;
0535     u32 set;
0536     u32 clear;
0537 
0538     dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
0539 
0540     /*
0541      * Force mode has no effect if the hardware is not OTG.
0542      */
0543     if (!dwc2_hw_is_otg(hsotg))
0544         return;
0545 
0546     /*
0547      * If dr_mode is either peripheral or host only, there is no
0548      * need to ever force the mode to the opposite mode.
0549      */
0550     if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
0551         return;
0552 
0553     if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
0554         return;
0555 
0556     gusbcfg = dwc2_readl(hsotg, GUSBCFG);
0557 
0558     set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
0559     clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
0560 
0561     gusbcfg &= ~clear;
0562     gusbcfg |= set;
0563     dwc2_writel(hsotg, gusbcfg, GUSBCFG);
0564 
0565     dwc2_wait_for_mode(hsotg, host);
0566     return;
0567 }
0568 
0569 /**
0570  * dwc2_clear_force_mode() - Clears the force mode bits.
0571  *
0572  * After clearing the bits, wait up to 100 ms to account for any
0573  * potential IDDIG filter delay. We can't know if we expect this delay
0574  * or not because the value of the connector ID status is affected by
0575  * the force mode. We only need to call this once during probe if
0576  * dr_mode == OTG.
0577  *
0578  * @hsotg: Programming view of DWC_otg controller
0579  */
0580 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
0581 {
0582     u32 gusbcfg;
0583 
0584     if (!dwc2_hw_is_otg(hsotg))
0585         return;
0586 
0587     dev_dbg(hsotg->dev, "Clearing force mode bits\n");
0588 
0589     gusbcfg = dwc2_readl(hsotg, GUSBCFG);
0590     gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
0591     gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
0592     dwc2_writel(hsotg, gusbcfg, GUSBCFG);
0593 
0594     if (dwc2_iddig_filter_enabled(hsotg))
0595         msleep(100);
0596 }
0597 
0598 /*
0599  * Sets or clears force mode based on the dr_mode parameter.
0600  */
0601 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
0602 {
0603     switch (hsotg->dr_mode) {
0604     case USB_DR_MODE_HOST:
0605         /*
0606          * NOTE: This is required for some rockchip soc based
0607          * platforms on their host-only dwc2.
0608          */
0609         if (!dwc2_hw_is_otg(hsotg))
0610             msleep(50);
0611 
0612         break;
0613     case USB_DR_MODE_PERIPHERAL:
0614         dwc2_force_mode(hsotg, false);
0615         break;
0616     case USB_DR_MODE_OTG:
0617         dwc2_clear_force_mode(hsotg);
0618         break;
0619     default:
0620         dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
0621              __func__, hsotg->dr_mode);
0622         break;
0623     }
0624 }
0625 
0626 /*
0627  * dwc2_enable_acg - enable active clock gating feature
0628  */
0629 void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
0630 {
0631     if (hsotg->params.acg_enable) {
0632         u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
0633 
0634         dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
0635         pcgcctl1 |= PCGCCTL1_GATEEN;
0636         dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
0637     }
0638 }
0639 
0640 /**
0641  * dwc2_dump_host_registers() - Prints the host registers
0642  *
0643  * @hsotg: Programming view of DWC_otg controller
0644  *
0645  * NOTE: This function will be removed once the peripheral controller code
0646  * is integrated and the driver is stable
0647  */
0648 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
0649 {
0650 #ifdef DEBUG
0651     u32 __iomem *addr;
0652     int i;
0653 
0654     dev_dbg(hsotg->dev, "Host Global Registers\n");
0655     addr = hsotg->regs + HCFG;
0656     dev_dbg(hsotg->dev, "HCFG    @0x%08lX : 0x%08X\n",
0657         (unsigned long)addr, dwc2_readl(hsotg, HCFG));
0658     addr = hsotg->regs + HFIR;
0659     dev_dbg(hsotg->dev, "HFIR    @0x%08lX : 0x%08X\n",
0660         (unsigned long)addr, dwc2_readl(hsotg, HFIR));
0661     addr = hsotg->regs + HFNUM;
0662     dev_dbg(hsotg->dev, "HFNUM   @0x%08lX : 0x%08X\n",
0663         (unsigned long)addr, dwc2_readl(hsotg, HFNUM));
0664     addr = hsotg->regs + HPTXSTS;
0665     dev_dbg(hsotg->dev, "HPTXSTS     @0x%08lX : 0x%08X\n",
0666         (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
0667     addr = hsotg->regs + HAINT;
0668     dev_dbg(hsotg->dev, "HAINT   @0x%08lX : 0x%08X\n",
0669         (unsigned long)addr, dwc2_readl(hsotg, HAINT));
0670     addr = hsotg->regs + HAINTMSK;
0671     dev_dbg(hsotg->dev, "HAINTMSK    @0x%08lX : 0x%08X\n",
0672         (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
0673     if (hsotg->params.dma_desc_enable) {
0674         addr = hsotg->regs + HFLBADDR;
0675         dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
0676             (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
0677     }
0678 
0679     addr = hsotg->regs + HPRT0;
0680     dev_dbg(hsotg->dev, "HPRT0   @0x%08lX : 0x%08X\n",
0681         (unsigned long)addr, dwc2_readl(hsotg, HPRT0));
0682 
0683     for (i = 0; i < hsotg->params.host_channels; i++) {
0684         dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
0685         addr = hsotg->regs + HCCHAR(i);
0686         dev_dbg(hsotg->dev, "HCCHAR  @0x%08lX : 0x%08X\n",
0687             (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
0688         addr = hsotg->regs + HCSPLT(i);
0689         dev_dbg(hsotg->dev, "HCSPLT  @0x%08lX : 0x%08X\n",
0690             (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
0691         addr = hsotg->regs + HCINT(i);
0692         dev_dbg(hsotg->dev, "HCINT   @0x%08lX : 0x%08X\n",
0693             (unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
0694         addr = hsotg->regs + HCINTMSK(i);
0695         dev_dbg(hsotg->dev, "HCINTMSK    @0x%08lX : 0x%08X\n",
0696             (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
0697         addr = hsotg->regs + HCTSIZ(i);
0698         dev_dbg(hsotg->dev, "HCTSIZ  @0x%08lX : 0x%08X\n",
0699             (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
0700         addr = hsotg->regs + HCDMA(i);
0701         dev_dbg(hsotg->dev, "HCDMA   @0x%08lX : 0x%08X\n",
0702             (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
0703         if (hsotg->params.dma_desc_enable) {
0704             addr = hsotg->regs + HCDMAB(i);
0705             dev_dbg(hsotg->dev, "HCDMAB  @0x%08lX : 0x%08X\n",
0706                 (unsigned long)addr, dwc2_readl(hsotg,
0707                                 HCDMAB(i)));
0708         }
0709     }
0710 #endif
0711 }
0712 
0713 /**
0714  * dwc2_dump_global_registers() - Prints the core global registers
0715  *
0716  * @hsotg: Programming view of DWC_otg controller
0717  *
0718  * NOTE: This function will be removed once the peripheral controller code
0719  * is integrated and the driver is stable
0720  */
0721 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
0722 {
0723 #ifdef DEBUG
0724     u32 __iomem *addr;
0725 
0726     dev_dbg(hsotg->dev, "Core Global Registers\n");
0727     addr = hsotg->regs + GOTGCTL;
0728     dev_dbg(hsotg->dev, "GOTGCTL     @0x%08lX : 0x%08X\n",
0729         (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
0730     addr = hsotg->regs + GOTGINT;
0731     dev_dbg(hsotg->dev, "GOTGINT     @0x%08lX : 0x%08X\n",
0732         (unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
0733     addr = hsotg->regs + GAHBCFG;
0734     dev_dbg(hsotg->dev, "GAHBCFG     @0x%08lX : 0x%08X\n",
0735         (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
0736     addr = hsotg->regs + GUSBCFG;
0737     dev_dbg(hsotg->dev, "GUSBCFG     @0x%08lX : 0x%08X\n",
0738         (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
0739     addr = hsotg->regs + GRSTCTL;
0740     dev_dbg(hsotg->dev, "GRSTCTL     @0x%08lX : 0x%08X\n",
0741         (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
0742     addr = hsotg->regs + GINTSTS;
0743     dev_dbg(hsotg->dev, "GINTSTS     @0x%08lX : 0x%08X\n",
0744         (unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
0745     addr = hsotg->regs + GINTMSK;
0746     dev_dbg(hsotg->dev, "GINTMSK     @0x%08lX : 0x%08X\n",
0747         (unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
0748     addr = hsotg->regs + GRXSTSR;
0749     dev_dbg(hsotg->dev, "GRXSTSR     @0x%08lX : 0x%08X\n",
0750         (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
0751     addr = hsotg->regs + GRXFSIZ;
0752     dev_dbg(hsotg->dev, "GRXFSIZ     @0x%08lX : 0x%08X\n",
0753         (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
0754     addr = hsotg->regs + GNPTXFSIZ;
0755     dev_dbg(hsotg->dev, "GNPTXFSIZ   @0x%08lX : 0x%08X\n",
0756         (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
0757     addr = hsotg->regs + GNPTXSTS;
0758     dev_dbg(hsotg->dev, "GNPTXSTS    @0x%08lX : 0x%08X\n",
0759         (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
0760     addr = hsotg->regs + GI2CCTL;
0761     dev_dbg(hsotg->dev, "GI2CCTL     @0x%08lX : 0x%08X\n",
0762         (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
0763     addr = hsotg->regs + GPVNDCTL;
0764     dev_dbg(hsotg->dev, "GPVNDCTL    @0x%08lX : 0x%08X\n",
0765         (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
0766     addr = hsotg->regs + GGPIO;
0767     dev_dbg(hsotg->dev, "GGPIO   @0x%08lX : 0x%08X\n",
0768         (unsigned long)addr, dwc2_readl(hsotg, GGPIO));
0769     addr = hsotg->regs + GUID;
0770     dev_dbg(hsotg->dev, "GUID    @0x%08lX : 0x%08X\n",
0771         (unsigned long)addr, dwc2_readl(hsotg, GUID));
0772     addr = hsotg->regs + GSNPSID;
0773     dev_dbg(hsotg->dev, "GSNPSID     @0x%08lX : 0x%08X\n",
0774         (unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
0775     addr = hsotg->regs + GHWCFG1;
0776     dev_dbg(hsotg->dev, "GHWCFG1     @0x%08lX : 0x%08X\n",
0777         (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
0778     addr = hsotg->regs + GHWCFG2;
0779     dev_dbg(hsotg->dev, "GHWCFG2     @0x%08lX : 0x%08X\n",
0780         (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
0781     addr = hsotg->regs + GHWCFG3;
0782     dev_dbg(hsotg->dev, "GHWCFG3     @0x%08lX : 0x%08X\n",
0783         (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
0784     addr = hsotg->regs + GHWCFG4;
0785     dev_dbg(hsotg->dev, "GHWCFG4     @0x%08lX : 0x%08X\n",
0786         (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
0787     addr = hsotg->regs + GLPMCFG;
0788     dev_dbg(hsotg->dev, "GLPMCFG     @0x%08lX : 0x%08X\n",
0789         (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
0790     addr = hsotg->regs + GPWRDN;
0791     dev_dbg(hsotg->dev, "GPWRDN  @0x%08lX : 0x%08X\n",
0792         (unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
0793     addr = hsotg->regs + GDFIFOCFG;
0794     dev_dbg(hsotg->dev, "GDFIFOCFG   @0x%08lX : 0x%08X\n",
0795         (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
0796     addr = hsotg->regs + HPTXFSIZ;
0797     dev_dbg(hsotg->dev, "HPTXFSIZ    @0x%08lX : 0x%08X\n",
0798         (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
0799 
0800     addr = hsotg->regs + PCGCTL;
0801     dev_dbg(hsotg->dev, "PCGCTL  @0x%08lX : 0x%08X\n",
0802         (unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
0803 #endif
0804 }
0805 
0806 /**
0807  * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
0808  *
0809  * @hsotg: Programming view of DWC_otg controller
0810  * @num:   Tx FIFO to flush
0811  */
0812 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
0813 {
0814     u32 greset;
0815 
0816     dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
0817 
0818     /* Wait for AHB master IDLE state */
0819     if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
0820         dev_warn(hsotg->dev, "%s:  HANG! AHB Idle GRSCTL\n",
0821              __func__);
0822 
0823     greset = GRSTCTL_TXFFLSH;
0824     greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
0825     dwc2_writel(hsotg, greset, GRSTCTL);
0826 
0827     if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
0828         dev_warn(hsotg->dev, "%s:  HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
0829              __func__);
0830 
0831     /* Wait for at least 3 PHY Clocks */
0832     udelay(1);
0833 }
0834 
0835 /**
0836  * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
0837  *
0838  * @hsotg: Programming view of DWC_otg controller
0839  */
0840 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
0841 {
0842     u32 greset;
0843 
0844     dev_vdbg(hsotg->dev, "%s()\n", __func__);
0845 
0846     /* Wait for AHB master IDLE state */
0847     if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
0848         dev_warn(hsotg->dev, "%s:  HANG! AHB Idle GRSCTL\n",
0849              __func__);
0850 
0851     greset = GRSTCTL_RXFFLSH;
0852     dwc2_writel(hsotg, greset, GRSTCTL);
0853 
0854     /* Wait for RxFIFO flush done */
0855     if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
0856         dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
0857              __func__);
0858 
0859     /* Wait for at least 3 PHY Clocks */
0860     udelay(1);
0861 }
0862 
0863 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
0864 {
0865     if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
0866         return false;
0867     else
0868         return true;
0869 }
0870 
0871 /**
0872  * dwc2_enable_global_interrupts() - Enables the controller's Global
0873  * Interrupt in the AHB Config register
0874  *
0875  * @hsotg: Programming view of DWC_otg controller
0876  */
0877 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
0878 {
0879     u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
0880 
0881     ahbcfg |= GAHBCFG_GLBL_INTR_EN;
0882     dwc2_writel(hsotg, ahbcfg, GAHBCFG);
0883 }
0884 
0885 /**
0886  * dwc2_disable_global_interrupts() - Disables the controller's Global
0887  * Interrupt in the AHB Config register
0888  *
0889  * @hsotg: Programming view of DWC_otg controller
0890  */
0891 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
0892 {
0893     u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
0894 
0895     ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
0896     dwc2_writel(hsotg, ahbcfg, GAHBCFG);
0897 }
0898 
0899 /* Returns the controller's GHWCFG2.OTG_MODE. */
0900 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
0901 {
0902     u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
0903 
0904     return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
0905         GHWCFG2_OP_MODE_SHIFT;
0906 }
0907 
0908 /* Returns true if the controller is capable of DRD. */
0909 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
0910 {
0911     unsigned int op_mode = dwc2_op_mode(hsotg);
0912 
0913     return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
0914         (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
0915         (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
0916 }
0917 
0918 /* Returns true if the controller is host-only. */
0919 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
0920 {
0921     unsigned int op_mode = dwc2_op_mode(hsotg);
0922 
0923     return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
0924         (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
0925 }
0926 
0927 /* Returns true if the controller is device-only. */
0928 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
0929 {
0930     unsigned int op_mode = dwc2_op_mode(hsotg);
0931 
0932     return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
0933         (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
0934 }
0935 
0936 /**
0937  * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
0938  * @hsotg: Programming view of DWC_otg controller.
0939  * @offset: Register's offset where bit/bits must be set.
0940  * @mask: Mask of the bit/bits which must be set.
0941  * @timeout: Timeout to wait.
0942  *
0943  * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
0944  */
0945 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
0946                 u32 timeout)
0947 {
0948     u32 i;
0949 
0950     for (i = 0; i < timeout; i++) {
0951         if (dwc2_readl(hsotg, offset) & mask)
0952             return 0;
0953         udelay(1);
0954     }
0955 
0956     return -ETIMEDOUT;
0957 }
0958 
0959 /**
0960  * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
0961  * @hsotg: Programming view of DWC_otg controller.
0962  * @offset: Register's offset where bit/bits must be set.
0963  * @mask: Mask of the bit/bits which must be set.
0964  * @timeout: Timeout to wait.
0965  *
0966  * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
0967  */
0968 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
0969                   u32 timeout)
0970 {
0971     u32 i;
0972 
0973     for (i = 0; i < timeout; i++) {
0974         if (!(dwc2_readl(hsotg, offset) & mask))
0975             return 0;
0976         udelay(1);
0977     }
0978 
0979     return -ETIMEDOUT;
0980 }
0981 
0982 /*
0983  * Initializes the FSLSPClkSel field of the HCFG register depending on the
0984  * PHY type
0985  */
0986 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
0987 {
0988     u32 hcfg, val;
0989 
0990     if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
0991          hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
0992          hsotg->params.ulpi_fs_ls) ||
0993         hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
0994         /* Full speed PHY */
0995         val = HCFG_FSLSPCLKSEL_48_MHZ;
0996     } else {
0997         /* High speed PHY running at full speed or high speed */
0998         val = HCFG_FSLSPCLKSEL_30_60_MHZ;
0999     }
1000 
1001     dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
1002     hcfg = dwc2_readl(hsotg, HCFG);
1003     hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
1004     hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
1005     dwc2_writel(hsotg, hcfg, HCFG);
1006 }
1007 
1008 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1009 {
1010     u32 usbcfg, ggpio, i2cctl;
1011     int retval = 0;
1012 
1013     /*
1014      * core_init() is now called on every switch so only call the
1015      * following for the first time through
1016      */
1017     if (select_phy) {
1018         dev_dbg(hsotg->dev, "FS PHY selected\n");
1019 
1020         usbcfg = dwc2_readl(hsotg, GUSBCFG);
1021         if (!(usbcfg & GUSBCFG_PHYSEL)) {
1022             usbcfg |= GUSBCFG_PHYSEL;
1023             dwc2_writel(hsotg, usbcfg, GUSBCFG);
1024 
1025             /* Reset after a PHY select */
1026             retval = dwc2_core_reset(hsotg, false);
1027 
1028             if (retval) {
1029                 dev_err(hsotg->dev,
1030                     "%s: Reset failed, aborting", __func__);
1031                 return retval;
1032             }
1033         }
1034 
1035         if (hsotg->params.activate_stm_fs_transceiver) {
1036             ggpio = dwc2_readl(hsotg, GGPIO);
1037             if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
1038                 dev_dbg(hsotg->dev, "Activating transceiver\n");
1039                 /*
1040                  * STM32F4x9 uses the GGPIO register as general
1041                  * core configuration register.
1042                  */
1043                 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
1044                 dwc2_writel(hsotg, ggpio, GGPIO);
1045             }
1046         }
1047     }
1048 
1049     /*
1050      * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1051      * do this on HNP Dev/Host mode switches (done in dev_init and
1052      * host_init).
1053      */
1054     if (dwc2_is_host_mode(hsotg))
1055         dwc2_init_fs_ls_pclk_sel(hsotg);
1056 
1057     if (hsotg->params.i2c_enable) {
1058         dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
1059 
1060         /* Program GUSBCFG.OtgUtmiFsSel to I2C */
1061         usbcfg = dwc2_readl(hsotg, GUSBCFG);
1062         usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
1063         dwc2_writel(hsotg, usbcfg, GUSBCFG);
1064 
1065         /* Program GI2CCTL.I2CEn */
1066         i2cctl = dwc2_readl(hsotg, GI2CCTL);
1067         i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
1068         i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
1069         i2cctl &= ~GI2CCTL_I2CEN;
1070         dwc2_writel(hsotg, i2cctl, GI2CCTL);
1071         i2cctl |= GI2CCTL_I2CEN;
1072         dwc2_writel(hsotg, i2cctl, GI2CCTL);
1073     }
1074 
1075     return retval;
1076 }
1077 
1078 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1079 {
1080     u32 usbcfg, usbcfg_old;
1081     int retval = 0;
1082 
1083     if (!select_phy)
1084         return 0;
1085 
1086     usbcfg = dwc2_readl(hsotg, GUSBCFG);
1087     usbcfg_old = usbcfg;
1088 
1089     /*
1090      * HS PHY parameters. These parameters are preserved during soft reset
1091      * so only program the first time. Do a soft reset immediately after
1092      * setting phyif.
1093      */
1094     switch (hsotg->params.phy_type) {
1095     case DWC2_PHY_TYPE_PARAM_ULPI:
1096         /* ULPI interface */
1097         dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
1098         usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
1099         usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
1100         if (hsotg->params.phy_ulpi_ddr)
1101             usbcfg |= GUSBCFG_DDRSEL;
1102 
1103         /* Set external VBUS indicator as needed. */
1104         if (hsotg->params.oc_disable)
1105             usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
1106                    GUSBCFG_INDICATORPASSTHROUGH);
1107         break;
1108     case DWC2_PHY_TYPE_PARAM_UTMI:
1109         /* UTMI+ interface */
1110         dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
1111         usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
1112         if (hsotg->params.phy_utmi_width == 16)
1113             usbcfg |= GUSBCFG_PHYIF16;
1114         break;
1115     default:
1116         dev_err(hsotg->dev, "FS PHY selected at HS!\n");
1117         break;
1118     }
1119 
1120     if (usbcfg != usbcfg_old) {
1121         dwc2_writel(hsotg, usbcfg, GUSBCFG);
1122 
1123         /* Reset after setting the PHY parameters */
1124         retval = dwc2_core_reset(hsotg, false);
1125         if (retval) {
1126             dev_err(hsotg->dev,
1127                 "%s: Reset failed, aborting", __func__);
1128             return retval;
1129         }
1130     }
1131 
1132     return retval;
1133 }
1134 
1135 static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg)
1136 {
1137     u32 usbcfg;
1138 
1139     if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI)
1140         return;
1141 
1142     usbcfg = dwc2_readl(hsotg, GUSBCFG);
1143 
1144     usbcfg &= ~GUSBCFG_USBTRDTIM_MASK;
1145     if (hsotg->params.phy_utmi_width == 16)
1146         usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT;
1147     else
1148         usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT;
1149 
1150     dwc2_writel(hsotg, usbcfg, GUSBCFG);
1151 }
1152 
1153 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1154 {
1155     u32 usbcfg;
1156     u32 otgctl;
1157     int retval = 0;
1158 
1159     if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
1160          hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
1161         hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1162         /* If FS/LS mode with FS/LS PHY */
1163         retval = dwc2_fs_phy_init(hsotg, select_phy);
1164         if (retval)
1165             return retval;
1166     } else {
1167         /* High speed PHY */
1168         retval = dwc2_hs_phy_init(hsotg, select_phy);
1169         if (retval)
1170             return retval;
1171 
1172         if (dwc2_is_device_mode(hsotg))
1173             dwc2_set_turnaround_time(hsotg);
1174     }
1175 
1176     if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1177         hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1178         hsotg->params.ulpi_fs_ls) {
1179         dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
1180         usbcfg = dwc2_readl(hsotg, GUSBCFG);
1181         usbcfg |= GUSBCFG_ULPI_FS_LS;
1182         usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
1183         dwc2_writel(hsotg, usbcfg, GUSBCFG);
1184     } else {
1185         usbcfg = dwc2_readl(hsotg, GUSBCFG);
1186         usbcfg &= ~GUSBCFG_ULPI_FS_LS;
1187         usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
1188         dwc2_writel(hsotg, usbcfg, GUSBCFG);
1189     }
1190 
1191     if (!hsotg->params.activate_ingenic_overcurrent_detection) {
1192         if (dwc2_is_host_mode(hsotg)) {
1193             otgctl = readl(hsotg->regs + GOTGCTL);
1194             otgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL;
1195             writel(otgctl, hsotg->regs + GOTGCTL);
1196         }
1197     }
1198 
1199     return retval;
1200 }
1201 
1202 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1203 MODULE_AUTHOR("Synopsys, Inc.");
1204 MODULE_LICENSE("Dual BSD/GPL");
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